Neural network circuit calibration method and design method
By acquiring and applying correction coefficients to correct nonlinearity in neural network circuits, the output deviation problem caused by memristor arrays is solved, and the network recognition rate is improved and the recognition efficiency is maintained.
Patent Information
- Application Number
- CN202011056258.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-09-30
- Publication Date
- 2025-03-21
- Estimated Expiration
- 2040-09-30
AI Technical Summary
In neural network circuits, due to the nonlinear characteristics of the memristor array, there is a large deviation between the output and the ideal output, which reduces the network recognition rate of the neural network circuit.
By obtaining the correction coefficients that characterize the relationship between the non-ideal output of the calculation circuit and the ideal output and adding it to the non-linear function circuit, the correction is performed by changing the circuit parameters of the neural network circuit to weaken or eliminate the non-linearity introduced by the calculation circuit.
The network recognition rate of neural network circuits is improved, ensuring that the recognition efficiency is not reduced, and at the same time, the deviation introduced by the nonlinearity of the calculation circuit is weakened.