Organic light emitting display device

Abstract

An organic light-emitting display device includes: a driving transistor in each of a plurality of pixel areas defined on a substrate; a reflective electrode on the driving transistor, the reflective electrode being electrically connected to a gate electrode of the driving transistor; a dielectric layer on the reflective electrode; a first electrode on the dielectric layer, the first electrode being electrically connected to a source electrode of the driving transistor and facing the reflective electrode; an organic light-emitting layer on the first electrode; and a second electrode on the organic light-emitting layer.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0125158, filed on October 10, 2019, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0002] The present invention relates to an organic light emitting display (OLED). Background Art

[0003] Recently, flat panel display devices having excellent advantages such as thin profile, light weight, low power consumption, etc. have been widely developed and applied to various fields.

[0004] Among flat panel display devices, an organic light emitting display device (OLED) may be referred to as an organic electroluminescent display device, in which charges are injected into a light emitting layer formed between a cathode serving as an electron injection electrode and an anode serving as a hole injection electrode, thereby forming electron-hole pairs, and light is emitted when the electron-hole pairs disappear.

[0005] As the resolution of an organic light emitting display device increases, it is difficult to ensure the capacitance of a storage capacitor, and thus, it is necessary to increase the storage capacitance. Summary of the invention

[0006] Accordingly, the present invention is directed to an organic light emitting display (OLED) device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0007] An object of the present invention is to provide an OLED capable of improving its storage capacitance.

[0008] Additional features and advantages of the present invention will be listed in the following description, and some of these features and advantages will become apparent from the following description or can be understood through the implementation of the present invention. These advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification, claims and drawings.

[0009] To achieve these and other advantages and in accordance with the intent of the present invention, as embodied and generally described herein, an organic light emitting display device includes: a driving transistor in each of a plurality of pixel areas defined on a substrate; a reflective electrode on the driving transistor, the reflective electrode being electrically connected to a gate electrode of the driving transistor; a dielectric layer on the reflective electrode; a first electrode on the dielectric layer, the first electrode being electrically connected to a source electrode of the driving transistor and facing the reflective electrode; an organic light emitting layer on the first electrode; and a second electrode on the organic light emitting layer.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this application, illustrate embodiments of the present invention and together with the description serve to explain the principle of the present invention. In the drawings:

[0012] Figure 1 is a plan view schematically illustrating an OLED according to a first embodiment of the present invention;

[0013] Figure 2 is a circuit diagram of an example of a pixel region according to a first embodiment of the present invention;

[0014] Figure 3 is a cross-sectional view schematically illustrating an OLED according to a first embodiment of the present invention;

[0015] Figure 4 is a cross-sectional view schematically illustrating an OLED according to a second embodiment of the present invention;

[0016] Figure 5 is a cross-sectional view schematically illustrating an OLED according to a third embodiment of the present invention;

[0017] Figure 6 Is magnification Figure 5 A cross-sectional view of a storage capacitor;

[0018] Figure 7 is a plan view schematically illustrating a reflective electrode and a first electrode forming a storage capacitor according to a third embodiment of the present invention;

[0019] Figure 8 is a cross-sectional view schematically illustrating an OLED according to a fourth embodiment of the present invention. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. The same or similar reference numerals may be used throughout the drawings to refer to the same or similar parts.

[0021] <First Embodiment>

[0022] Figure 1 is a plan view schematically illustrating an OLED according to a first embodiment of the present invention. Figure 2 is a circuit diagram of an example of a pixel region according to the first embodiment of the present invention.

[0023] Reference Figure 1 and Figure 2 In the OLED 10 of the present invention, a plurality of pixel regions P may be arranged in a matrix form in a display region to display an image.

[0024] The plurality of pixel regions P may include pixel regions for constituting a unit pixel and displaying a first color, a second color, and a third color as different colors, for example, an R pixel region P1, a G pixel region P2, and a B pixel region P3 that display red, green, and blue, respectively. For the purpose of explanation, the R pixel region P1, the G pixel region P2, and the B pixel region P3 may be referred to as a first pixel region P1, a second pixel region P2, and a third pixel region P3, respectively.

[0025] The first pixel region P1 , the second pixel region P2 , and the third pixel region P3 may be alternately arranged along a direction.

[0026] The pixel region P may include a light emitting diode OD and a driving element for driving the light emitting diode OD, and the driving element may include a storage capacitor Cst and a plurality of transistors Ts and Td.

[0027] Reference Figure 2 The circuit configuration of the pixel region P is further explained.

[0028] In each pixel region P of the OLED 10 of the present embodiment, a plurality of transistors such as a switching transistor Ts and a driving transistor Td, a storage capacitor Cst, and a light emitting diode OD may be formed.

[0029] The switching transistor Ts may be connected to a gate line GL and a data line DL that cross each other to define a pixel region P. A gate electrode of the switching transistor Ts may be connected to the gate line GL, and a source electrode of the switching transistor Ts may be connected to the data line DL.

[0030] The driving transistor Td may be electrically connected to the switching transistor Ts. For example, a gate electrode of the driving transistor Td may be connected to a drain electrode of the switching transistor Ts.

[0031] The driving transistor Td may be connected to the light emitting diode OD. For example, a source electrode of the driving transistor Td may be connected to a first electrode that is an anode of the light emitting diode OD.

[0032] The drain electrode of the driving transistor Td may be electrically connected to the driving voltage line VDL and provided with the first driving voltage VDD. For example, the drain electrode of the driving transistor Td may be connected to the driving voltage line VDL transmitting the first driving voltage VDD as a high potential driving voltage.

[0033] The light emitting diode OD may be configured such that a second electrode serving as a cathode thereof is supplied with a second driving voltage VSS serving as a low potential driving voltage.

[0034] The storage capacitor Cst may be connected between the gate electrode and the source electrode of the driving transistor Td.

[0035] For example, a first storage electrode as one electrode of the storage capacitor Cst may be connected to a gate electrode of the driving transistor Td. A second storage electrode as the other electrode of the storage capacitor Cst may be connected to a source electrode of the driving transistor Td.

[0036] For the pixel region P configured as above, when a gate signal of a turn-on level is applied to the gate line GL, the switching transistor Ts is turned on, and the data signal transmitted through the data line DL is applied to the gate electrode of the driving transistor Td. Therefore, the driving transistor Td is turned on, and a driving current whose amplitude corresponds to the amplitude of the data signal is applied to the light emitting diode OD through the channel of the driving transistor Td. Therefore, light having a brightness corresponding to the applied driving current is generated from the light emitting diode OD.

[0037] A voltage between the gate electrode and the source electrode of the driving transistor Td may be stored in the storage capacitor Cst, and the stored voltage may be maintained until the next frame.

[0038] By way of example, Figure 2 Alternatively, at least one transistor other than the switching transistor Ts and the driving transistor Td may be added to the pixel region P.

[0039] The storage capacitor Cst of the present embodiment may be formed by the first electrode of the light emitting diode OD and the reflective electrode located below the first electrode. Therefore, a desired storage capacitance may be effectively obtained.

[0040] The structure of the OLED 10 capable of ensuring the capacitance of the storage capacitor Cst is explained in detail below.

[0041] Figure 3 is a cross-sectional view schematically illustrating an OLED according to a first embodiment of the present invention.

[0042] Reference Figures 1 to 3 , the OLED 10 may be a top emission type display device. In other words, the OLED 10 may be configured to emit light upward from the substrate 101.

[0043] The substrate 101 may be a silicon substrate, but is not limited thereto. Alternatively, the substrate 101 may be a glass substrate or a plastic substrate. In this embodiment, a silicon substrate made of crystalline silicon (eg, single crystal silicon) used as a semiconductor is given by way of example.

[0044] In some embodiments, when the substrate 101 formed of silicon is used, there is an advantage of effectively realizing a small-sized display device requiring high resolution. However, in other embodiments, other substrates besides silicon may be used to achieve the same technical advantages.

[0045] The substrate 101 formed of silicon may be a lightly doped P (positive) or N (negative) type substrate.

[0046] On the substrate 101 formed of silicon, an active portion (or active region) serving as a semiconductor layer corresponding to each transistor is formed in the pixel region P. For example, at a location where the driving transistor Td is formed, an active portion 105 of the driving transistor Td may be formed.

[0047] The active portion 105 may include a channel region 105a, and a drain region 105b and a source region 105c located at both sides of the channel region 105a. The drain region 105b and the source region 105c may be formed as N or P type highly doped regions.

[0048] On the substrate 101 having the active portion 105, a gate insulating layer 111 made of an insulating material may be formed. The gate insulating layer 111 may correspond to the channel region 105a.

[0049] A first metal layer made of a first metal material may be formed on the gate insulating layer 111. For example, the first metal layer may include a gate electrode 113 located on the gate insulating layer 111 corresponding to the channel region 105a.

[0050] The first metal layer may include a gate line GL connected to the switching transistor Ts.

[0051] On the first metal layer including the gate electrode 113, a first passivation layer 121 as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the first passivation layer 121 as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0052] In the first passivation layer 121, first and second semiconductor contact holes CH1 and CH2 respectively exposing the drain and source regions 105b and 105c of the active portion 105 may be formed. The first and second semiconductor contact holes CH1 and CH2 may be located at both sides of the gate electrode 113 and spaced apart from the gate electrode 113.

[0053] A first gate connection contact hole CHg1 , which is a contact hole exposing the gate electrode 113 , may be formed in the first passivation layer 121 .

[0054] A second metal layer made of a second metal material may be formed on the first passivation layer 121. For example, the second metal layer may include a drain electrode 131 and a source electrode 133. The drain electrode 131 and the source electrode 133 may contact the drain region 105b and the source region 105c through the first semiconductor contact hole CH1 and the second semiconductor contact hole CH2, respectively.

[0055] The second metal layer may include a first gate connection pattern 135. The first gate connection pattern 135 may contact the gate electrode 113 through the first gate connection contact hole CHg1.

[0056] On the second metal layer including the drain and source electrodes 131 and 133 and the first gate connection pattern 135, a second passivation layer 122 as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the second passivation layer 122 as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0057] In the second passivation layer 122 , a first drain connection contact hole CHd1 and a first source connection contact hole CHs1 exposing the drain electrode 131 and the source electrode 133 , respectively, may be formed.

[0058] A second gate connection contact hole CHg2 , which is a contact hole exposing the first gate connection pattern 135 , may be formed in the second passivation layer 122 .

[0059] A third metal layer made of a third metal material may be formed on the second passivation layer 122. For example, the third metal layer may include a data line DL connected to the switching transistor Ts.

[0060] The third metal layer may include a first drain connection pattern 141 , a first source connection pattern 143 , and a second gate connection pattern 145 .

[0061] The first drain connection pattern 141 may contact the drain electrode 131 through the first drain connection contact hole CHd1. The first source connection pattern 143 may contact the source electrode 133 through the first source connection contact hole CHs1.

[0062] The second gate connection pattern 145 may contact the first gate connection pattern 135 through the second gate connection contact hole CHg2 .

[0063] On the third metal layer including the first drain connection pattern 141, the first source connection pattern 143, and the second gate connection pattern 145, a third passivation layer 123 as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the third passivation layer 123 as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0064] In the third passivation layer 123 , a second drain connection contact hole CHd2 and a second source connection contact hole CHs2 exposing the first drain connection pattern 141 and the first source connection pattern 143 , respectively, may be formed.

[0065] A third gate connection contact hole CHg3 , which is a contact hole exposing the second gate connection pattern 145 , may be formed in the third passivation layer 123 .

[0066] A fourth metal layer made of a fourth metal material may be formed on the third passivation layer 123. For example, the fourth metal layer may include a second drain connection pattern 151, a second source connection pattern 153, and a third gate connection pattern 155.

[0067] The second drain connection pattern 151 may contact the first drain connection pattern 141 through the second drain connection contact hole CHd2. The second source connection pattern 153 may contact the first source connection pattern 143 through the second source connection contact hole CHs2.

[0068] The third gate connection pattern 155 may contact the second gate connection pattern 145 through the third gate connection contact hole CHg3 .

[0069] On the fourth metal layer including the second drain connection pattern 151, the second source connection pattern 153, and the third gate connection pattern 155, a fourth passivation layer 124 as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the fourth passivation layer 124 as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0070] In the fourth passivation layer 124 , a third drain connection contact hole CHd3 and a third source connection contact hole CHs3 exposing the second drain connection pattern 151 and the second source connection pattern 153 , respectively, may be formed.

[0071] A fourth gate connection contact hole CHg4 , which is a contact hole exposing the third gate connection pattern 155 , may be formed in the fourth passivation layer 124 .

[0072] A fifth metal layer made of a fifth metal material may be formed on the fourth passivation layer 124. For example, the fifth metal layer may include a third drain connection pattern 161, a third source connection pattern 163, and a fourth gate connection pattern 165.

[0073] The third drain connection pattern 161 may contact the second drain connection pattern 151 through the third drain connection contact hole CHd3. The third source connection pattern 163 may contact the second source connection pattern 153 through the third source connection contact hole CHs3.

[0074] The fourth gate connection pattern 165 may contact the third gate connection pattern 155 through the fourth gate connection contact hole CHg4 .

[0075] On the fifth metal layer including the third drain connection pattern 161, the third source connection pattern 163, and the fourth gate connection pattern 165, a fifth passivation layer 125 as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the fifth passivation layer 125 as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0076] In the fifth passivation layer 125 , a fourth drain connection contact hole CHd4 and a fourth source connection contact hole CHs4 exposing the third drain connection pattern 161 and the third source connection pattern 163 , respectively, may be formed.

[0077] A fifth gate connection contact hole CHg5 , which is a contact hole exposing the fourth gate connection pattern 165 , may be formed in the fifth passivation layer 125 .

[0078] A sixth metal layer made of a sixth metal material may be formed on the fifth passivation layer 125. For example, the sixth metal layer may include a fourth drain connection pattern 171, a fourth source connection pattern 173, and a fifth gate connection pattern 175.

[0079] The fourth drain connection pattern 171 may contact the third drain connection pattern 161 through the fourth drain connection contact hole CHd4. The fourth source connection pattern 173 may contact the third source connection pattern 163 through the fourth source connection contact hole CHs4.

[0080] The fifth gate connection pattern 175 may contact the fourth gate connection pattern 165 through the fifth gate connection contact hole CHg5 .

[0081] On the sixth metal layer, a driving voltage line VDL for transmitting the first driving voltage VDD may be formed. A fourth drain connection pattern 171 may be configured to extend from the driving voltage line VDL.

[0082] On the sixth metal layer including the fourth drain connection pattern 171, the fourth source connection pattern 173, and the fifth gate connection pattern 175, a sixth passivation layer 126 (or coating layer) as an insulating layer made of an insulating material may be formed over the entire substrate 101. However, in other embodiments, the sixth passivation layer 126 (or coating layer) as an insulating layer made of an insulating material may be formed to at least partially cover the substrate 101.

[0083] In the sixth passivation layer 126 , a source contact hole CHs and a gate contact hole CHg exposing the fourth source connection pattern 173 and the fifth gate connection pattern 175 , respectively, may be formed.

[0084] The sixth passivation layer 126 may serve as a planarization layer and have a flat (or uniform) top surface.

[0085] As described above, a plurality of metal layers may be stacked under the sixth passivation layer 126 to form electrodes for constituting driving elements such as transistors in the pixel region, and various signals such as data signals and scanning signals including gate signals for transmitting driving the pixel region, and signal lines for transmitting power supply voltage signals including driving voltages, and in this embodiment, the first to sixth metal layers are stacked by way of example. The number of stacked metal layers may vary depending on the types of driving elements and signal lines required.

[0086] The reflective electrode 180 may be formed on the sixth passivation layer 126. The reflective electrode 180 may be formed in a patterned form at each pixel region P. In this regard, the reflective electrodes 180 of adjacent pixel regions may be spaced apart from each other and electrically disconnected.

[0087] The metal material having a reflective property of the reflective electrode 180 may be, for example, Al, Ag, Ti, or APC (Al—Pd—Cu), but is not limited thereto.

[0088] The reflective electrode 180 may serve to reflect upwardly the light generated from the light emitting diode OD and propagating downwardly.

[0089] In addition, the reflective electrode 180 may function as a first storage electrode which is one storage electrode of the storage capacitor Cst.

[0090] In this regard, the reflective electrode 180 may contact the fifth gate connection pattern 175 through the gate contact hole CHg.

[0091] Therefore, the reflective electrode 180 may be electrically connected to the gate electrode 113 of the driving transistor Td located therebelow, and thus function as a first storage electrode of the storage capacitor Cst.

[0092] A dielectric layer 185 may be formed on the reflective electrode 180. The dielectric layer 185 may be formed of an organic insulating material or an inorganic insulating material. The dielectric layer 185 may be formed in a patterned manner in each pixel region P, for example, but is not limited thereto.

[0093] In the dielectric layer 185 and the sixth passivation layer 126 , a source contact hole CHs exposing the fourth source connection pattern 173 may be formed.

[0094] A first electrode 190 of the light emitting diode OD may be formed on the dielectric layer 185. The first electrode 190 may be formed in each pixel region P in a patterned form.

[0095] The first electrode 190 may be formed of a transparent conductive material such as ITO.

[0096] The first electrode 190 may contact the fourth source connection pattern 173 through the source contact hole CHs.

[0097] The first electrode 190 may be electrically connected to the source electrode 133 of the driving transistor Td.

[0098] The first electrode 190 electrically connected to the source electrode 133 may be positioned in the pixel region P to face the reflective electrode 180 with a dielectric layer 185 therebetween.

[0099] Therefore, the first electrode 190 may function as a second storage electrode as the other electrode of the storage capacitor Cst, the second storage electrode being connected to the source electrode 133 of the driving transistor Td.

[0100] A bank 200 (or a partition wall) may be formed on the first electrode 190 , the bank 200 surrounding the pixel region P along a boundary of the pixel region P. As shown in FIG.

[0101] The bank 200 may include an opening exposing the first electrode 190 of the pixel region P, and cover an edge of the first electrode 190. By the opening of the bank 200, a light emitting area EA for substantially generating light in the pixel region P may be defined.

[0102] The edge of the reflective electrode 180 may extend below the bank 200 .

[0103] An organic light emitting layer 210 may be formed on the first electrode 190 exposed through the opening of the bank 200. The organic light emitting layer 210 may be composed of a multi-layered structure including a light emitting material layer.

[0104] The organic light emitting layer 210 may be formed per pixel region P. Alternatively, the organic light emitting layer 210 may be continuously formed over the entire display region and correspond to all pixel regions P. In the present embodiment, the organic light emitting layer 210 formed over the entire display region is given by way of example, in which case the organic light emitting layer 210 may be formed to extend along the first electrode 190 and the bank 200. However, other arrangements of the organic light emitting layer 210 may be designed. For example, the organic light emitting layer 210 may be continuously formed to at least partially cover the display region.

[0105] The organic light emitting layer 210 may be a white organic light emitting layer 210 emitting white. Since the organic light emitting layer 210 may be continuously formed on all pixel regions P, the organic light emitting layers 210 located in the first to third pixel regions P1 to P3 displaying different colors may emit the same white light.

[0106] Alternatively, the organic light emitting layer 210 may be formed per pixel region P. In this case, the organic light emitting layer 210 located in the first to third pixel regions P1 to P3 displaying different colors may emit light of the colors of the respective pixel regions P1 to P3.

[0107] The second electrode 220 may be formed on the organic light emitting layer 210. In some embodiments, the second electrode 220 may be formed over the entire substrate 101.

[0108] The second electrode 220 may be a transparent electrode having a transparent property, and in this case, the second electrode 220 may be formed of a transparent conductive material such as ITO.

[0109] The encapsulation layer 300 may be formed on the second electrode 220 to encapsulate the substrate 101 having the second electrode 220. In some embodiments, the encapsulation layer 300 may be formed over the entire substrate 101. The encapsulation layer 300 may prevent penetration of external moisture and oxygen and improve reliability.

[0110] In addition, the encapsulation layer 300 may planarize the substrate 101 having the second electrode 220 .

[0111] The encapsulation layer 300 may be formed of a single layer structure or a multi-layer structure using at least one of an inorganic insulating material and an organic insulating material.

[0112] A color filter layer 310 may be formed on the encapsulation layer 300. The color filter layer 310 may be used to generate light of a color of each pixel region P.

[0113] In this regard, the color filter layer 310 may include a first color filter pattern 310r, a second color filter pattern 310g, and a third color filter pattern 310b corresponding to the first pixel region P1, the second pixel region P2, and the third pixel region P3, respectively, to produce red, green, and blue colors of the first pixel region P1, the second pixel region P2, and the third pixel region P3.

[0114] Therefore, white light from the light emitting diode OD emitting white light passes through the color filter patterns 310r, 310g, and 310b to output red light, green light, and blue light.

[0115] A black matrix 315 may be formed on the encapsulation layer 300. The black matrix 315 may be positioned along a boundary of the pixel region P and between adjacent color filter patterns.

[0116] In the above-described embodiment, in the top emission type OLED 10, the storage capacitor Cst may be formed above the array stack structure for driving the light emitting diode OD and below the light emitting diode OD, and the array stack structure may include a driving element and a line and pattern for transmitting a signal. In this case, the reflective electrode 180 may be used as one electrode of the storage capacitor Cst, and the first electrode 190 of the light emitting diode OD may be used as the other electrode of the storage capacitor Cst.

[0117] In this way, by arranging the storage capacitor Cst above the array stacking structure, the storage capacitor Cst is not limited by the area or design of the array stacking structure, and thus the storage capacitor Cst can be formed to have as large an area as possible. Therefore, the capacitance of the storage capacitor Cst required in the high-resolution mode can be fully ensured. Similarly, the array stacking structure is not limited by the area or design of the storage capacitor Cst, and thus the layout freedom of the array stacking structure can be improved.

[0118] In addition, since the reflective electrode 180 and the first electrode 190 are used as the storage electrode, no additional electrode is required to constitute the storage capacitor Cst. Therefore, the production process and cost can be reduced, and the production efficiency can be ensured.

[0119] <Second Embodiment>

[0120] Figure 4 is a cross-sectional view schematically illustrating an OLED according to a second embodiment of the present invention.

[0121] exist Figure 4 , for the purpose of explanation, components of the OLED related to the present embodiment are shown, and the array stacked structure under the reflective electrode 180 is omitted.

[0122] Explanations of portions similar to those of the above first embodiment may be omitted.

[0123] Reference Figure 4 The OLED 10 of this embodiment may include a microcavity structure. The microcavity structure realizes a microcavity effect that improves color purity and light efficiency through constructive interference of light.

[0124] In order to constitute the microcavity structure, the second electrode 220 may include a semi-transparent (or semi-reflective) electrode layer having a semi-transparent (or semi-reflective) property.

[0125] Therefore, in each pixel region, light reflected and constructively interfered between the reflective electrode 180 and the second electrode 220 located below and above the organic light emitting layer 210 may pass through the second electrode 220 having a semi-transparent property and be output upward.

[0126] Since the first to third pixel regions P1 to P3 output different colors, ie, different wavelengths of light, the first to third pixel regions P1 to P3 have different cavity thicknesses. The cavity thickness is the distance between the reflective electrode 180 and the second electrode 220.

[0127] In this regard, the first pixel region P1, the second pixel region P2, and the third pixel region P3 displaying red, green, and blue, respectively, may have a cavity thickness proportional to the wavelength of each color (or the half wavelength of each color). The cavity thickness of each pixel region P may match an integer multiple of the half wavelength of its color.

[0128] In this regard, the first pixel region P1 of red having the longest wavelength has a first cavity thickness t1, the second pixel region P2 of green having an intermediate wavelength has a second cavity thickness t2 less than the first cavity thickness t1, and the third pixel region P3 of blue having the shortest wavelength has a third cavity thickness t3 less than the second cavity thickness t2.

[0129] In the present embodiment, when different cavity thicknesses are set among the first to third pixel regions P1 to P3, the height (or thickness) of the dielectric layer 185 may be different between the first to third pixel regions P1 to P3. In other words, each of the reflective electrode 180, the first electrode 190, and the organic light emitting layer 210 may be formed with the same or substantially the same thickness between the pixel regions, and thus the height of the dielectric layer 185 may be different between the pixel regions.

[0130] For example, the dielectric layer 185 of the red first pixel region P1 may have the highest first height h1, the dielectric layer 185 of the green second pixel region P2 may have a second height h2 less than the first height h1, and the dielectric layer 185 of the blue third pixel region P3 may have a third height h3 less than the second height h2.

[0131] In this way, by making the height of the dielectric layer 185 different between the pixel regions P1 , P2 , and P3 of different colors, different cavity thicknesses required for the pixel regions P1 , P2 , and P3 may be achieved.

[0132] In this embodiment, a microcavity structure may be realized by different structures of the height of the dielectric layer 185. Therefore, the pixel regions P1, P2, and P3 of different colors may have the same or substantially the same thickness of the light emitting diode OD, and thus the pixel regions P1, P2, and P3 may have the same or substantially the same characteristics of the light emitting diode OD.

[0133] In addition, the first to third pixel regions P1 to P3 may use the same white organic light emitting layer 210 , and each pixel region P may convert white light into light of its color through its microcavity structure and output light of the corresponding color.

[0134] Furthermore, in order to increase color purity, each pixel region P may include a corresponding color filter pattern 310r, 310g, or 310b on the light emitting diode OD.

[0135] <Third Embodiment>

[0136] Figure 5 is a cross-sectional view schematically illustrating an OLED according to a third embodiment of the present invention. Figure 6 Is magnification Figure 5 Cross-sectional view of a storage capacitor. Figure 7 is a plan view schematically illustrating a reflective electrode and a first electrode for forming a storage capacitor according to a third embodiment of the present invention.

[0137] exist Figure 5 , for the purpose of explanation, components of the OLED related to the present embodiment are shown, and the array stack structure located under the reflective electrode 180 is omitted.

[0138] Explanations of portions similar to those of the above first and second embodiments may be omitted.

[0139] Reference Figures 5 to 7 In the OLED 10 of the present embodiment, the storage capacitor Cst may have a non-uniform or uneven structure.

[0140] The OLED 10 of the present embodiment may have the same or similar components as those of the OLED of the first embodiment, except that the storage capacitor Cst has a concavo-convex structure.

[0141] like Figure 5As shown, the storage capacitor Cst has a first plate and a second plate and a dielectric layer 185 located between the first plate and the second plate. That is, the first plate is implemented by the first electrode 190, and the second plate is implemented by the reflective electrode 180. The storage capacitor Cst has a concave-convex shape or structure, and its cross section shows a square wave shape. For example, the first electrode 190 is uneven in the light emitting area EA, and includes a groove portion or a recessed portion. The dielectric layer 185 also has a square wave cross section in the light emitting area EA. The reflective electrode 180 has a groove portion 183 and a protrusion 182 in the light emitting area EA.

[0142] Since the storage capacitor Cst has the concavo-convex structure, the surface areas of the reflective electrode 180 and the first electrode 190 which are storage electrodes of the storage capacitor Cst are increased.

[0143] In this regard, in the first embodiment above, the storage electrode in the pixel region P has the same or substantially the same thickness as a whole and is formed approximately flat over the substrate. Compared with the structure of the first embodiment, in the concave-convex structure of the reflective electrode 180 and the first electrode 190 of the present embodiment, the surface area increases the area of ​​the side portion that is not flush with the surface of the substrate. By increasing the surface area, the capacitance of the storage capacitor Cst can be increased. Therefore, the required capacitance of the storage capacitor Cst can be more effectively ensured.

[0144] Regarding the concavo-convex structure of the present embodiment, the reflective electrode 180 as the lower storage electrode may have a concavo-convex surface, ie, a top surface, and for this purpose, the reflective electrode 180 may have a plurality of furrows 183 having uneven top surfaces spaced apart from each other in one direction.

[0145] In this regard, in the reflective electrode 180, a plurality of protrusions 182 protruding upward and a plurality of recesses 181 recessed downward may be alternately arranged in one direction, and thus a plurality of grooves 183 are recessed spaces on the recesses 181. Therefore, in the reflective electrode 180, the protrusions 182 and the grooves 183 may be alternately arranged in one direction.

[0146] The trench portion 183 may be formed to have a width r and a height d. In this regard, each of the width r and the height d of the trench portion 183 may be in the range of nanometers. For example, the width r of the trench portion 183 may be about 250 nm to about 350 nm, but is not limited thereto, and the height d of the trench portion 183 may be about 30 nm to about 70 nm, but is not limited thereto.

[0147] The groove portion 183 may have a circular shape in a plan view, such as Figure 7 Alternatively, the groove portion 183 may have a polygonal shape in a plan view.

[0148] Since the reflective electrode 180 is formed to have a concavo-convex shape, the dielectric layer 185 and the first electrode 190 stacked over the reflective electrode 180 may have a concavo-convex shape along the top surface of the reflective electrode 180 or may be formed according to the concavo-convex shape of the top surface of the reflective electrode 180, or may be formed according to the uneven top surface of the reflective electrode 180.

[0149] As such, since the reflective electrode 180 and the first electrode 190 constituting the storage capacitor Cst are formed to have a concavo-convex shape in a cross-sectional view, the storage capacitor Cst may be generated at a side surface portion of the groove portion 183. In this regard, the storage capacitor Cst may be generated between the side surface 184 of the protrusion 182 of the reflective electrode 180 and the corresponding side surface of the first electrode 190.

[0150] As described above, by means of the concavo-convex structure, the surface area of ​​the storage electrode can be increased by the side surface portion of the groove portion 183, and the capacitance of the storage capacitor Cst can be increased.

[0151] Since the storage capacitor Cst has a concavo-convex structure, the organic light emitting layer 210 and the second electrode 220 on the first electrode 190 may have a concavo-convex structure, that is, the organic light emitting layer 210 and the second electrode 220 may be formed according to the concavo-convex shape of the first electrode 190 .

[0152] In this way, through the concavo-convex structure of the storage capacitor Cst, the light emitting diode OD located on the storage capacitor Cst can naturally include a lens array structure in which the protrusions and the recesses are repeatedly arranged. In this regard, as described above, the groove portion 183 can be formed in a nanometer size, and thus the light emitting diode OD can have a lens array structure of a nanolens size, that is, a nanolens (nanolens) array structure.

[0153] Since the light emitting diode OD has a nano lens array structure, the efficiency of outputting the light waveguided in the lateral direction in the light emitting diode OD to the outside can be improved. In other words, the path of the light waveguided in the lateral direction is changed by the nano lens array structure in a similar principle to the micro lens array structure, thereby reducing the incident angle, and thus being able to increase the output amount of the waveguided light.

[0154] In addition, in the nano lens array structure, visible light with a relatively short wavelength can be diffracted. Therefore, the path of the light waveguided in the lateral direction is changed to the outside of the light emitting diode OD by diffraction, and the light output efficiency can be further increased. In this regard, since the micro lens array structure has a micron lens size, diffraction of visible light hardly occurs. However, by the nano lens array structure of this embodiment, the light output efficiency can be further increased.

[0155] <Fourth Embodiment>

[0156] Figure 8 is a cross-sectional view schematically illustrating an OLED according to a fourth embodiment of the present invention.

[0157] exist Figure 8 , for the purpose of explanation, components of the OLED related to the present embodiment are shown, and the array stack structure located under the reflective electrode 180 is omitted.

[0158] Explanations of portions similar to those of the above first to third embodiments may be omitted.

[0159] Reference Figure 8 In the OLED 10 of the present embodiment, the storage capacitor Cst may have a concavo-convex structure as in the third embodiment, and the light emitting diode OD may have a microcavity structure as in the second embodiment.

[0160] In order to form a microcavity structure, the second electrode 220 located on the organic light emitting layer 210 may include a semi-transparent (or semi-reflective) electrode layer having a semi-transparent (or semi-reflective) property.

[0161] Therefore, in each pixel region, light reflected and constructively interfered between the reflective electrode 180 and the second electrode 220 located below and above the organic light emitting layer 210 may pass through the second electrode 220 having a semi-transparent property and be output upward.

[0162] Since the first to third pixel regions P1 to P3 output lights of different colors, ie, different wavelengths, the first to third pixel regions P1 to P3 have different cavity thicknesses.

[0163] In this regard, the first pixel region P1, the second pixel region P2, and the third pixel region P3 that display red, green, and blue, respectively, may have a cavity thickness proportional to the wavelength of each color (or the half wavelength of each color). For example, the first pixel region P1 of red having the longest wavelength has a first cavity thickness t1, the second pixel region P2 of green having an intermediate wavelength has a second cavity thickness t2 that is less than the first cavity thickness t1, and the third pixel region P3 of blue having the shortest wavelength has a third cavity thickness t3 that is less than the second cavity thickness t2.

[0164] In the present embodiment, when different cavity thicknesses are set among the first to third pixel regions P1 to P3, the height (or thickness) of the dielectric layer 185 may be different between the first to third pixel regions P1 to P3. In other words, each of the reflective electrode 180, the first electrode 190, and the organic light emitting layer 210 may be formed with the same thickness between the pixel regions, and thus the height of the dielectric layer 185 may be different between the pixel regions.

[0165] For example, the dielectric layer 185 of the red first pixel region P1 may have the highest first height h1, the dielectric layer 185 of the green second pixel region P2 may have a second height h2 less than the first height h1, and the dielectric layer 185 of the blue third pixel region P3 may have a third height h3 less than the second height h2.

[0166] In this way, by making the height of the dielectric layer 185 different between the pixel regions P1 , P2 , and P3 of different colors, different cavity thicknesses required for the pixel regions P1 , P2 , and P3 may be achieved.

[0167] In this embodiment, a microcavity structure may be realized by different structures of the height of the dielectric layer 185. Therefore, the pixel regions P1, P2, and P3 of different colors may have the same or substantially the same thickness of the light emitting diode OD, and thus the pixel regions P1, P2, and P3 may have the same or substantially the same characteristics of the light emitting diode OD.

[0168] In addition, the first to third pixel regions P1 to P3 may use the same white organic light emitting layer 210 , and each pixel region P may convert white light into light of its color through its microcavity structure and output light of the corresponding color.

[0169] Furthermore, in order to increase color purity, each pixel region P may include a corresponding color filter pattern 310r, 310g, or 310b on the light emitting diode OD.

[0170] In the above embodiment, the storage capacitor Cst may be formed over the array stack structure of the driving light emitting diode in which the driving element and the lines and patterns for transmitting signals are formed, and the reflective electrode and the first electrode of the light emitting diode may be used as the storage electrode.

[0171] Therefore, the storage capacitor is not limited by the area or design of the array stack structure located below the storage capacitor, and the storage capacitor can be formed to have as large an area as possible, thereby fully ensuring the required storage capacitance. Similarly, the array stack structure is not limited by the area or design of the storage capacitor located above the array stack structure, thereby improving the layout freedom of the array stack structure.

[0172] Furthermore, since the reflective electrode and the first electrode are used as the storage electrode, an additional storage electrode is not required, so that the production process and cost can be reduced, and production efficiency can be ensured.

[0173] In addition, when the storage capacitor is formed to have a concavo-convex pattern, the storage capacitance can be maximized. In this case, since the light emitting diode has a nano lens array structure, light output efficiency can be increased.

[0174] It is obvious to those skilled in the art that various modifications and changes can be made in the display device of the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and changes to the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. An organic light emitting display device, comprising: a driving transistor in each of a plurality of pixel regions defined on the substrate; a reflective electrode on the driving transistor, the reflective electrode being electrically connected to a gate electrode of the driving transistor; a dielectric layer on the reflective electrode; a first electrode on the dielectric layer, the first electrode being electrically connected to the source electrode of the driving transistor and facing the reflective electrode; an organic light-emitting layer on the first electrode; and a second electrode on the organic light emitting layer, The plurality of pixel regions include a first pixel region, a second pixel region and a third pixel region which display different first colors, second colors and third colors respectively. wherein the first color has a wavelength longer than the wavelength of the second color, and the second color has a wavelength longer than the wavelength of the third color, and The dielectric layer of the first pixel region has a thickness greater than that of the dielectric layer of the second pixel region, and the dielectric layer of the second pixel region has a thickness greater than that of the dielectric layer of the third pixel region. 2 . The organic light emitting display device according to claim 1 , wherein each of the reflective electrode, the dielectric layer, and the first electrode has a concavo-convex shape.

3. The organic light emitting display device according to claim 2, wherein the reflective electrode comprises a plurality of grooves and has a top surface with a concavo-convex shape, and The dielectric layer and the first electrode are formed according to the concavo-convex shape of the top surface of the reflective electrode. 4 . The organic light emitting display device according to claim 2 , wherein the organic light emitting layer and the second electrode are formed according to the concavo-convex shape of the first electrode. 5 . The organic light emitting display device of claim 3 , wherein the groove portion of the reflective electrode has a width of about 250 nm to about 350 nm and a height of about 30 nm to about 70 nm.

6. The organic light-emitting display device according to claim 1, wherein in each of the first pixel region, the second pixel region, and the third pixel region, a thickness as a distance from the reflective electrode to the second electrode matches an integer multiple of a half wavelength of a color of each of the first pixel region, the second pixel region, and the third pixel region.

7. The organic light emitting display device according to claim 1, wherein the organic light emitting layer of each of the plurality of pixel regions emits white light, and A color filter pattern corresponding to a color of each of the plurality of pixel regions is provided on the second electrode.

8. The organic light emitting display device according to claim 1, wherein the substrate is a crystalline silicon substrate, A plurality of metal layers are formed between the substrate and the reflective electrode, and The plurality of metal layers include: a first metal layer comprising the gate electrode of the driving transistor; a second metal layer on the first metal layer, the second metal layer comprising a drain electrode and a source electrode of the driving transistor; and At least one metal layer on the second metal layer, the at least one metal layer comprising: at least one gate connection pattern connecting the gate electrode to the reflective electrode, at least one source connection pattern connecting the source electrode to the first electrode, and at least one drain connection pattern connecting the drain electrode to a driving voltage line. 9 . The organic light emitting display device according to claim 1 , wherein the first electrode, the organic light emitting layer, and the second electrode constitute a light emitting diode, and the reflective electrode, the dielectric layer, and the first electrode constitute a storage capacitor. 10 . The organic light emitting display device according to claim 9 , wherein the light emitting diodes have the same thickness in the plurality of pixel regions. The organic light emitting display device according to claim 3 , wherein the groove is formed in a nanometer size. 12 . The organic light emitting display device according to claim 1 , further comprising a bank formed on the first electrode, wherein the bank comprises an opening exposing the first electrode and covers an edge of the first electrode, wherein an edge of the reflective electrode extends below the bank. 13 . The organic light emitting display device according to claim 1 , wherein a cross section of the first electrode has a square wave shape. The organic light emitting display device according to claim 9 , wherein a cross section of the dielectric layer has a square wave shape. 15 . The organic light emitting display device of claim 2 , wherein the reflective electrode comprises a plurality of grooves to have an uneven top surface, wherein the dielectric layer and the first electrode are formed according to the uneven top surface of the reflective electrode.

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