Power management circuit and display device having the same

Abstract

Disclosed are a power management circuit for a display device and a display device, wherein the power management circuit includes: a voltage information storage device, including a first bank and a second bank storing first voltage information and second voltage information corresponding to first voltage levels and second voltage levels different from each other; a bank selection pin, receiving a bank selection signal; a voltage information selection circuit, in response to the bank selection signal received through the bank selection pin, selectively outputting the first voltage information stored in the first bank or the second voltage information stored in the second bank; and a DC-DC converter, which generates a panel driving voltage having a first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and generates a panel driving voltage having a second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit.

Description

[0001] The technical field relates to display devices including power management circuits. Background Art

[0002] Display devices such as liquid crystal display (LCD) devices often undergo aging treatment after they are assembled. Aging treatment drives the display device to detect defects in the display panel caused by wear over time or use. However, when the panel drive voltage (e.g., analog drive voltage, high gate voltage, low gate voltage, etc.) used in the normal driving operation of the display device is used in the aging treatment, the aging treatment may take too much time. In order to reduce the time of the aging treatment, a high voltage stress (HVS) aging treatment has been developed, which uses a panel drive voltage with a level (or absolute value) higher than the level (or absolute value) of the panel drive voltage under normal driving operation.

[0003] In order to perform the HVS aging process, before the HVS aging process, a data writing operation of writing voltage information of the panel driving voltage having a higher level to the power management circuit should be performed, and after the HVS aging process, a data writing operation of writing voltage information of the panel driving voltage under normal driving operation to the power management circuit should be performed. Therefore, due to the added supplementary processing time, the entire aging processing time may increase. Summary of the invention

[0004] Some example embodiments provide a power management circuit of a display device capable of reducing an entire aging process time of the display device.

[0005] Some example embodiments provide a display device capable of reducing the overall aging process time.

[0006] According to an exemplary embodiment, a power management circuit of a display device is provided. The power management circuit includes: a voltage information storage device including a first bank configured to store first voltage information representing a first voltage level and a second bank configured to store second voltage information corresponding to a second voltage level different from the first voltage level; a bank selection pin configured to receive a bank selection signal; a voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin; and a DC-DC converter configured to generate a panel driving voltage having a first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate a panel driving voltage having a second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit.

[0007] In an exemplary embodiment, during the aging process of the display device, the voltage information selection circuit may receive a bank selection signal having a first level through a bank selection pin, and may output first voltage information in response to the bank selection signal having the first level. After the aging process, the voltage information selection circuit may receive a bank selection signal having a second level different from the first level through the bank selection pin, and may output second voltage information in response to the bank selection signal having the second level.

[0008] In an exemplary embodiment, during the aging process, the bank select pin may receive a bank select signal from a bridge board coupled to a control board on which the power management circuit is mounted.

[0009] In an exemplary embodiment, the first voltage information may be high voltage information and the first voltage level may be a high voltage level, and the second voltage information may be normal voltage information and the second voltage level may be a normal voltage level.

[0010] In an exemplary embodiment, the voltage information selection circuit may receive a bank selection signal having a first level through a bank selection pin in a first mode of the display device, and may output first voltage information in response to receiving the bank selection signal having the first level. The voltage information selection circuit may receive a bank selection signal having a second level different from the first level through a bank selection pin in a second mode of the display device, and may output second voltage information in response to receiving the bank selection signal having the second level.

[0011] In an exemplary embodiment, the bank selection pin may receive a bank selection signal from a timing controller included in the display device.

[0012] In an exemplary embodiment, the first mode may be a 2D mode in which the display device displays a 2D image, and the second mode may be a 3D mode in which the display device displays a 3D image.

[0013] In an exemplary embodiment, the first mode may be a standard dynamic range mode in which the display device displays an image with a standard dynamic range, and the second mode may be a high dynamic range mode in which the display device displays an image with a high dynamic range.

[0014] In an exemplary embodiment, the voltage information storage means may be implemented with a nonvolatile memory device.

[0015] In an exemplary embodiment, the panel driving voltage generated by the DC-DC converter may include an analog driving voltage and a semi-analog driving voltage provided to a data driver included in the display device, and may also include a high gate voltage and a low gate voltage provided to a gate driver included in the display device.

[0016] In an exemplary embodiment, the first voltage information may include first transition time information corresponding to the first transition time, and the second voltage information may include second transition time information corresponding to the second transition time. The DC-DC converter may be configured to gradually change the panel driving voltage from the second voltage level to the first voltage level within the first transition time in response to the first voltage information, and may gradually change the panel driving voltage from the first voltage level to the second voltage level within the second transition time in response to the second voltage information.

[0017] According to an exemplary embodiment, a power management circuit of a display device is provided. The power management circuit includes: a voltage information storage device including N banks configured to store N voltage information together, where N is an integer greater than 1; at least one bank selection pin configured to receive a bank selection signal; a voltage information selection circuit configured to selectively output one voltage information of the N voltage information stored in the N banks in response to the bank selection signal received through the at least one bank selection pin; and a DC-DC converter configured to generate a panel driving voltage having a voltage level corresponding to one voltage information based on one voltage information output from the voltage information selection circuit.

[0018] In an exemplary embodiment, the at least one bank select pin includes M bank select pins, where M may be an integer satisfying the equation N≤2^M<2*N.

[0019] In an exemplary embodiment, during the aging process, at least one bank select pin may receive a bank select signal from a bridge board coupled to a control board on which the power management circuit is mounted.

[0020] In an exemplary embodiment, at least one bank selection pin may receive a bank selection signal from a timing controller included in the display device.

[0021] In an exemplary embodiment, the panel driving voltage generated by the DC-DC converter may include an analog driving voltage and a semi-analog driving voltage provided to a data driver included in the display device, and a high gate voltage and a low gate voltage provided to a gate driver included in the display device.

[0022] According to an exemplary embodiment, a display device is provided, the display device including: a display panel including a plurality of pixels; a power management circuit configured to generate a panel driving voltage; and a panel driver configured to drive the display panel based on the panel driving voltage. The power management circuit includes: a voltage information storage device including a first bank storing first voltage information corresponding to a first voltage level and a second bank storing second voltage information corresponding to a second voltage level different from the first voltage level; a bank selection pin configured to receive a bank selection signal; a voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin; and a DC-DC converter configured to generate a panel driving voltage having a first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate a panel driving voltage having a second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit.

[0023] In an exemplary embodiment, during the aging process of the display device, the voltage information selection circuit may receive a bank selection signal having a first level through a bank selection pin, and may output first voltage information in response to the bank selection signal having the first level. After the aging process, the voltage information selection circuit may receive a bank selection signal having a second level different from the first level through the bank selection pin, and may output second voltage information in response to the bank selection signal having the second level.

[0024] In an exemplary embodiment, during the aging process, the bank select pin may receive a bank select signal from a bridge board coupled to a control board on which the power management circuit is mounted.

[0025] In an exemplary embodiment, the first voltage information may be high voltage information and the first voltage level may be a high voltage level, and the second voltage information may be normal voltage information and the second voltage level may be a normal voltage level.

[0026] As described above, the power management circuit and the display device according to the exemplary embodiment can store a plurality of voltage information, can select one of the plurality of voltage information in response to a bank selection signal received through a bank selection pin, and can generate a panel driving voltage having a voltage level represented by the selected voltage information. Therefore, the voltage level of the panel driving voltage can be effectively changed.

[0027] In addition, the power management circuit and the display device according to the exemplary embodiment can generate a panel driving voltage having a first voltage level in response to a bank selection signal having a first level when performing an aging process, and can generate a panel driving voltage having a second voltage level in response to a bank selection signal having a second level after performing an aging process. Therefore, although a plurality of data writing operations for writing different voltage information of the panel driving voltage to the power management circuit are not performed before and after the aging process, the voltage level of the panel driving voltage can be effectively changed, and the entire aging process time of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment.

[0030] Figure 2 is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0031] Figure 3 is a flowchart illustrating a testing process of a display device according to an exemplary embodiment.

[0032] Figure 4 is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0033] Figure 5 is a diagram illustrating an example of first voltage information and second voltage information stored in a first bank and a second bank of a power management circuit according to an exemplary embodiment.

[0034] Figure 6 is a timing diagram for describing an operation of a power management circuit when a test process of a display device is performed according to an exemplary embodiment.

[0035] Figure 7 is a graph showing an example of changes over time during aging treatment.

[0036] Figure 8 is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0037] Fig. 9 is a timing diagram for describing an operation of a power management circuit when a test process of a display device is performed according to an exemplary embodiment.

[0038] Fig.10 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment.

[0039] Fig.11 is a block diagram illustrating a power management circuit and a timing controller included in a display device according to an exemplary embodiment.

[0040] Fig.12 is a diagram illustrating an example of first voltage information and second voltage information stored in a first bank and a second bank of a power management circuit according to an exemplary embodiment.

[0041] Fig.13 is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0042] Fig.14 is a block diagram illustrating an electronic device including a display device according to an exemplary embodiment. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments of the inventive concept will be explained in detail with reference to the accompanying drawings.

[0044] Example embodiments are described with reference to the drawings, wherein like reference numerals may refer to like elements throughout.

[0045] Although the terms "first", "second", etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Without departing from the teaching of one or more embodiments, the first element can be referred to as the second element. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can be used to distinguish elements of different categories or sets. For simplicity, the terms "first", "second", etc. can respectively represent "first type (or first set)", "second type (or second set)", etc.

[0046] The singular forms “a,” “an,” and “the” may include the plural forms as well, unless the context clearly indicates otherwise.

[0047] Furthermore, the statement that a first element, such as a layer, region, substrate, or board, is placed “on” or “over” a second element not only indicates the case where the first element is directly placed “on” the second element but also indicates the case where one or more intervening elements are placed between the first element and the second element.

[0048] When used in this specification, the terms "include" and / or "including" specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence and / or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0049] The sizes of elements in the drawings may be exaggerated for convenience of explanation.

[0050] Figure 1 is a block diagram illustrating a display apparatus according to an exemplary embodiment.

[0051] Reference Figure 1 , the display device 100 according to an exemplary embodiment may include: a display panel 110 including a plurality of pixels PX; a power management circuit 120 generating a panel driving voltage; and a panel driver 130 driving the display panel 110 based on the panel driving voltage. The panel driver 130 may include a data driver 140 providing a data signal DS to the plurality of pixels PX, a gate driver 150 providing a gate signal GS to the plurality of pixels PX, and a timing controller (TCON) 160 controlling the operation of the display device 100.

[0052] The display panel 110 may include a plurality of data lines, a plurality of gate lines, and a plurality of pixels PX coupled to the plurality of data lines and the plurality of gate lines. The display panel 110 may be a liquid crystal display (LCD) panel in which each pixel PX includes a switching transistor and a liquid crystal capacitor coupled to the switching transistor, or an OLED display panel in which each pixel PX includes at least one capacitor, at least one transistor, and an organic light emitting diode (OLED). The display panel 110 is not limited to an LCD panel and an OLED display panel, and may be any suitable display panel.

[0053] The power management circuit 120 may generate a panel driving voltage based on an input voltage VIN provided from an external circuit or an external device. The panel driving voltage generated by the power management circuit 120 may include an analog driving voltage AVDD and a semi-analog driving voltage HAVDD provided to the data driver 140 and a high gate voltage VGH and a low gate voltage VGL provided to the gate driver 150. The power management circuit 120 may include a gamma reference voltage generator that generates a gamma reference voltage based on the analog driving voltage AVDD and / or the input voltage VIN. The gamma reference voltage provided to the data driver 140 is considered to be one of the panel driving voltages. For example, the gamma reference voltage may include a positive high (or upper-high) gamma reference voltage having the highest voltage level, a negative low (lower-low) gamma reference voltage having the lowest voltage level, and a positive low (upper-low) gamma reference voltage and a negative high (lower-high) gamma reference voltage between the positive high gamma reference voltage and the negative low gamma reference voltage. In addition, the power management circuit 120 may include a common voltage generator that generates a common voltage based on the analog driving voltage AVDD and / or the input voltage VIN. The panel driving voltage may include a common voltage provided to the display panel 110. The power management circuit 120 may be implemented with a power management integrated circuit (PMIC) mounted on a control board (e.g., a control printed circuit board (PCB) or a control printed board assembly (PBA)) where the timing controller 160 is located.

[0054] The data driver 140 may receive the analog driving voltage AVDD and the half-analog driving voltage HAVDD from the power management circuit 120, and may receive the output image data ODAT and the data control signal DCTRL outputted from the timing controller 160. The data driver 140 may also generate the data signal DS based on the analog driving voltage AVDD, the half-analog driving voltage HAVDD, the output image data ODAT, and the data control signal DCTRL. Then, the data driver 140 may provide the data signal DS to the plurality of pixels PX. For example, the data driver 140 may generate gray voltages (e.g., 256 gray voltages) corresponding to all gray levels (e.g., from gray level 0 to gray level 255) respectively based on the analog driving voltage AVDD, the half-analog driving voltage HAVDD, and / or the gamma reference voltage, and may output the gray voltages corresponding to the gray levels represented by the output image data ODAT as the data signal DS to the plurality of pixels PX. The data driver 140 may perform a polarity inversion operation using the positive gray voltage and the negative gray voltage alternately. The output buffer of the data driver 140 can output a positive grayscale voltage based on the analog drive voltage AVDD and the semi-analog drive voltage HAVDD, and can output a negative grayscale voltage based on the semi-analog drive voltage HAVDD and the ground voltage. Therefore, compared with a data driver that does not use the semi-analog drive voltage HAVDD, the power consumption of the data driver 140 can be reduced. The data control signal DCTRL may include a horizontal start signal and a load signal. The data driver 140 may be implemented with one or more data driver integrated circuits (ICs). For example, one or more data driver ICs may be mounted on a flexible film connected to the display panel 110 in a chip on film (COF) manner, or may be mounted on the display panel 110 in a chip on glass (COG) manner or a chip on plastic (COP) manner.

[0055] The gate driver 150 may receive a high gate voltage VGH and a low gate voltage VGL from the power management circuit 120, and may receive a gate control signal GCTRL from the timing controller 160. The gate driver 150 may also generate a gate signal GS based on the high gate voltage VGH, the low gate voltage VGL, and the gate control signal GCTRL, and may sequentially provide the gate signal GS to a plurality of pixels PX row by row. For example, the gate control signal GCTRL may include a gate start signal and a gate clock signal. The gate driver 150 may be implemented as an amorphous silicon gate (ASG) driver integrated in the peripheral portion of the display panel 110, or the gate driver 150 may be implemented with one or more gate driver ICs. In addition, the gate driver 150 may be mounted on a flexible film connected to the display panel 110 in a COF manner, or may be mounted on the display panel 110 in a COG manner or a COP manner.

[0056] The timing controller 160 may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU) or a graphics card). For example, the input image data IDAT may be RGB image data including red image data, green image data, and blue image data. In addition, the control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a master clock signal, and other such similar signals. The timing controller 160 may generate output image data ODAT, a data control signal DCTRL, and a gate control signal GCTRL based on the input image data IDAT and the control signal CTRL. The timing controller 160 may control the operation of the data driver 140 by providing the output image data ODAT and the data control signal DCTRL to the data driver 140, and may control the operation of the gate driver 150 by providing the gate control signal GCTRL to the gate driver 150. The timing controller 160 may be implemented with an integrated circuit and may be mounted on a control board (e.g., a control PCB or a control PBA) together with the power management circuit 120.

[0057] In the display device 100 according to the exemplary embodiment, the power management circuit 120 may store a plurality of voltage information in a plurality of banks, select a voltage information from the plurality of voltage information in response to a bank selection signal BSS received through a bank selection pin, and generate a panel driving voltage having a voltage level represented by the selected voltage information. Therefore, the voltage level of the panel driving voltage may be effectively changed. During the aging process, the power management circuit 120 may generate a panel driving voltage having a first voltage level (e.g., a high voltage level) in response to a bank selection signal BSS having a first level. After the aging process, the power management circuit 120 may generate a panel driving voltage having a second voltage level (e.g., a normal voltage level) in response to the bank selection signal BSS. Therefore, although a plurality of data writing operations of writing different voltage information of the panel driving voltage to the power management circuit 120 are not performed before and after the aging process, the voltage level of the panel driving voltage may be effectively changed, and thus the entire aging process time of the display device 100 may be reduced. In an embodiment, the power management circuit 120 may generate a panel driving voltage having a first voltage level in response to a bank selection signal BSS having a first level in a first mode (e.g., a two-dimensional (2D) mode, a standard dynamic range (SDR) mode, etc.), and may generate a panel driving voltage having a second voltage level in response to a bank selection signal BSS having a second level in a second mode (e.g., a three-dimensional (3D) mode, a high dynamic range (HDR) mode, etc.). Therefore, the voltage level of the panel driving voltage may be effectively changed according to the operation mode of the display device 100.

[0058] Figure 2 is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0059] Reference Figure 2 , a power management circuit 120 a of a display device according to an exemplary embodiment may include a voltage information storage device 210 , a bank selection pin BSP, a voltage information selection circuit 220 , and a direct current-to-direct current (DC-DC) converter 230 .

[0060] The voltage information storage device 210 may include a first bank (BANK1) 212 storing first voltage information VI1 representing (e.g., expressing or corresponding to) a first voltage level and a second bank (BANK2) 214 storing second voltage information VI2 representing a second voltage level different from the first voltage level. Here, the first bank 212 and the second bank 214 may be physically separate different physical memory cells, or may be logically separate storage areas within the same physical memory cell. The first voltage information VI1 stored in the first bank 212 may be high voltage information representing a high voltage level as the first voltage level, and the second voltage information VI2 stored in the second bank 214 may be normal voltage information representing a normal voltage level as the second voltage level. Here, the high voltage level may have an absolute value higher than the normal voltage level. The voltage information storage device 210 may be implemented with a non-volatile memory device that retains data even when there is no power supply. For example, the voltage information storage device 210 may be implemented with an electrically erasable programmable read-only memory (EEPROM), a flash memory device, etc. In an embodiment, the voltage information storage device 210 may be implemented with a volatile memory device.

[0061] The bank selection pin BSP may receive a bank selection signal BSS. When an aging process is performed on a display device including the power management circuit 120a, the bank selection pin BSP may receive a bank selection signal BSS having a first level from a bridge board connected to a control board on which the power management circuit 120a is mounted. In addition, a line on the control board through which the bank selection signal BSS is transmitted may be connected to a pull-down terminal resistor, and the bank selection pin BSP may receive a bank selection signal BSS having a second level through the pull-down terminal resistor when the aging process is not performed.

[0062] The voltage information selection circuit 220 may selectively output the first voltage information VI1 stored in the first bank 212 or the second voltage information VI2 stored in the second bank 214 in response to the bank selection signal BSS received through the bank selection pin BSP. Figure 2As shown in , the voltage information selection circuit 220 may include a multiplexer 225, and the multiplexer 225 operates in response to a bank selection signal BSS received through a bank selection pin BSP. For example, the multiplexer 225 may output the first voltage information VI1 in response to receiving the bank selection signal BSS having a first level, and may output the second voltage information VI2 in response to receiving the bank selection signal BSS having a second level.

[0063] The DC-DC converter 230 may generate a panel driving voltage having a first voltage level based on the first voltage information VI1 or the second voltage information VI2 according to the voltage received from the voltage information selection circuit 220. The panel driving voltage generated by the DC-DC converter 230 may include an analog driving voltage AVDD and a semi-analog driving voltage HAVDD provided to the data driver, and may also include a high gate voltage VGH and a low gate voltage VGL provided to the gate driver. The panel driving voltage may further include a gamma reference voltage, a common voltage, and other similar voltages. Each voltage information (e.g., the first voltage information VI1 or the second voltage information VI2) provided to the DC-DC converter 230 from the voltage information selection circuit 220 may represent a voltage level of the analog driving voltage AVDD, a voltage level of the semi-analog driving voltage HAVDD, a voltage level of the high gate voltage VGH, and a voltage level of the low gate voltage VGL.

[0064] like Figure 2 As shown in , the DC-DC converter 230 may include an analog drive voltage generating circuit 240, which generates an analog drive voltage AVDD based on an input voltage VIN provided from an external circuit or an external device. The analog drive voltage generating circuit 240 may convert the input voltage VIN into an analog drive voltage AVDD having a voltage level represented by the voltage information (e.g., the first voltage information VI1 or the second voltage information VI2) selected by the voltage information selecting circuit 220. For example, the analog drive voltage generating circuit 240 may be implemented with a boost converter, which includes an inductor L1, a switching element SW, a diode D1, a capacitor C1, and a pulse width modulation (PWM) control block 245. The PWM control block 245 may change the pulse width or duty cycle of the switching signal SWS applied to the switching element SW according to the voltage level of the analog drive voltage AVDD represented by the selected voltage information.

[0065] The DC-DC converter 230 may also include a semi-analog drive voltage generating circuit 250 that generates a semi-analog drive voltage HAVDD based on an input voltage VIN and / or an analog drive voltage AVDD, a high gate voltage generating circuit 260 that generates a high gate voltage VGH based on the input voltage VIN and / or the analog drive voltage AVDD, and a low gate voltage generating circuit 270 that generates a low gate voltage VGL based on the input voltage VIN and / or the analog drive voltage AVDD. Each of the semi-analog drive voltage generating circuit 250, the high gate voltage generating circuit 260, and the low gate voltage generating circuit 270 may be implemented with any type of converter such as a boost converter, a buck converter, and a buck-boost converter. The semi-analog drive voltage generating circuit 250 may convert the input voltage VIN or the analog drive voltage AVDD into a semi-analog drive voltage HAVDD having a voltage level represented by the selected voltage information. The high gate voltage generating circuit 260 may convert the input voltage VIN or the analog drive voltage AVDD into a high gate voltage VGH having a voltage level represented by the selected voltage information. The low gate voltage generating circuit 270 may convert the input voltage VIN or the analog driving voltage AVDD into a low gate voltage VGL having a voltage level indicated by the selected voltage information.

[0066] As described above, when performing the aging process, the power management circuit 120a can generate a panel driving voltage having a first voltage level (e.g., a high voltage level) in response to the bank selection signal BSS having a first level received from the bridge board through the bank selection pin BSP. When the aging process is not performed, the power management circuit 120a can generate a panel driving voltage having a second voltage level (e.g., a normal voltage level) in response to the bank selection signal BSS having a second level received through the bank selection pin BSP. Therefore, although a plurality of data write operations of writing different voltage information of the panel driving voltage to the power management circuit 120a are not performed before and after the aging process, a panel driving voltage having a high voltage level can be generated during the aging process, and a panel driving voltage having a normal voltage level can be generated after the aging process. Therefore, the aging process can be effectively performed by using a panel driving voltage having a high voltage level, and the entire aging process time of the display device can be reduced.

[0067] Figure 3 is a flowchart illustrating a testing process of a display device according to an exemplary embodiment, Figure 4 is a block diagram illustrating a power management circuit that receives a bank select signal from a bridge board according to an exemplary embodiment, Figure 5 is a diagram showing first voltage information and second voltage information stored in first and second banks of a power management circuit according to an exemplary embodiment, Figure 6is a timing diagram for describing the operation of the power management circuit when performing a test process of the display device according to an exemplary embodiment, and Figure 7 is a graph showing a change over time during an aging process using a panel driving voltage having a normal voltage level and a change over time during an aging process using a panel driving voltage having a high voltage level.

[0068] Reference Figures 1 to 3 After assembling or manufacturing the display device 100 according to the exemplary embodiment (S310), a test process (S320 to S360) of the display device 100 may be performed. The assembly process of the display device 100 may include: a cleaning and polarization (CP) process of cullet glass of the lower substrate and the upper substrate of the display panel 110; an on-chip wire bonding (OLB) process of attaching the display panel 110 and the data driver 140; a PCB bonding process of attaching the data driver 140 and the control board on which the power management circuit 120 and the timing controller 160 are mounted, etc.

[0069] The test process of the display device 100 may include a manual test (MT) process (S320), an aging treatment (S340), and a final test (FT) process (S360). The MT process (S320) of the display device 100 may drive the display device 100 to display a test pattern image, and may detect line defects or point defects of the display device 100 with the naked eye or by using a camera (e.g., a charge coupled device (CCD) camera). For example, during the MT process (S320), the control board of the display device 100 may be connected to a setting board that provides an input voltage VIN and input image data IDAT corresponding to the test pattern image. The MT process (S320) may be an automatic manual test (AMT) process. The display device 100 determined to be defective by the MT process (S320) may be discarded or repaired.

[0070] Before the aging process (S340), the bank selection signal BSS having a first level may be provided to the power management circuit 120 (S330). Figure 4 As shown in FIG. 1 , the control board 410 on which the power management circuit (PMIC) 120 and the timing controller (TCON) 160 are mounted may be coupled to the bridge board 450 through a flexible printed circuit FPC. The bridge board 450 may include a switch 460 that selectively transmits a voltage of a first level (e.g., about 3.3V), and the power management circuit (PMIC) 120 may receive the voltage of the first level from the bridge board 450 through the switch 460 as the bank selection signal BSS.

[0071] The power management circuit (PMIC) 120 may include a first bank (BANK1) 212 storing the first voltage information VI1 and a second bank (BANK2) 214 storing the second voltage information VI2. The first voltage information VI1 and the second voltage information VI2 may be written to the first bank 212 and the second bank 214 substantially at the same time by an external circuit or an external device. The voltage information storage device 210 including the first bank 212 and the second bank 214 may be implemented with a non-volatile memory device. For example, the first voltage information VI1 and the second voltage information VI2 may be written to the first bank 212 and the second bank 214 substantially at the same time before the assembly process (S310) of the display device 100, or may be written substantially at the same time after the assembly process (S310) of the display device 100 and before the MT process (S320). In an embodiment, when the display device 100 is powered on, the first voltage information VI1 and the second voltage information VI2 may be written to the first bank 212 and the second bank 214 substantially at the same time from the timing controller 160 through integrated circuit (I2C) communication. In this case, the voltage information storage apparatus 210 including the first bank 212 and the second bank 214 may be implemented with a volatile memory device.

[0072] Before performing the aging process (S340), the power management circuit 120 may generate a panel driving voltage (e.g., an analog driving voltage AVDD, a semi-analog driving voltage HAVDD, a high gate voltage VGH, and a low gate voltage VGL). In response to the bank selection signal BSS having a first level, the panel driving voltage may have a first voltage level (e.g., a high voltage level) corresponding to the first voltage information VI1 stored in the first bank 212. For example, Figure 5 As shown in , the first library 212 may store high voltage information HVI as the first voltage information VI1. The high voltage information HVI may represent about 18V as the voltage level of the analog driving voltage AVDD, about 9V as the voltage level of the half analog driving voltage HAVDD, about 40V as the voltage level of the high gate voltage VGH, and about -12V as the voltage level of the low gate voltage VGL.

[0073] As described above, since the bank selection signal BSS having the first level is provided to the power management circuit 120 before the aging process (S340), the aging process (S340) can be performed by using the panel driving voltage having a high voltage level. Figure 6As shown in, during the period APP of performing the aging process (S340), the control board 410 may be connected to the setting board that provides the input voltage VIN and the input image data IDAT through the bridge board 450, the power management circuit 120 may receive the bank selection signal BSS having a first level from the bridge board 450, and the power management circuit 120 may generate an analog driving voltage AVDD of about 18 V, a half analog driving voltage HAVDD of about 9 V, a high gate voltage VGH of about 40 V, and a low gate voltage VGL of about -12 V. Through the aging process (S340), the transistors (of the pixel PX or the gate driver 150 implemented with the ASG driver) included in the display panel 110 may be changed due to aging (e.g., through use and accelerated wear).

[0074] As described above, since the aging process (S340) is not performed with a panel driving voltage having a normal voltage level but is performed by using a panel driving voltage having a high voltage level, the time required for the aging process (S340) can be reduced. Figure 7 In the comparative example 510 of the aging treatment in FIG. 5 , when the aging treatment (S340) is performed by using a panel driving voltage having a normal voltage level, the aging treatment (S340) should be performed for about 4T to allow a change in the voltage (VGS)-current (IDS) characteristics of the transistor included in the display panel 110 to occur over time. However, as Figure 7 As shown in the embodiment of the present invention indicated by 530 in FIG. 1 , when the aging process (S340) is performed by using a panel driving voltage having a high voltage level, the aging process (S340) may be performed for a time of about 1T to allow a change in the voltage (VGS)-current (IDS) characteristics of the transistors included in the display panel 110 to occur over time. Therefore, the time required for the aging process (S340) performed by using a panel driving voltage having a high voltage level may be reduced to a quarter of the time required for the aging process performed by using a panel driving voltage having a normal voltage level.

[0075] After the aging process (S340), the bank selection signal BSS having a second level (eg, a low level) may be provided to the power management circuit 120 (S350). Figure 4 As shown in FIG, a line 420 on the control board 410 through which the bank selection signal BSS is transmitted to the bank selection pin BSP of the power management circuit 120 may be coupled to a pull-down terminal resistor 430. Therefore, when the bank selection signal BSS having a first level (e.g., a high level) is not provided to the line 420, the bank selection signal BSS having a second level (e.g., a low level) may be provided to the bank selection pin BSP of the power management circuit 120 through the pull-down terminal resistor 430.

[0076] In addition, after the aging process (S340), the power management circuit 120 may generate a panel driving voltage having a second voltage level (e.g., a normal voltage level) corresponding to the second voltage information VI2 stored in the second bank 214 in response to the bank selection signal BSS having a second level. Figure 5 As shown in , the second library 214 may store normal voltage information NVI as the second voltage information VI2. The normal voltage information NVI may represent about 16V as the voltage level of the analog driving voltage AVDD, about 8V as the voltage level of the half analog driving voltage HAVDD, about 30V as the voltage level of the high gate voltage VGH, and about -8V as the voltage level of the low gate voltage VGL. Therefore, as Figure 6 As shown in FIG. 1 , after the period APP of the aging process (S340), the power management circuit 120 can generate an analog driving voltage AVDD of about 16 V, a half analog driving voltage HAVDD of about 8 V, a high gate voltage VGH of about 30 V, and a low gate voltage VGL of about -8 V. Therefore, in both the FT process (S360) and the normal driving operation after the FT process (S360), the power management circuit 120 can generate a panel driving voltage having a normal voltage level.

[0077] The FT process (S360) may be performed on the display device 100 on which the aging process (S340) is performed. The FT process (S360) may be performed in a manner similar to the MT process (S320) and may detect line defects or point defects of the display device 100 that change over time.

[0078] As described above, in the display device 100 including the power management circuit 120 according to the exemplary embodiment, a panel driving voltage having a high voltage level can be generated when the aging process (S340) is performed, and a panel driving voltage having a normal voltage level can be generated when the aging process (S340) is not performed. Therefore, although a plurality of data writing operations for writing different voltage information of the panel driving voltage to the power management circuit 120 are not performed before and after the aging process (S340), a panel driving voltage having a high voltage level can be generated during the aging process (S340), and a panel driving voltage having a normal voltage level can be generated after the aging process (S340). Therefore, the aging process (S340) can be effectively performed by using the panel driving voltage having a high voltage level, and the entire aging process time of the display device 100 can be reduced.

[0079] Figure 8 is a block diagram showing a power management circuit according to an exemplary embodiment, and Fig. 9is a timing diagram for describing an operation of a power management circuit when a test process of a display device is performed according to an exemplary embodiment.

[0080] Reference Figure 8 , the power management circuit 120b according to the exemplary embodiment may include a voltage information storage device 210b, a bank selection pin BSP, a voltage information selection circuit 220, and a DC-DC converter 230b. In addition to the first voltage information VI1 stored in the first bank 212b may include the first transition time information TTI1, the second voltage information VI2 stored in the second bank 214b may include the second transition time information TTI2, and the DC-DC converter 230b may gradually change the voltage level of the panel driving voltage, Figure 8 The power management circuit 120b may have Figure 2 The power management circuit 120a has a similar configuration and similar operation.

[0081] The first bank 212b of the voltage information storage device 210b may store first voltage information VI1 indicating a first voltage level, and the second bank 214b of the voltage information storage device 210b may store second voltage information VI2 indicating a second voltage level. The first voltage information VI1 may include first transition time information TTI1 including a first transition time, and the second voltage information VI2 may include second transition time information TTI2 including a second transition time. The voltage information selection circuit 220 may selectively output the first voltage information VI1 or the second voltage information VI2 in response to a bank selection signal BSS received through a bank selection pin BSP.

[0082] When the first voltage information VI1 is output from the voltage information selection circuit 220, the DC-DC converter 230b may generate a panel driving voltage having a first voltage level based on the first voltage information VI1. When the second voltage information VI2 is output from the voltage information selection circuit 220, the DC-DC converter 230b may generate a panel driving voltage having a second voltage level based on the second voltage information VI2. In order to generate an analog driving voltage AVDD, a semi-analog driving voltage HAVDD, a high gate voltage VGH, and a low gate voltage VGL as panel driving voltages, the DC-DC converter 230b may include an analog driving voltage generating circuit 240b, a semi-analog driving voltage generating circuit 250b, a high gate voltage generating circuit 260b, and a low gate voltage generating circuit 270b.

[0083] In response to the first voltage information VI1 including the first transition time information TTI1, the DC-DC converter 230b may gradually change the panel driving voltage from the second voltage level to the first voltage level within the first transition time indicated by the first transition time information TTI1. In response to the second voltage information VI2 including the second transition time information TTI2, the DC-DC converter 230b may gradually change the panel driving voltage from the first voltage level to the second voltage level within the second transition time indicated by the second transition time information TTI2.

[0084] In order to gradually change the voltage level of the analog drive voltage AVDD, such as Figure 8 As shown in , the analog drive voltage generating circuit 240b may include an inductor L1, a switching element SW, a diode D1, a capacitor C1, an error amplifier 241b, a comparator 243b, and a PWM control block 245b. The error amplifier 241b may amplify the difference between the analog drive voltage AVDD and the reference voltage VREF provided from the PWM control block 245b. The comparator 243b may generate a switching signal SWS by comparing the output voltage of the error amplifier 241b and the sawtooth voltage VSAW provided from the PWM control block 245b. The PWM control block 245b may receive the first transition time information TTI1 or the second transition time information TTI2, and may gradually change the reference voltage VREF within the first transition time or the second transition time. The analog drive voltage generating circuit 240b may gradually change the voltage level of the analog drive voltage AVDD based on the gradually changing reference voltage VREF. The semi-analog driving voltage generating circuit 250b, the high gate voltage generating circuit 260b and the low gate voltage generating circuit 270b may also have a configuration similar to the analog driving voltage generating circuit 240b, and may gradually change the semi-analog driving voltage HAVDD, the high gate voltage VGH and the low gate voltage VGL in response to the first transition time information TTI1 or the second transition time information TTI2.

[0085] For example, Fig. 9 As shown in, the DC-DC converter 230b can gradually (e.g., step by step) increase the voltage levels of the analog drive voltage AVDD, the half-analog drive voltage HAVDD, the high gate voltage VGH, and the low gate voltage VGL within a first transition time TT1 represented by the first transition time information TTI1, starting from the start time point of the aging treatment period APP. In addition, the DC-DC converter 230b can gradually reduce the voltage levels of the analog drive voltage AVDD, the half-analog drive voltage HAVDD, the high gate voltage VGH, and the low gate voltage VGL within a second transition time TT2 represented by the second transition time information TTI2, starting from the end time point of the aging treatment period APP. Although Fig. 9An example is shown in which the DC-DC converter 230 b changes the voltage level of the panel driving voltage stepwise, but the DC-DC converter 230 b may change the voltage level of the panel driving voltage linearly and smoothly.

[0086] Fig.10 is a flowchart illustrating a method of driving a display device according to an exemplary embodiment, Fig.11 is a block diagram illustrating a power management circuit and a timing controller included in a display device according to an exemplary embodiment, and Fig.12 is a diagram illustrating first voltage information and second voltage information stored in a first bank and a second bank of a power management circuit according to an exemplary embodiment.

[0087] Reference Figure 1 , Fig.10 and Fig.11 According to an exemplary embodiment, the first voltage information VI1 and the second voltage information VI2 may be stored in the first bank 712 and the second bank 714 of the power management circuit 120c of the display device 100, respectively (S610). In an embodiment, the voltage information storage device 710 including the first bank 712 and the second bank 714 may be implemented with a non-volatile memory device, and the first voltage information VI1 and the second voltage information VI2 may be written to the first bank 712 and the second bank 714 by an external device substantially at the same time when the display device 100 is manufactured. In an embodiment, the voltage information storage device 710 including the first bank 712 and the second bank 714 may be implemented with a volatile memory device, and the first voltage information VI1 and the second voltage information VI2 may be written to the first bank 712 and the second bank 714 substantially at the same time by the timing controller 160 when the display device 100 is powered on.

[0088] The timing controller 160 of the display device 100 may generate a bank selection signal BSS having a first level or a second level according to an operation mode of the display device 100 (S620, S630, and S650). In the case where the display device 100 operates in the first mode (S620), the timing controller 160 may generate a bank selection signal BSS having a first level (S630). In addition, in the case where the display device 100 operates in the second mode (S620), the timing controller 160 may generate a bank selection signal BSS having a second level (S650). The bank selection pin BSP of the power management circuit 120c may be connected to the timing controller 160, and may receive the bank selection signal BSS from the timing controller 160. The voltage information selection circuit 720 of the power management circuit 120c may output the first voltage information VI1 in response to the bank selection signal BSS having a first level received through the bank selection pin BSP in the first mode of the display device 100, and may output the second voltage information VI2 in response to the bank selection signal BSS having a second level received through the bank selection pin BSP in the second mode of the display device 100. The DC-DC converter 730 of the power management circuit 120c may generate the panel driving voltages AVDD, HAVDD, VGH, and VGL based on the first voltage information VI1 output from the voltage information selection circuit 720 in the first mode of the display device 100 (S640), and may generate the panel driving voltages AVDD, HAVDD, VGH, and VGL based on the second voltage information VI2 output from the voltage information selection circuit 720 in the second mode of the display device 100 (S660).

[0089] The first mode may be a two-dimensional mode, in which the display device 100 displays a two-dimensional image, and the second mode may be a three-dimensional mode, in which the display device 100 displays a three-dimensional image (e.g., by using a lenticular lens, a parallax barrier, and other similar methods). Fig.12 As shown in , the first library 712 can store two-dimensional voltage information 2DVI of panel driving voltages AVDD, HAVDD, VGH, and VGL applicable to the two-dimensional mode as the first voltage information VI1. The two-dimensional voltage information 2DVI can represent about 16V as the voltage level of the analog driving voltage AVDD, can represent about 8V as the voltage level of the semi-analog driving voltage HAVDD, can represent about 30V as the voltage level of the high gate voltage VGH, and can represent about -8V as the voltage level of the low gate voltage VGL. In addition, as shown in Fig.12As shown in , the second library 714 can store three-dimensional voltage information 3DVI of panel driving voltages AVDD, HAVDD, VGH and VGL applicable to the three-dimensional mode as the second voltage information VI2. The three-dimensional voltage information 3DVI can represent about 20V as the voltage level of the analog driving voltage AVDD, about 10V as the voltage level of the half-analog driving voltage HAVDD, about 30V as the voltage level of the high gate voltage VGH, and about -8V as the voltage level of the low gate voltage VGL. Therefore, the power management circuit 120c can generate an analog driving voltage AVDD of about 16V, a half-analog driving voltage HAVDD of about 8V, a high gate voltage VGH of about 30V, and a low gate voltage VGL of about -8V in the two-dimensional mode, and can generate an analog driving voltage AVDD of about 20V, a half-analog driving voltage HAVDD of about 10V, a high gate voltage VGH of about 30V, and a low gate voltage VGL of about -8V in the three-dimensional mode. In an embodiment, the first mode may be a standard dynamic range (SDR) mode, and the second mode may be a high dynamic range (HDR) mode, wherein in the SDR mode the display device 100 displays an image with a standard dynamic range, and in the HDR mode the display device 100 displays an image with a high dynamic range.

[0090] The panel driver 130 may drive the display panel 110 based on the panel driving voltages AVDD, HAVDD, VGH, and VGL provided from the power management circuit 120c (S670). For example, the panel driver 130 may drive the display panel 110 in the first mode according to the panel driving voltages AVDD, HAVDD, VGH, and VGL generated based on the first voltage information VI1, and may drive the display panel 110 in the second mode according to the panel driving voltages AVDD, HAVDD, VGH, and VGL generated based on the second voltage information VI2.

[0091] As described above, the display device 100 including the power management circuit 120c according to the exemplary embodiment may generate the panel driving voltages AVDD, HAVDD, VGH, and VGL based on the first voltage information VI1 in response to the bank selection signal BSS having the first level in a first mode (e.g., a 2D mode, an SDR mode, etc.), and may generate the panel driving voltages AVDD, HAVDD, VGH, and VGL based on the second voltage information VI2 in response to the bank selection signal BSS having the second level in a second mode (e.g., a 3D mode, an HDR mode, etc.). Therefore, the voltage levels of the panel driving voltages AVDD, HAVDD, VGH, and VGL may be effectively changed according to the operation mode of the display device 100.

[0092] Fig.13is a block diagram illustrating a power management circuit according to an exemplary embodiment.

[0093] Reference Fig.13 , the power management circuit 120d according to the exemplary embodiment may include a voltage information storage device 810, at least one bank selection pin BSP1 ... BSPM, a voltage information selection circuit 820, and a DC-DC converter 830. In addition to the voltage information storage device 810 including N banks (i.e., BANK1, BANK2 ... BANKN) 811, 812 ... 81N, and the power management circuit 120d may include M bank selection pins BSP1 ... BSPM, Fig.13 The power management circuit 120d may have Figure 2 The power management circuit 120a has a similar configuration and similar operation.

[0094] The voltage information storage device 810 may include N banks 811, 812...81N storing N voltage information VI1, VI2...VI_N, where N is an integer greater than 1. The power management circuit 120d may include M bank selection pins BSP1...BSPM (M may be an integer satisfying the equation "N≤2^M<2*N"). For example, when N is 3 or 4, M may be 2, and when N is 5 to 8, M may be 3. When performing aging processing of the display device, the M bank selection pins BSP1...BSPM may receive a bank selection signal BSS from a bridge board connected to a control board on which the power management circuit 120d is mounted. In an embodiment, the M bank selection pins BSP1...BSPM may receive a bank selection signal BSS from a timing controller included in the display device.

[0095] The voltage information selection circuit 820 may include a multiplexer 825 that selects one of the N voltage information VI1, VI2, ... VI_N stored in the N banks 811, 812, ... 81N, respectively, in response to a bank selection signal BSS received through the M bank selection pins BSP1 ... BSPM, and outputs the selected voltage information. The DC-DC converter 830 may generate a panel driving voltage having a voltage level represented by the selected voltage information output from the voltage information selection circuit 820. The panel driving voltage generated by the DC-DC converter 830 may include an analog driving voltage AVDD and a semi-analog driving voltage HAVDD provided to a data driver included in the display device, and may also include a high gate voltage VGH and a low gate voltage VGL provided to a gate driver included in the display device.

[0096] As described above, the power management circuit 120d according to the exemplary embodiment can store N voltage information VI1, VI2 ... VI_N, can select voltage information among the N voltage information VI1, VI2 ... VI_N in response to the bank selection signal BSS received through the M bank selection pins BSP1 ... BSPM, and can generate a panel driving voltage having a voltage level represented by the selected voltage information. Therefore, the voltage level of the panel driving voltage can be effectively changed.

[0097] Fig.14 is a block diagram illustrating an electronic device including a display device according to an exemplary embodiment.

[0098] Reference Fig.14 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0099] The processor 1110 may be hardware for performing various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, etc. The processor 1110 may be further connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0100] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include hardware of at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0101] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be connected to other components via a bus or other communication links.

[0102] The display device 1160 may store a plurality of voltage information, may select one of the plurality of voltage information in response to a bank selection signal received through a bank selection pin, and may generate a panel driving voltage having a voltage level represented by the selected voltage information. Therefore, the voltage level of the panel driving voltage may be effectively changed.

[0103] The inventive concept may be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the inventive concept may be applied to a television (TV), a digital TV, a 3D TV, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.

[0104] The above is an explanation of the exemplary embodiments and should not be interpreted as limiting them. Based on this specification, those of ordinary skill in the art will easily understand that many modifications can be made in the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all of these modifications are intended to be included within the scope of the inventive concept defined in the claims. The above is an explanation of various embodiments and should not be interpreted as being limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.

Claims

1. A power management circuit for a display device, the power management circuit comprising: A voltage information storage device, comprising a first library and a second library, wherein the first library is configured to store first voltage information corresponding to a first voltage level, and the second library is configured to store second voltage information corresponding to a second voltage level different from the first voltage level; a bank select pin configured to receive a bank select signal; a voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin; as well as a DC-DC converter configured to generate a panel driving voltage having the first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate the panel driving voltage having the second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit; wherein, during the aging process of the display device, the voltage information selection circuit receives the bank selection signal having a first level through the bank selection pin, and outputs the first voltage information in response to the bank selection signal having the first level, and Wherein, after the aging process, the voltage information selection circuit receives the bank selection signal having a second level different from the first level through the bank selection pin, and outputs the second voltage information in response to the bank selection signal having the second level.

2. The power management circuit according to claim 1, wherein: During the aging process, the bank select pin receives the bank select signal from a bridge board coupled to a control board on which the power management circuit is mounted.

3. The power management circuit according to claim 1, wherein: The first voltage information is high voltage information, and the first voltage level is a high voltage level, and The second voltage information is normal voltage information, and the second voltage level is a normal voltage level.

4. A power management circuit for a display device, the power management circuit comprising: A voltage information storage device, comprising a first library and a second library, wherein the first library is configured to store first voltage information corresponding to a first voltage level, and the second library is configured to store second voltage information corresponding to a second voltage level different from the first voltage level; a bank select pin configured to receive a bank select signal; a voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin; as well as a DC-DC converter configured to generate a panel driving voltage having the first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate the panel driving voltage having the second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit; wherein the voltage information selection circuit receives the bank selection signal having a first level through the bank selection pin in the first mode of the display device, and outputs the first voltage information in response to receiving the bank selection signal having the first level, and The voltage information selection circuit receives the bank selection signal having a second level different from the first level through the bank selection pin in the second mode of the display device, and outputs the second voltage information in response to receiving the bank selection signal having the second level.

5. The power management circuit according to claim 4, wherein: The bank selection pin receives the bank selection signal from a timing controller included in the display device.

6. The power management circuit according to claim 4, wherein: The first mode is a two-dimensional mode in which the display device displays a two-dimensional image, and the second mode is a three-dimensional mode in which the display device displays a three-dimensional image.

7. The power management circuit according to claim 4, wherein: The first mode is a standard dynamic range mode, and the second mode is a high dynamic range mode, wherein in the standard dynamic range mode, the display device displays an image with a standard dynamic range, and in the high dynamic range mode, the display device displays an image with a high dynamic range.

8. A power management circuit for a display device, the power management circuit comprising: A voltage information storage device, comprising N libraries configured to jointly store N voltage information, wherein N is an integer greater than 1; at least one bank select pin configured to receive a bank select signal; a voltage information selection circuit configured to selectively output one voltage information among the N voltage information stored in the N banks in response to the bank selection signal received through the at least one bank selection pin; and A DC-DC converter configured to generate a panel driving voltage having a voltage level corresponding to the one voltage information based on the one voltage information output from the voltage information selection circuit; wherein, during the aging process of the display device, the voltage information selection circuit outputs voltage information corresponding to a first voltage level among the N voltage information in response to a bank selection signal having a first level among the bank selection signals; and Wherein, after the aging process, the voltage information selection circuit outputs voltage information corresponding to the second voltage level among the N voltage information in response to the bank selection signal having the second level among the bank selection signals.

9. A power management circuit for a display device, the power management circuit comprising: A voltage information storage device, comprising N libraries configured to jointly store N voltage information, wherein N is an integer greater than 1; at least one bank select pin configured to receive a bank select signal; a voltage information selection circuit configured to selectively output one voltage information among the N voltage information stored in the N banks in response to the bank selection signal received through the at least one bank selection pin; and A DC-DC converter configured to generate a panel driving voltage having a voltage level corresponding to the one voltage information based on the one voltage information output from the voltage information selection circuit; wherein the voltage information selection circuit outputs voltage information corresponding to a first voltage level among the N voltage information in response to a bank selection signal having a first level among the bank selection signals in a first mode of the display device; and The voltage information selection circuit outputs voltage information corresponding to a second voltage level among the N voltage information in response to a bank selection signal having a second level among the bank selection signals in the second mode of the display device.

10. Display equipment, including: A display panel including a plurality of pixels; a power management circuit configured to generate a panel drive voltage; as well as a panel driver configured to drive the display panel based on the panel driving voltage, Wherein, the power management circuit comprises: A voltage information storage device comprising a first library storing first voltage information corresponding to a first voltage level and a second library storing second voltage information corresponding to a second voltage level different from the first voltage level; a bank select pin configured to receive a bank select signal; a voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin; and a DC-DC converter configured to generate the panel driving voltage having the first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate the panel driving voltage having the second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit; wherein, during the aging process of the display device, the voltage information selection circuit receives the bank selection signal having a first level through the bank selection pin, and outputs the first voltage information in response to the bank selection signal having the first level, and Wherein, after the aging process, the voltage information selection circuit receives the bank selection signal having a second level different from the first level through the bank selection pin, and outputs the second voltage information in response to the bank selection signal having the second level.

11. Display equipment, including: A display panel including a plurality of pixels; a power management circuit configured to generate a panel drive voltage; as well as a panel driver configured to drive the display panel based on the panel driving voltage, wherein the power management circuit comprises: A voltage information storage device comprising a first library storing first voltage information corresponding to a first voltage level and a second library storing second voltage information corresponding to a second voltage level different from the first voltage level; a bank select pin configured to receive a bank select signal; A voltage information selection circuit configured to selectively output the first voltage information stored in the first bank or the second voltage information stored in the second bank in response to the bank selection signal received through the bank selection pin. Voltage information; and a DC-DC converter configured to generate the panel driving voltage having the first voltage level based on the first voltage information when the first voltage information is output from the voltage information selection circuit, and to generate the panel driving voltage having the second voltage level based on the second voltage information when the second voltage information is output from the voltage information selection circuit; wherein the voltage information selection circuit receives the bank selection signal having a first level through the bank selection pin in the first mode of the display device, and outputs the first voltage information in response to receiving the bank selection signal having the first level, and The voltage information selection circuit receives the bank selection signal having a second level different from the first level through the bank selection pin in the second mode of the display device, and outputs the second voltage information in response to receiving the bank selection signal having the second level.

Images