An optimized method for LDPC decoding

Abstract

The application provides an optimization method for LDPC decoding. In the scheme, the hard decision value cw is marked, so that the hard decision value cw of the same position in each iteration is written only once. The cw value of the same position is used in each row of check, and the value written for the first time is used as the standard. The generated chk_err of each row is propagated, and the check is confirmed to pass. In this way, the phenomenon of "false" success can be avoided. In addition, the ping-pong hard decision storage module CWRAM is introduced. Each check is performed after the CWRAM is updated after the last iteration, so that as long as CW*H T =0, the storage in the CWRAM is the correct decoding result. Thus, the possibility of multiple iterations caused by using the first value of each position for check is avoided. The decoding success probability and efficiency of the code block are improved, and power consumption is saved.

Description

[0001] This invention belongs to the field of wireless communication technology, and in particular relates to an optimization method for LDPC decoding. Background Technology

[0002] Low-density parity-check (LDPC) codes, as an optimal error-correcting code technique that approximates the Shannon limit, are widely used in modern communication systems. There are many research and implementation methods for LDPC decoding algorithms; considering both area and performance, the following two methods are currently the most popular:

[0003] One approach is based on standard message propagation scheduling, where updated messages in each iteration are not propagated until the next iteration. The disadvantage of this method is that it requires more iterations and converges slowly. Another approach is based on row or column message propagation scheduling, which ensures that updated messages in an iteration are delivered immediately. The advantage of this method is that it requires fewer iterations and converges quickly. Regardless of the decoding method used, the issue of determining successful decoding is involved. Currently, the main methods for determining successful decoding are as follows:

[0004] The current decoding result is compared with the previous decoding result. If they are the same, the iteration is considered to terminate. The drawback of this method is that, regardless of the decoding method used, there is a certain probability that two consecutive iterations will produce the same decoding result. In other words, this iteration termination strategy can result in "false" successes.

[0005] Based on information such as the modulation and coding scheme (MCS), a preset maximum number of iterations is configured, and iteration only terminates when this maximum number of iterations is reached. The biggest drawback of this method is that it performs many unnecessary iterations, wasting a significant amount of power. Furthermore, it causes the decoding result to be delayed, adding unnecessary latency. Finally, these extra iterations may even cause correctly decoded results to become incorrect.

[0006] In LDPC decoding algorithms based on row or column message propagation scheduling, the number of iterations can be reduced and decoding can be completed quickly because the updated messages are immediately delivered and used during each iteration. Assuming the result after hard decision is CW (1xN dimensional) and the parity-check matrix is ​​H (MxN dimensional), theoretically if... If we consider a 1xM zero matrix, then the CW is the accurate decoding result. In this strategy, each item of the CW is updated many times, while H... T It multiplies each row by the newly generated CW, so there's a high probability that an iteration will fail at the end. However, CW is not actually the correct decoding result.

[0007] Assume that the hard decision result for each iteration is CW=[cw0,cw1,cw2,...,cwn ] represents a 1xN matrix; H T =[h0,h1,h2,...,h m ], where each sub-item h 0、 h1, etc., are all quasi-circular matrices of size TxT. For example... Figure 1 As shown, the method used is... This is a common practice when used as a pass criterion for verification.

[0008] Each hard decision value cw is stored in the hard decision storage module CWRAM. Each time a hard decision value is generated, the generated hard decision array is cyclically shifted to the right according to the offset.

[0009] The pseudocode is as follows:

[0010] Chk_res <= `h0;

[0011] Chk_res <= chk_res ^ `cwa^`cwb^`cwc^`cwd^`cwe^`cwf^`cwg^`cwh;

[0012] Because only one hard decision value (cw) is generated per cycle, the above operation requires eight cycles to complete. Each cycle involves only T bitwise XOR operations, where T is determined based on the LDPC code length and code rate. In fact, the consecutive XOR operations are determined after the LDPC H matrix is ​​finalized. The example shows eight hard decision results that need to be verified; this is merely an example. In reality, the number may be greater than or less than eight, depending on the H matrix.

[0013] Once the verification calculation for the previous row is complete, the calculation proceeds to the next row (the calculation method is the same for each row) until the last row is calculated. The number of elements requiring XOR operations in each row and the total number of rows are determined after the LDPC H matrix is ​​finalized. The result chk_res / chk_err of each row is propagated to the next row. Verification is considered successful only if every row has chk_err=0 and chk_res=0; otherwise, any row with chk_err will result in verification failure.

[0014] These iteration termination criteria show that, although theoretically... This is used to indicate the principle of iteration termination, but since the CW value used at the same position in each iteration may be different, "false" successes can occur. The reasons for these "false" successes are analyzed in detail below:

[0015] The following are the scenarios where a "false" success occurs:

[0016] (a) The first line of validation steps in a certain iteration is as follows:

[0017] A. Initialize chk_res=0, first item cw x Circular right shift off x The bit changes to cw` whose first column is '1'. x ,chk_res = chk_res ^ cw` x

[0018] B. The second item, cw y Circular right shift off y The '1' in the first column became cw` y ,chk_res = chk_res ^ cw` y

[0019] C. Continue in this manner until the last item cw in that row. z Circular right shift off z The first column, '1', became 'cw'. z ,chk_res= chk_res ^ cw` z The total number of terms is the sum of H. T The number of non-zero matrices in the first column is related to H. T It is determined simultaneously with the code length and code rate of a certain LDPC algorithm.

[0020] The condition for successful decoding is that chk_res = 0 after the above line is calculated. If chk_res != 0, then the verification is considered to have failed and chk_err = 1.

[0021] (ii) In a certain iteration, the verification steps for the second row are similar to those for the first row. If this row contains a sub-item that is different from the one in the first row but also contains the same sub-item, let's assume that this sub-item is cw. x And this cw x and the cw used in the previous iteration x They are different values, but coincidentally, the other sub-items in this iteration are the same as this cw. x With the corresponding H T The result of the multiplication still results in che_res=0. At this point, we still think the verification is successful, but in fact, the data used in the same position for this verification is actually different. It is not a true success, but a "false" success.

[0022] Then, perform the validation of other rows following similar steps as above.

[0023] To put it figuratively, in the LDPC decoding algorithm, each line... The operation is equivalent to randomly selecting a few items from the hard-decision cw matrix each time and performing a logical XOR operation. If the final result is 0, then the verification of this row is considered correct. Although the positions of the data taken in each row (the positions of the cw items) are mostly different, there are times when they are in the same position. Coincidentally, in this case, an even number of items have the same position but different values ​​from the previous row. The result of performing a logical XOR operation is exactly 0, which is the root cause of the "false" success.

[0024] To address the shortcomings of existing decoding termination strategies, some optimized and improved technical solutions need to be proposed. Summary of the Invention

[0025] In view of this, the technical problem to be solved by the present invention is to propose some optimized and improved technical solutions for LDPC decoding. In the LDPC decoding verification process, after the verification is passed, the iteration is terminated in time to avoid unnecessary iterations and avoid the possible phenomenon of "false" verification success, thereby improving the decoding success probability and efficiency of this code block, and also saving power consumption.

[0026] This invention provides an optimization method for LDPC decoding, comprising:

[0027] During the verification process of the LDPC decoding algorithm, it is performed line by line. Operation, where cw k The hard decision result matrix CW=[cw0,cw1,cw2,...,cw] generated in each iteration n Sub-items of ]; H T =[h0,h1,h2,...,h m ], where each sub-item h k It is a TxT quasi-cyclic matrix, which is the parity check matrix determined after the LDPC algorithm.

[0028] right The first row of sub-items cw i Perform a circular right shift (off) i The word "off" is mentioned. i The bit is determined by the LDPC algorithm used, resulting in a new sub-item cw. i ', will the sub-item cw i Write to the corresponding location in the hard decision memory module CWRAM, and for each sub-item cw i Set the corresponding flag flag[i]=1 for identification;

[0029] Perform chk_res = chk_res XOR cw iThe operation is performed to determine whether the verification was successful. If chk_res = 0 after the verification of the row, the verification is successful and chk_err = 0; if chk_res = 1, the verification fails and chk_err = 1. XOR is the exclusive OR operation.

[0030] Validate each subsequent line: check the identifier to determine the value of the item cw. j Whether it has been used (flag[j]=0 indicates it has not been used, otherwise it indicates it has been used); if it has been used, then retrieve the item from the hard decision storage module CWRAM and perform a circular right shift off. j The position is obtained as cw j ', perform chk_res = chk_res XOR cw j The calculation of 'off' j The bit is determined by the LDPC algorithm used; if it has not been used before, the current cw is used. j Perform a circular right shift (off) j cw generated after bit j ', the off j The bits are calculated after being determined by the LDPC algorithm used. And set the corresponding flag flag[j]=1 for this cw j Mark it and set the current value cw j Write to the corresponding location in the hard decision storage module CWRAM; if chk_res = 0 after the row verification is completed, the verification is successful and chk_err = 0; if chk_res = 1, the verification fails and chk_err = 1.

[0031] After all rows are checked, if chk_err=0 and chk_res=0, then the value stored in the current CWRAM is determined to be the final decoding result, and subsequent decoding operations are stopped.

[0032] Furthermore, the method also includes:

[0033] Once decoding is complete, a flag is set to prevent data from being written to CWRAM in the next iteration, thus preventing erroneous data from being generated during additional iterations.

[0034] Another optimization method for LDPC decoding provided by this invention includes:

[0035] At least two storage modules, CWRAM, are set up for storing CW, and the CWRAM adopts the structure of ping-pong RAM;

[0036] Each iteration uses one of the RAMs to store the hard decision value generated in the current iteration, while the CW value at the appropriate position is read from another CWRAM that already stores the hard decision value of the previous iteration, according to the rules of the H matrix.

[0037] And according to the offset value off at that position i off i for cw i The corresponding offset value, off i The cw value is obtained by cyclically shifting the CW value to the right, as determined by the LDPC algorithm used. i Then, an XOR operation is performed with chk_res, which is initially set to 0 each time. After a row is validated, if chk_res=0, then chk_err=0; otherwise, chk_err=1. After all rows are validated, if chk_res=0 for each row, then chk_err=0; otherwise, if chk_res=1 for any row, then chk_err=1.

[0038] At the end of the verification, the value of chk_err=0 and chk_res=0 is used to determine whether the verification passed.

[0039] If chk_err=0 and chk_res=0, the verification is deemed successful, and the hard decision stored in the CW RAM of the CW storage module is determined to be the final decoding result. For the foregoing and related purposes, one or more embodiments are included, as will be described in detail below. The following description and accompanying drawings illustrate certain exemplary aspects, and are merely some of the various ways in which the principles of the various embodiments can be utilized. Other benefits and novel features will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, and the disclosed embodiments are intended to include all such aspects and their equivalents. Attached Figure Description

[0040] Figure 1 It is used in LDPC decoding provided by existing technology Implementation principle diagram when used as a verification pass criterion;

[0041] Figure 2 This is a schematic diagram of an optimized scheme for LDPC decoding proposed in an embodiment of the present invention.

[0042] Figure 3 This is a schematic diagram of another optimized scheme for LDPC decoding proposed in another embodiment of the present invention. Detailed Implementation

[0043] The following description and accompanying drawings fully illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. In this document, these embodiments of the invention may be referred to individually or collectively with the term "invention," which is merely for convenience and is not intended to automatically limit the scope of the application to any single invention or inventive concept if more than one invention is disclosed.

[0044] The improvement proposed in this invention is to eliminate H T When multiplying with the hard decision value CW updated in each row, changes are found in CW before and after.

[0045] This invention provides an optimization method for LDPC decoding, comprising:

[0046] During the verification process of the LDPC decoding algorithm, it is performed line by line. Operation, where cw k The hard decision result matrix CW=[cw0,cw1,cw2,...,cw] generated in each iteration n Sub-items of ]; H T =[h0,h1,h2,...,h m ], where each sub-item h k It is a TxT quasi-circular matrix, which is the parity check matrix determined after the LDPC algorithm is determined;

[0047] right The first row of sub-items cw i Perform a circular right shift (off) i The bit (which is determined during the LDPC algorithm) is used to obtain the new sub-item cw. i ', will the sub-item cw i Write the corresponding position in the hard decision CWRAM, and for each sub-item cw i Set the corresponding flag flag[i]=1 for identification;

[0048] Perform chk_res = chk_res XOR cw i The XOR operation is used to determine whether the verification was successful. If chk_res = 0 after the verification of the row, the verification is successful and chk_err = 0; if chk_res = 1, the verification fails and chk_err = 1. XOR is the 'exclusive OR operation'.

[0049] Validate each subsequent line: check the identifier to determine the value of the item cw. j Whether it has been used (flag[j]=0 indicates it has not been used, otherwise it indicates it has been used); if it has been used, then retrieve the item from the hard-decision CWRAM and perform a circular right shift off. j The bits (which are determined when the LDPC algorithm is implemented) are used to obtain cw. j ', perform chk_res = chk_resXOR cw j The calculation of '; if it has not been used before, the current cw is used. j Perform a circular right shift (off) j The cw generated after the bits (which are already determined when the LDPC algorithm is used) j ', then calculate And set the corresponding flag flag[j]=1 for this cw j Mark it and set the current value cw j Write to the corresponding position in the hard decision CWRAM; if chk_res = 0 after the line is checked, the check is successful and chk_err = 0; if chk_res = 1, the check fails and chk_err = 1.

[0050] After each row is validated, an "OR" operation is performed on chk_err. That is, if the validation of a row fails, then chk_err = 1, and only if the validation of all rows passes will chk_err = 0.

[0051] If chk_err=0 after all rows are checked, it is determined that the value stored in the current CW RAM is the final decoding result, and subsequent decoding operations are stopped. Here, OR stands for 'or operation'.

[0052] The method further includes:

[0053] Once decoding is complete, a flag is set to prevent data from being written to CW RAM during the next iteration.

[0054] This prevents additional iterations from generating erroneous data that could affect the hard decision values ​​in the previously correctly validated CW RAM.

[0055] This ensures that the CW RAM only stores the first occurrence of each sub-item in each iteration of the decision result matrix CW, thus ensuring that the verified CW RAM contains correct hard decision values.

[0056] If you want to use the last occurrence of each sub-item in each iteration of CW for validation.

[0057] Another optimization method for LDPC decoding provided by this invention includes:

[0058] Configure at least two storage modules (CW RAM) for storing CW, which adopt the structure of ping-pong RAM;

[0059] Each iteration uses one RAM to store the hard decision value generated in the current iteration, while the CW value at the appropriate position is read from another RAM that already stores the hard decision value of the previous iteration according to the rules of the H matrix.

[0060] And according to the offset value at that position, for example, CW i The corresponding offset value is off i This off i The value of CW is determined when the LDPC algorithm is implemented; it is obtained by cyclically shifting the CW value to the right. i Then, an XOR operation is performed with chk_res, which is initially set to 0 each time: chk_res = chk_res XOR cw i After a row is validated, if chk_res=0, then chk_err=0; otherwise, chk_err=1. After all rows are validated, if chk_res=0 for each row, then chk_err=0; otherwise, if chk_res=1 for any row, then chk_err=1.

[0061] At the end of the verification, the value of chk_err=0 and chk_res=0 is used to determine whether the verification passed.

[0062] If chk_err=0 and chk_res=0, the verification is considered successful, and the hard decision stored in the CW memory module (RAM) is determined to be the final decoding result.

[0063] To make the principles, features, and advantages of the present invention clearer, the invention will be described in detail below with reference to specific embodiments.

[0064] Example 1

[0065] The new method proposed in this embodiment introduces a variable [m-1:0]w_flag. If w_flag[i]=1, it means that the cw sub-item at position i is used in this row. The specific improvement method is as follows:

[0066] 1. The first line of validation steps in a certain iteration is as follows:

[0067] A. Initialize chk_res=0, first item cw x Circular right shift offx The '1' in the first column became cw` x ,chk_res = chk_res ^ cw` x Set the flag w_flag[x]=1 and write the sub-item to the corresponding location in the hard decision RAM.

[0068] B. The second item, cw y Circular right shift off y The first column, '1', became 'cw'. y ,chk_res = chk_res ^ cw` y Set the flag w_flag[y]=1, and write the sub-item to the corresponding location in the hard decision RAM.

[0069] C. Continue in this manner until the last item cw in that row. z Circular right shift off z The first column, '1', became 'cw'. z ,chk_res= chk_res ^ cw` z If w_flag[z] = 1, write the sub-item to the corresponding location in the hard decision RAM. If chk_res != 0 at this time, then the verification is considered to have failed, and chk_err = 1.

[0070] 2. The subsequent line verification steps after the start of a certain iteration are as follows:

[0071] A. Check whether w_flag[i] is '1' to determine the value of cw. i If the item has already been used, retrieve it from the hard-decision RAM and circularly shift it right by off. i The '1' in the first column became cw` i , perform chk_res = chk_res ^ cw` i The calculation means using the old value instead of the new value.

[0072] B. For other items, the same procedure as for the first item above is followed: first, check if the corresponding w_flag is '1' to determine if the item has been used. If it has been used, calculate using the old value; otherwise, use the current value, mark the corresponding w_flag as '1', and write the current value to the corresponding location in the hard decision RAM. If chk_res != 0 when the line verification ends, the verification is considered to have failed, and chk_err = chk_err|1 (this operation means that chk_err will record the result of the previous line verification; as long as any line verification fails, chk_err will retain the value 1).

[0073] 3. After all rows are checked, chk_res=0 and chk_err=0. Then it is assumed that the final decoding result is now stored in the CW RAM, and the decoding operation can be stopped.

[0074] It should be noted that the verification operation always produces a result only after the current iteration is completely finished, so it is very likely that the next iteration will begin when the result is obtained. Handling this situation is simple: just set a flag when decoding is considered complete in step three above. This flag will prevent the new iteration from writing data to the CWRAM, thus avoiding redundant iterations that could corrupt the correct hard decision value in the CWRAM.

[0075] Figure 2 The image shown is the improved version proposed in this embodiment. Implementation method:

[0076] Each cw is stored at the corresponding location in the hard decision RAM; each time a hard decision value is generated, the generated hard decision array is cyclically shifted to the right according to the offset.

[0077] Assuming the index range of matrix H is 0~N, the pseudocode is as follows:

[0078] W_flag <= N`h0;

[0079] Chk_res <= T`h0; / / Initial value

[0080] Chk_res <= chk_res ^ `cwa^`cwb^`cwc^`cwd^`cwe^`cwf^`cwg^`cwh;

[0081] W_flag <= N`h4518a4; / / Where the position of 1 indicates the position of idxa / idxb / idxc etc. The numbers in the example have no special meaning and are only for the convenience of describing the invention.

[0082] When calculating the checksum of the second row, the `w_flag` is checked. If the corresponding position is 1, it means that the hard decision result at this position was previously used in the checksum of the first row. In this case, the currently generated `cw` is not used in the calculation of the second row. Instead, the old value used in the first row is read from the hard decision RAM and used in the checksum calculation of the second row. The decision criterion for the checksum result `chk_res` of this row is still the same as that of the first row.

[0083] The calculation of the check values ​​for subsequent rows is performed in a similar manner to the second row above.

[0084] The validation is determined by the final chk_res / chk_err. If chk_err=0 and chk_res=0, then it passes. If chk_res=1 even once, then it fails.

[0085] It can be seen that the improved verification calculation process introduces the w_flag signal, which can ensure that only one value is used for the CW value at the same position in this iteration. This avoids the situation where multiple CW values ​​at the same position in a row change, but the verification result of that row happens to still pass, thus avoiding the phenomenon of "false" success.

[0086] 【Example 2】

[0087] After understanding the technical solution of Implementation Example 1, it can be found that although it can guarantee that at the end of the current iteration, if chk_res=0 and chk_err=0, then the hard decision RAM stores the final correct decoding result, w_flag only stores the first value of the hard decision at a certain position in the entire iteration. Since the last update value of the iteration may be the correct hard decision value, it may be necessary to iterate several times to achieve chk_res=0. This wastes some unnecessary computation time. Therefore, the following improvement scheme is proposed:

[0088] like Figure 3 The diagram shows another optimization scheme for LDPC decoding proposed in this embodiment of the invention.

[0089] Write the CW position recorded by idx into RAM, one CW data point per frame.

[0090] According to the position to be verified in each row of the H matrix, read out one CW value to be verified in each frame;

[0091] Based on the offset value accompanying the position to be verified in each row of the H matrix, the CW value read from RAM is cyclically shifted to the right.

[0092] The above structure is the decision circuit structure for one iteration. The circuit structure is the same for subsequent iterations, except that the CW RAM uses a different ping-pong RAM.

[0093] The CW RAM uses a ping-pong RAM structure. Each iteration uses one RAM to store the hard decision value generated in the current iteration, while the appropriate CW value is read from another RAM that already stores the previous hard decision value, according to the rules of the H matrix. The CW value is then cyclically shifted right by the offset associated with that position, and then XORed with chk_res, which is initially set to 0 each time. The chk_err value for each row is retained. At the end of the verification process, if chk_err = 0 and chk_res = 0, the verification passes; otherwise, it fails. When the verification passes, the final decoding result is stored in the CW RAM.

[0094] As can be seen from the implementation structure of the scheme described in Embodiment 2, this scheme avoids the potential multiple iterations problem in Embodiment 1, but it uses an additional CW RAM. Both schemes employ theoretically validating equations. Furthermore, the CW value at the same position is consistent during each verification. The resulting structure is always a correct decoding result.

[0095] Both of the above schemes can achieve the ideal strategy of terminating the iteration early. Suppose that the maximum number of iterations configured by the software during this decoding is M, and the actual number of iterations used is N. This means that MN iterations of time are saved, and this iteration time can be given to the next code block. Thus, the maximum decoding time of this code block becomes (2M-N), which increases the probability that this code block is successfully decoded.

[0096] Suppose the maximum number of decoding attempts is M, and decoding still fails after M-1 attempts. For the first approach, the w_flag function is disabled during the Mth decoding attempt, allowing the complete data of this iteration to be stored in the CW RAM. This means the CW value at the same location will store the last updated value. For the second approach, the result of the Mth decoding attempt will also be used as the final output decoding result.

[0097] In summary, the solution provided by this invention marks the hard decision value cw (specifically, sets the w_flag flag), ensuring that the hard decision value cw at the same position is written only once in each iteration. For each row of verification, if the same cw value is used, the value written the first time is used. The chk_err generated in each row is propagated, and verification is considered successful only if chk_err=1 throughout the entire iteration. This successfully avoids the phenomenon of "false" successes.

[0098] In addition, a ping-pong hard-decision storage module, CWRAM, was introduced. Each verification is performed after the CWRAM has been updated since the last iteration, thus ensuring that as long as... Therefore, the CWRAM will definitely store the correct decoding result. This avoids the possibility of needing multiple iterations due to using the first value at each position for verification.

[0099] When decoding consecutive code blocks, the number of iterations (time) saved by ending the current code block early is given to the next code block, thereby increasing the probability of successful decoding of the next code block.

[0100] Compared with existing LDPC iteration termination techniques, the technical solution of this invention has the following advantages:

[0101] 1. Using theoretical verification equations However, the CW value should either be the first occurrence or the last occurrence, thus avoiding the "false" success phenomenon that occurs in the currently popular LDPC decoding algorithms based on row or column updates.

[0102] 2. After the verification is passed, the iteration can be terminated early with confidence, thereby saving power consumption.

[0103] 3. By using the preset maximum number of iterations, when decoding consecutive code blocks, the iteration time saved by the previous code block can be allocated to the current code block, which may increase the success rate of decoding the current code block.

[0104] Those skilled in the art will understand that the various exemplary method steps and apparatus units described herein in conjunction with the disclosed embodiments can be implemented in electronic hardware, software, or a combination of both. To clearly illustrate the interchangeability between hardware and software, the various exemplary steps and units have been generally described above in their functional form. Whether this functionality is implemented in hardware or software depends on the specific application and the design constraints implemented by the entire system. Those skilled in the art can implement the described functionality in various ways for each specific application, but the result of such implementation should not be construed as departing from the scope of the invention.

[0105] The steps of the methods described in conjunction with the above-disclosed embodiments can be directly embodied in hardware, software modules executed by a processor, or a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the art. A typical storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. In an alternative embodiment, the storage medium is a component of the processor. The processor and storage medium may reside in an ASIC. This ASIC may reside in a user station. In an alternative embodiment, the processor and storage medium may exist as discrete components in a user station.

[0106] Based on the disclosed embodiments, those skilled in the art can implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can also be applied to other embodiments without departing from the scope and spirit of the invention. The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An optimization method for LDPC decoding, characterized in that, include: During the verification process of the LDPC decoding algorithm, cw is performed line by line. k *H T Operation, where cw k The hard decision result matrix CW = [cw0, cw1, cw2, ..., cw] generated in each iteration. n Sub-items of ]; H T =[h0,h1,h2,...,h m ], where each sub-item h k It is a TxT quasi-cyclic matrix, which is the parity check matrix determined after the LDPC algorithm. For CW k *H T The first row of the operation results contains the sub-items cw. i Perform a circular right shift (off) i The bit, the off i The bit is determined by the LDPC algorithm used, resulting in a new sub-item cw. i ', will the sub-item cw i Write to the corresponding location in the hard decision memory module CWRAM, and for each sub-item cw i Set the corresponding flag flag[i] = 1 for identification; Perform chk_res = chk_res XOR cw i The operation is called 'XOR', where chk_res is the verification result and chk_err is a flag indicating that the verification result of chk_res failed, to determine whether the verification was successful. If chk_res = 0 after the verification of this row, the verification is successful and chk_err = 0; if chk_res = 1, the verification fails and chk_err = 1. Validate each subsequent line: check the identifier to determine the value of the item cw. j Whether it has been used; flag[j] = 0 means it has not been used, otherwise it means it has been used; If it has been used, the entry is retrieved from the hard decision memory (CWRAM) module and then cyclically shifted right (off). j The position is obtained as cw j ', perform chk_res = chk_res XOR cw j The calculation of 'off' j The bit is determined by the LDPC algorithm used; if it has not been used before, the current cw is used. j Perform a circular right shift (off) j cw generated after bit j ', the off j After the bits are determined by the LDPC algorithm used, chk_res is calculated as chk_res XOR cw. j ', and set the corresponding flag flag[j]=1 for this cw j Mark it and set the current value cw j Write to the corresponding location in the hard decision storage module CWRAM; if chk_res = 0 after the row verification is completed, the verification is successful and chk_err = 0; if chk_res = 1, the verification fails and chk_err = 1. After all rows are checked, if chk_err = 0 and chk_res = 0, then the value stored in the current CWRAM is determined to be the final decoding result, and subsequent decoding operations are stopped.

2. The optimization method for LDPC decoding as described in claim 1, characterized in that, Also includes: Once decoding is complete, a flag is set to prevent data from being written to CWRAM in the next iteration, thus preventing erroneous data from being generated during additional iterations.

3. An optimization method for LDPC decoding, characterized in that, include: At least two storage modules CWRAM are provided for storing CW, and the storage modules CWRAM adopt the structure of ping-pong RAM; Each iteration uses one of the storage modules CWRAM to store the hard decision value generated in the current iteration, while reading the appropriate CW value from another CWRAM that already stores the hard decision value from the previous iteration. And according to the offset value off at that position i off i for cw i The corresponding offset value, off i The cw value is obtained by cyclically shifting the CW value to the right, as determined by the LDPC algorithm used. i Then, an XOR operation is performed with chk_res, which is initially set to 0 each time: chk_res = chk_res XOR cw i After a row is validated, if chk_res = 0, then chk_err = 0; otherwise, chk_err = 1. After all rows are validated, if chk_res = 0 for each row, then chk_err = 0; otherwise, if chk_res = 1 for any row, then chk_err = 1. At the end of the verification, the verification is determined based on the values ​​of chk_err=0 and chk_res=0. If chk_err=0 and chk_res=0, the verification is deemed to have passed, and the hard decision stored in the CW RAM of the CW storage module is determined to be the final decoding result.

Images