Multistage power amplifier and amplifier array

Abstract

A multi-stage amplifier includes a driver stage transistor characterized by a first power density, and a final stage transistor characterized by a second power density greater than the first power density. A first drain bias circuit is coupled to a first drain terminal of the driver stage transistor and configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to a second drain terminal of the final stage transistor and configured to provide a second drain bias voltage to the second drain terminal, wherein the second drain bias voltage is equal to the first drain bias voltage. An inter-stage impedance matching circuit is coupled between the first drain terminal and a gate terminal of the final stage transistor. The multi-stage amplifier can be included in a Doherty power amplifier, a transceiver, and / or an array of transceivers.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to multi-stage power amplifiers. Background Technology

[0002] Massive MIMO (Multiple-Input Multiple-Output) base stations provide bidirectional, multiplexed communication to multiple wireless devices (i.e., user equipment) within a cell served by the base station. A typical base station includes a remote radio unit (or remote radio head) connected to an array of antenna elements (e.g., tens to hundreds of antennas) configured to communicate with the wireless devices via an air interface. The remote radio unit includes a transceiver front end with a transceiver array, where each transceiver is coupled to one antenna in the antenna array (i.e., there is a 1:1 correlation between transceivers and antenna elements). For example, a typical massive MIMO transceiver array can include up to 4096 transceivers (e.g., in an 8x8 array, also known as an 8T or 8T8R array) starting from 64 transceivers (e.g., in a 64x64 transceiver array, also known as a 64T or 64T64R array), but smaller and larger antenna and transceiver arrays are also considered. Given the inherent complexity of so many transceivers in a large-scale MIMO transceiver array, system designers are constantly striving to achieve high-performance systems that can meet increasingly stringent size and power consumption requirements. Summary of the Invention

[0003] According to one aspect of the present invention, a multi-stage amplifier is provided, comprising:

[0004] A driver-level transistor having a first gate terminal and a first drain terminal, wherein the driver-level transistor is characterized by having a first power density;

[0005] A first drain bias circuit is coupled to the first drain terminal of the driver stage transistor and is configured to provide a first drain bias voltage to the first drain terminal.

[0006] A final stage transistor having a second gate terminal and a second drain terminal, wherein the final stage transistor is characterized by having a second power density that is greater than the first power density.

[0007] A second drain bias circuit, coupled to the second drain terminal of the final stage transistor, and configured to provide a second drain bias voltage to the second drain terminal, wherein the second drain bias voltage is equal to the first drain bias voltage; and

[0008] An interstage impedance matching circuit is coupled between the first drain terminal and the second gate terminal.

[0009] According to one or more embodiments of the present invention, the ratio of the first power density of the driving stage transistor to the second power density of the final stage transistor is in the range of 1:2 to 1:8.

[0010] According to one or more embodiments of the present invention, the driving stage transistor is a silicon-based semiconductor field-effect transistor; and the final stage transistor is a III-V group semiconductor field-effect transistor.

[0011] According to one or more embodiments of the present invention, the driving stage transistor is a laterally diffused metal-oxide-semiconductor field-effect transistor, and the first power density is in the range of about 1.0 W / mm to about 3.0 W / mm; and the final stage transistor is a gallium nitride-based high electron mobility transistor, and the second power density is in the range of about 5.0 W / mm to about 15.0 W / mm.

[0012] According to one or more embodiments of the present invention, the first drain bias voltage and the second drain bias voltage are in the range of 30 volts to 60 volts.

[0013] According to one or more embodiments of the present invention, the driving stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die; the final stage transistor is integrally formed in a second semiconductor die; and the interstage impedance matching circuit includes a connector between the first semiconductor die and the second semiconductor die.

[0014] According to one or more embodiments of the present invention, the amplifier further includes: a final-stage gate bias circuit coupled to the second gate terminal and integrally formed in the second semiconductor die; and a decoupling capacitor coupled between the first drain bias circuit and the final-stage gate bias circuit.

[0015] According to a second aspect of the present invention, a Doherty power amplifier is provided, comprising:

[0016] A first magnification path, the first magnification path includes

[0017] A first driving stage transistor, having a first gate terminal and a first drain terminal, wherein the first driving stage transistor is characterized by having a first power density.

[0018] A first drain bias circuit is coupled to the first drain terminal of the first driver stage transistor and configured to provide a first drain bias voltage to the first drain terminal.

[0019] A first terminal transistor having a second gate terminal and a second drain terminal, wherein the first terminal transistor is characterized by having a second power density that is greater than the first power density.

[0020] A second drain bias circuit, coupled to the second drain terminal of the first final stage transistor, and configured to provide a second drain bias voltage to the second drain terminal; and

[0021] The second amplification path includes...

[0022] The second driving stage transistor has a third gate terminal and a third drain terminal, wherein the third driving stage transistor is characterized by having the first power density.

[0023] A third drain bias circuit is coupled to the third drain terminal of the second driver stage transistor and configured to provide a third drain bias voltage to the third drain terminal.

[0024] The second final-stage transistor has a fourth gate terminal and a fourth drain terminal, wherein the second final-stage transistor is characterized by having the second power density, and

[0025] A fourth drain bias circuit is coupled to the fourth drain terminal of the second final-stage transistor and configured to provide a fourth drain bias voltage to the fourth drain terminal, wherein the first drain bias voltage, the second drain bias voltage, the third drain bias voltage, and the fourth drain bias voltage are equal. According to one or more embodiments of the invention, the ratio of the first power density to the second power density is in the range of 1:2 to 1:8.

[0026] According to one or more embodiments of the present invention, the first driving stage transistor and the second driving stage transistor are silicon-based semiconductor field-effect transistors; and the first terminal stage transistor and the second terminal stage transistor are III-V group semiconductor field-effect transistors.

[0027] According to one or more embodiments of the present invention, the Doherty power amplifier further includes: a power splitter having an input terminal and a first output terminal and a second output terminal, wherein the first output terminal is electrically coupled to a first gate terminal, the second output terminal is electrically coupled to a third gate terminal, and the power splitter is configured to receive an input RF signal at the input terminal of the power splitter, and to split the power of the input RF signal into a first RF signal and a second RF signal generated at the first output terminal and the second output terminal of the power splitter.

[0028] According to another aspect of the present invention, a transceiver array is provided, comprising:

[0029] Transceiver array substrate;

[0030] A first transceiver, coupled to the transceiver array substrate and having a first multi-stage amplifier, the first multi-stage amplifier having a first driver stage transistor with a first drain terminal, a first final stage transistor with a second drain terminal, and a first bias circuit system coupled to the first drain terminal and the second drain terminal;

[0031] A second transceiver, coupled to the transceiver array substrate and having a second multi-stage amplifier, the second multi-stage amplifier having a second driver stage transistor with a third drain terminal, a second final stage transistor with a fourth drain terminal, and a second bias circuit system coupled to the third drain terminal and the fourth drain terminal; and

[0032] An interconnect bias power line network, coupled to the transceiver array substrate and electrically connected to the first bias circuitry and the second bias circuitry, facilitates the provision of a single drain bias voltage to the first drain terminal, the second drain terminal, the third drain terminal, and the fourth drain terminal.

[0033] According to one or more embodiments of the present invention, the transceiver array further includes: a DC drain bias voltage source coupled to the interconnect bias power line network and configured to provide the individual drain bias voltage.

[0034] According to one or more embodiments of the present invention, the first multistage amplifier forms part of a first Doherty power amplifier; and the second multistage amplifier forms part of a second Doherty power amplifier.

[0035] According to one or more embodiments of the present invention, the first driving stage transistor and the second driving stage transistor are characterized in that they have a first power density; and the first terminal stage transistor and the second terminal stage transistor are characterized in that they have a second power density that is greater than the first power density.

[0036] According to one or more embodiments of the present invention, the ratio of the first power density to the second power density is in the range of 1:2 to 1:8.

[0037] According to one or more embodiments of the present invention, the first driving stage transistor and the second driving stage transistor are laterally diffused metal-oxide-semiconductor field-effect transistors, and the first power density is in the range of about 1.0 W / mm to about 3.0 W / mm; and the first terminal stage transistor and the second terminal stage transistor are gallium nitride-based high electron mobility transistors, and the second power density is in the range of about 5.0 W / mm to about 15.0 W / mm.

[0038] According to one or more embodiments of the present invention, the first driving stage transistor and the second driving stage transistor are silicon-based semiconductor field-effect transistors; and the first terminal stage transistor and the second terminal stage transistor are III-V group semiconductor field-effect transistors. Attached Figure Description

[0039] A more complete understanding of the subject matter can be obtained by referring to the detailed embodiments and claims when the following figures are considered in conjunction with them, wherein similar reference numerals in the figures refer to similar elements.

[0040] Figure 1 This is a simplified diagram of a portion of a massive MIMO system with an 8T transceiver array according to an embodiment;

[0041] Figure 2 This is a simplified block diagram of a transceiver suitable for use in a large-scale MIMO transceiver array according to an embodiment;

[0042] Figure 3 This is an embodiment based on the example. Figure 2 A top view of the transceiver module of the transceiver;

[0043] Figure 4 This is a simplified block diagram of a two-stage power amplifier according to an example embodiment;

[0044] Figure 5 This is a circuit diagram of an embodiment of a two-stage cascaded amplifier according to an example embodiment; and

[0045] Figure 6This is a simplified block diagram of a Doherty power amplifier that can be used in a transmitter group according to an embodiment. Detailed Implementation

[0046] An embodiment of a multi-stage amplifier includes: a driver stage transistor characterized by having a first power density; and a final stage transistor characterized by having a second power density greater than the first power density. A first drain bias circuit is coupled to the first drain terminal of the driver stage transistor and configured to provide a first drain bias voltage to the first drain terminal. A second drain bias circuit is coupled to the second drain terminal of the final stage transistor and configured to provide a second drain bias voltage to the second drain terminal, wherein the second drain bias voltage is equal to the first drain bias voltage. An interstage impedance matching circuit is coupled between the first drain terminal and the gate terminal of the final stage transistor.

[0047] According to another embodiment, the ratio of the first power density of the driver stage transistor to the second power density of the final stage transistor is in the range of 1:2 to 1:8. According to yet another embodiment, the driver stage transistor is a silicon-based semiconductor field-effect transistor, and the final stage transistor is a group III-V semiconductor field-effect transistor. According to yet another embodiment, the driver stage transistor is a laterally diffused metal-oxide-semiconductor field-effect transistor, and the first power density is in the range of about 1.0 W / mm to about 3.0 W / mm, and the final stage transistor is a gallium nitride-based high electron mobility transistor, and the second power density is in the range of about 5.0 W / mm to about 15.0 W / mm. According to yet another embodiment, the first drain bias voltage and the second drain bias voltage are in the range of 30 volts to 60 volts. According to yet another embodiment, the driver stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die, the final stage transistor is integrally formed in a second semiconductor die, and an interstage impedance matching circuit is included in a connector between the first semiconductor die and the second semiconductor die. According to another embodiment, the final-stage gate bias circuit is coupled to the second gate terminal and integrally formed in the second semiconductor die, and the decoupling capacitor is coupled between the first drain bias circuit and the final-stage gate bias circuit.

[0048] Embodiments of the Doherty power amplifier include a first amplification path and a second amplification path. The first amplification path includes: a first driver stage transistor having a first gate and a first drain; a first drain bias circuit coupled to the first drain of the first driver stage transistor and configured to provide a first drain bias voltage to the first drain; a first final stage transistor having a second gate and a second drain; and a second drain bias circuit coupled to the second drain of the first final stage transistor and configured to provide a second drain bias voltage to the second drain. The second amplification path includes: a second driver stage transistor having a third gate and a third drain; a third drain bias circuit coupled to the third drain of the second driver stage transistor and configured to provide a third drain bias voltage to the third drain; a second final stage transistor having a fourth gate and a fourth drain; and a fourth drain bias circuit coupled to the fourth drain of the second final stage transistor and configured to provide a fourth drain bias voltage to the fourth drain. The first drain bias voltage, the second drain bias voltage, the third drain bias voltage, and the fourth drain bias voltage are equal. The first driving stage transistor and the second driving stage transistor are characterized by having a first power density, and the first final stage transistor and the second final stage transistor are characterized by having a second power density that is greater than the first power density.

[0049] According to another embodiment, the ratio of the first power density to the second power density is in the range of 1:2 to 1:8. According to yet another embodiment, the first and second driver stage transistors are silicon-based semiconductor field-effect transistors, and the first and second final stage transistors are III-V group semiconductor field-effect transistors. According to yet another embodiment, the Doherty power amplifier further includes a power splitter having an input terminal and a first and a second output terminal, wherein the first output terminal is electrically coupled to a first gate terminal, the second output terminal is electrically coupled to a third gate terminal, and the power splitter is configured to receive an input RF signal at its input terminal and to split the power of the input RF signal into a first RF signal and a second RF signal generated at the first and second output terminals of the power splitter.

[0050] An embodiment of the transceiver array includes a transceiver array substrate and a first transceiver and a second transceiver coupled to the transceiver array substrate. The first transceiver has a first multistage amplifier having a first driver stage transistor with a first drain terminal, a first terminal stage transistor with a second drain terminal, and a first bias circuit system coupled to the first and second drain terminals. The second transceiver has a second multistage amplifier having a second driver stage transistor with a third drain terminal, a second terminal stage transistor with a fourth drain terminal, and a second bias circuit system coupled to the third and fourth drain terminals. The transceiver array also includes an interconnect bias power line network coupled to the transceiver array substrate and electrically connected to the first and second bias circuit systems to facilitate the provision of a single drain bias voltage to the first, second, third, and fourth drain terminals.

[0051] According to another embodiment, the transceiver array further includes a DC drain bias voltage source coupled to an interconnect bias power line network and configured to provide a single drain bias voltage. According to yet another embodiment, a first multistage amplifier forms part of a first Doherty power amplifier, and a second multistage amplifier forms part of a second Doherty power amplifier. According to yet another embodiment, the first and second driver stage transistors are characterized by having a first power density, and the first and second final stage transistors are characterized by having a second power density greater than the first power density. According to yet another embodiment, the ratio of the first power density to the second power density is in the range of 1:2 to 1:8. According to yet another embodiment, the first and second driver stage transistors are laterally diffused metal-oxide-semiconductor field-effect transistors, and the first power density is in the range of about 1.0 W / mm to about 3.0 W / mm, and the first and second final stage transistors are gallium nitride-based high electron mobility transistors, and the second power density is in the range of about 5.0 W / mm to about 15.0 W / mm. According to another embodiment, the first driving stage transistor and the second driving stage transistor are silicon-based semiconductor field-effect transistors, and the first terminal stage transistor and the second terminal stage transistor are III-V group semiconductor field-effect transistors.

[0052] Figure 1 This is a simplified diagram of a portion of a massive MIMO system 100 with an 8T transceiver array according to an embodiment. System 100 includes a baseband and intermediate frequency (IF) subsystem 110, a transceiver array 130, and an antenna array 150. System 100 can be implemented, for example, in a cellular base station, but it can also be implemented in another type of wireless system besides a base station.

[0053] The baseband and IF subsystem 110 is configured to perform baseband and IF processing on multiple signals (“TX signals” herein) for transmission and to provide these signals to the transceiver array 130 via multiple conductors 120. Furthermore, the baseband and IF subsystem 110 is configured to receive and process multiple signals (“RX signals” herein) from the transceiver array 130 via the multiple conductors 120. For example, the multiple conductors 120 may include multiple coaxial cables or other conductors.

[0054] Transceiver array 130 includes a plurality of identical transceivers 132, which may be arranged in multiple rows and columns. In some embodiments, all transceivers 132 in array 130 may be coupled to a common transceiver array substrate 134 (e.g., a multilayer printed circuit board (PCB) or other type of substrate), which includes multiple transceiver sockets into which transceivers 132 are inserted, or multiple transceiver mounting areas to which transceivers 132 are coupled (e.g., soldered). In the illustrated embodiment, transceiver array 130 includes 8 rows and 8 columns of transceivers 132, i.e., a total of 64 transceivers 132 in array 130. In other embodiments, the number of rows and / or columns of transceivers may be smaller or larger, and / or the number of rows may be different from the number of columns. In other embodiments, subarrays of transceivers 132 may be coupled to different transceiver substrates. To avoid Figure 1 The mess is such that only one connection between connector 120 and transceiver 132 is shown in the upper left corner of transceiver array 130. Based on the description herein, those skilled in the art will understand that transceiver array 130 may include dedicated connections between each connector 120 and each transceiver 132.

[0055] Transceiver array 130 is electrically coupled to antenna array 150, which includes multiple antennas 152. According to an embodiment, system 100 is a time-division duplex (TDD) system, and each antenna 152 is configured to both transmit radio frequency (RF) signals (“RF TX signals” herein) via an air interface and receive RF signals (“RF RX signals” herein) from an air interface. In such embodiments, each transceiver 132 in transceiver array 130 is coupled to a different antenna among the antennas 152 in antenna array 150 (i.e., there is a 1:1 correlation between the number of transceivers 132 and the number of antennas 152). To avoid Figure 1 The mess is such that only one connector between transceiver 132 and antenna 152 is shown in the upper right corner of transceiver array 130. Based on the description herein, those skilled in the art will understand that transceiver array 130 may include dedicated connectors between each transceiver 132 and each antenna 152.

[0056] As will be combined later Figure 2 In more detail, each transceiver 132 includes a transmitter (e.g., Figure 2 Transmitter 240), receiver (e.g., Figure 2 The receiver 260) and transmit / receive (TX / RX) switch (e.g., Figure 2 (TX / RX switch 270). As will be combined later. Figure 4 To explain in more detail, the transmitter of each transceiver 132 includes one or more multistage amplifiers (e.g., Figure 4 A multistage amplifier 400), wherein each multistage amplifier includes a final stage amplifier (e.g., Figure 4 The final stage amplifier 470) is a series-coupled driver stage amplifier (e.g., Figure 4 The driver stage amplifier 410). For example, both the driver stage amplifier and the power stage amplifier can be implemented using field-effect transistors (FETs). In a particular embodiment, the driver stage amplifier FET and the final stage amplifier FET have significantly different power densities and can be mounted on different semiconductor dies (e.g., Figure 6 Different semiconductor technologies are used to implement this in the dies 610 and 670. For example, the driver-stage FET can be a silicon-based FET, and the final-stage FET can be a III-V semiconductor-based FET.

[0057] Each amplification stage of each multistage amplifier receives one or more DC bias voltages from one or more external voltage sources. According to a particular embodiment, even if the driver stage amplifier FET and the final stage amplifier FET have significantly different power densities and may be implemented using different semiconductor technologies, the driver stage amplifier FET and the final stage amplifier FET of each transceiver 132 will receive the same output (e.g., drain) DC bias voltage (“output / drain bias voltage” herein) Figure 1As shown, additional DC bias voltages and other voltages can also be supplied to transceivers 132 in transceiver array 130. These additional DC bias voltages and other voltages include, for example, one or more input (e.g., gate) DC bias voltages (“input / gate bias voltages” herein) for the driver stage amplifier FET and the final stage amplifier FET of each transmitter. To avoid Figure 1 The mess is not shown, as are the additional DC voltage sources and bias / power lines.

[0058] Figure 2 According to the embodiments, it is suitable for use in large-scale MIMO transceiver arrays (e.g., Figure 1 The transceiver 200 used in the transceiver array 130) (e.g., Figure 1 A simplified block diagram of transceiver 232. Transceiver 232 includes transmitter 240, receiver 260, and TX / RX switch 270. Transmitter 240 and receiver 260 are each coupled to baseband and IF subsystem 210 (e.g., ...). Figure 1 System 110) and antenna 252 (e.g., Figure 1 The baseband and IF subsystem 210 includes a transmit (TX) signal processor 212 and a receive (RX) signal processor 214, respectively coupled to the input 246 of the transmitter 240 and the output 266 of the receiver 260.

[0059] Transceiver system 200 is a half-duplex transceiver configured to support TDD communication. Therefore, at any given time, only one of the transmitter 240 or receiver 260 is coupled to antenna 252 via TX / RX switch 270. More specifically, (e.g., by...) Figure 3 The switch controller 350 controls the state of the TX / RX switch 270 to switch between a transmission state in which the switch 270 couples the RF TX signal generated by the transmitter 240 to the antenna 252, or a reception state in which the switch 270 couples the RF RX signal received by the antenna 252 to the receiver 260.

[0060] The transmission signal processor 212 is configured to generate a transmission signal and provide the transmission signal to the transmitter 240 via input 246. For example, the transmitter 240 may include a preamplifier 242 and a power amplifier 244. The preamplifier 242 appropriately amplifies the transmission signal provided by the transmission signal processor 212. The power amplifier 244 further amplifies the transmission signal and provides the amplified TX RF signal to the TX / RX switch 270. As will be described in more detail later, the power amplifier 244 includes a multi-stage amplifier having a driver stage amplifier FET and a final stage amplifier FET that receive the same output / drain bias voltage. For example, this can be achieved by a DC drain bias voltage source 280 (e.g., connected to the power amplifier 244 via a DC bias input 282, and more specifically, connected to the outputs of the driver stage amplifier FET and the final stage amplifier FET within the power amplifier 244). Figure 1 A DC drain bias voltage source (180) supplies the output / drain bias voltage. When, for example... Figure 1 When a transceiver array such as transceiver array 130 includes transceiver 232, DC bias input 282 can be connected, for example, to the interconnect bias power line 182 network previously discussed and coupled to transceiver array substrate 134.

[0061] Receiver 260 may include, for example, a receive amplifier 262 (e.g., a low-noise amplifier). Receiver amplifier 262 is configured to amplify the relatively low-power RF RX signal received from TX / RX switch 270 and provide the amplified received signal to receive signal processor 214 via output 266. Receiver signal processor 214 is configured to use or process the received signal.

[0062] During each transmission time interval, the TX / RX switch 270 is controlled to be in the first or "transmission" state, such as... Figure 2 As depicted, a transmission signal path is closed between transmitter node 272 and antenna node 276, and a reception signal path is open between antenna node 276 and receiver node 274. Conversely, during each reception time interval, TX / RX switch 270 is controlled to be in a second or "receive" state, wherein a reception signal path is closed between antenna node 276 and receiver node 274, and a transmission signal path is open between transmitter node 272 and antenna node 276.

[0063] The following will be combined Figure 3In more detail, the RF transceiver 232 can be physically implemented using a variety of active and passive ICs, modules, and electrical components. For example, various components of the RF transceiver 232 can be implemented in standalone modules or packaged electrical devices that can be coupled to a transceiver substrate (e.g., ...) along with multiple other transceiver modules or devices. Figure 1 The transceiver substrate 134). As used herein, the term "transceiver device" refers to all components of a transceiver (e.g., Figure 1 , 2 A transceiver device is a group of active and / or passive electrical devices (e.g., ICs, modules, and electrical components) physically housed within a single housing (e.g., a device package) or physically coupled to a common substrate (e.g., a PCB). The “transceiver device” also includes multiple conductive terminals for electrically connecting the group of devices to other parts forming a power system (e.g., [other components]). Figure 1 , 2 The external circuitry system includes the baseband and IF subsystems 110, 210, bias voltage sources 180, 280, and antennas 152, 252. For example, in various embodiments, the transceiver device can be in the form of a PCB-based module, surface mount module, chip carrier device, ball, pin, or grid array device, flat package (e.g., quad or bidirectional flat package), chip-scale package, system-in-package (SiP) device, or other types of integrated circuit packages. Although specific types of transceiver devices are described below, it should be understood that embodiments of the subject matter of this invention can also be included in other types of transceiver devices.

[0064] For example, Figure 3 This is an embodiment based on the example. Figure 2 The transceiver device 300 of the RF transceiver 232 (e.g., Figure 1 A top view of an example of transceiver 132. According to the illustrated example embodiment, device 300 is implemented as a PCB-based module, but device 300 may also be packaged in other types of packages or modules (e.g., quad flat no-lead (QFN) devices or another type of device). In any case, device 300 includes a substrate 310, which may include, for example, a plastic substrate, a single-layer or multi-layer PCB, conductive flanges, and / or another rigid structure.

[0065] The device 300 also includes a plurality of components coupled to the substrate 310, the plurality of components including (e.g., Figure 2 The preamplifier 242 is a transmission preamplifier module 342 (e.g., the preamplifier 242 is a transmission preamplifier module 342). Figure 2 The transmission amplifier module 344 (e.g., the embodiment of transmission amplifier 244) Figure 2The receiver amplifier module 362, which embodies the receiver amplifier 262, and (for example, Figure 2 The TX / RX switch module or duplexer 370 embodies the TX / RX switch 270. Furthermore, the device 300 includes a plurality of connectors (or terminals or leads) configured to provide electrical connection between an external power system and the transceiver assembly housed within the device 300. For example, the connectors (or leads or terminals) may include one or more grounding connectors 320, transmission signal input connectors 346 (e.g., ... Figure 2 Transmitter input 246), receive signal output connector 366 (e.g., Figure 2 Receiver output 266), antenna / load connector 376 (e.g., Figure 2 Antenna terminal 254), first DC bias voltage connector 380 (e.g., Figure 2 The various modules 342, 344, 362, 370 and connectors 320, 346, 366, 376, 380, 390 are electrically connected together via multiple conductive electrical features (e.g., including conductive traces 382, ​​392 and other conductive features). In other embodiments, other conductive structures may be used to electrically connect the various modules in modules 342, 344, 362, 370 and connectors 320, 346, 366, 376, 380, 390 together. In various embodiments, device 300 may be housed within a cavity or overmolded (e.g., encapsulated), but device 300 may also be considered complete without such housing.

[0066] When the device 300 is incorporated into the transceiver array (e.g., Figure 1 Following the transceiver array 130, and during operation of the transceiver system, bias and ground reference voltages can be provided to device 300 through bias and ground terminals 320, 380, and 390. As mentioned above, and in conjunction with... Figure 4-6 In more detail, for example, amplifier module 344 includes at least one multistage amplifier having a driver-stage amplifier FET and a final-stage amplifier FET, the driver-stage amplifier FET and the final-stage amplifier FET being configured to receive the same output / drain DC bias voltage via bias voltage connector 380 and conductive trace 382, ​​the bias voltage connector 380 and conductive trace 382 being coupled to an external DC drain bias voltage source (e.g., Figure 1 , 2The DC drain bias voltage sources 180 and 280. The transmit preamplifier module 342 and / or receive amplifier module 362 can receive one or more other bias and / or operating DC voltages via voltage connector 390 and conductive trace 392, and can be coupled to another external DC voltage source (not shown).

[0067] The TX / RX duplexer 370 can operate in either transmit or receive mode at any given time. When the TX / RX duplexer 370 operates in transmit mode, the transmit signal received through the transmit signal input connector 346 and amplified by the preamplifier and power amplifier modules 342, 344 is transmitted through the TX / RX duplexer 370 to the antenna connector 376. Conversely, when the TX / RX duplexer 370 operates in receive mode, the signal received from the antenna connector 376 is transmitted through the TX / RX duplexer 370 to the receive amplifier module 362, which amplifies the received signal and provides the amplified received signal to the receive signal output connector 366.

[0068] As discussed previously, transmission power amplifiers (e.g., Figure 2 , 3 The amplifier 244 or amplifier module 344 includes at least one multistage amplifier. Figure 4 and 5 It is shown that, according to various embodiments, it can be included respectively in a transmission amplifier or module (e.g., Figure 2 , 3 Amplifier 244 or module 344) and / or transceiver (e.g., Figure 1 , 2 A simplified block diagram of the multistage amplifier 400 and a circuit diagram of the multistage amplifier 500 within the transceivers 132 and 232.

[0069] Simply put, Figure 4 and 5Each of the multistage amplifiers 400 and 500 includes a driver stage amplifier 410 and 510 coupled in series with the final stage amplifiers 470 and 570. According to an embodiment, the driver stage amplifiers 410 and 510 and the final stage amplifiers 470 and 570 all include field-effect transistors (FETs) 440, 472, 540, and 572, but the power densities of the driver stage amplifiers 410 and 510 and the final stage amplifiers 470 and 570 are significantly different. In a particular embodiment, the driver stage amplifiers FETs 440 and 540 and the final stage amplifiers FETs 472 and 574 are implemented using different semiconductor technologies on different semiconductor dies. For example, the driver stage FET can be a silicon-based FET, and the final stage FET can be a III-V semiconductor-based FET. In alternative embodiments, the driver stage FET or the final stage FET can be implemented using technologies other than silicon or GaN, or the same semiconductor technology can be used to implement both the driver stage FET and the final stage FET, provided that the power densities of the two devices are significantly different.

[0070] According to a specific embodiment, even though the driver stage amplifier FETs and the final stage amplifier FETs 440, 472, 540, 572 have different power densities and can be implemented using different semiconductor technologies, the driver stage amplifier FETs 440, 540 and the final stage amplifier FETs 472, 572 will each be biased from DC drain voltage sources 480, 580 (e.g., Figure 1 , 2 The DC drain bias voltage sources 180, 280 receive the same output / drain DC bias voltage. For example, the DC drain bias voltage sources 480, 580 can be configured to provide an output / drain bias voltage in the range of about 20V to about 60V (e.g., about 48V output / drain bias voltage), but the output / drain bias voltage can also be lower or higher.

[0071] First refer to Figure 4 A simplified block diagram of a two-stage amplifier 400 according to an example embodiment is shown, which includes a driver stage IC die 410 and a final stage IC die 470 electrically coupled together in a cascaded arrangement between an RF signal input terminal 402 and an RF signal output terminal 404. The basic components of the two-stage amplifier 400 include a series-coupled combination of a driver stage transistor 440 in the driver stage IC die 410, an interstage impedance matching circuit 450, and a final stage transistor 472 in the final stage IC die 470.

[0072] The driver-stage IC die 410 includes an input terminal 420, an output terminal 422, an input impedance matching circuit 430, and a driver-stage transistor 440. According to an embodiment, the driver-stage IC die 410 also includes an integrated portion of an inter-stage impedance matching circuit 450 electrically coupled between the driver-stage transistor 440 and the output terminal 422 of the driver-stage IC die 410. In an embodiment, the final-stage IC die 470 includes an input terminal 490, an output terminal 492, and a final-stage transistor 472. An inductive connector 423 (e.g., a bonding wire) is electrically coupled between the output terminal 422 of the driver-stage IC die 410 and the input terminal 490 of the final-stage IC die 470.

[0073] exist Figure 4 and 5 In the illustrated embodiment, the interstage impedance matching circuit 450 includes multiple components integrally formed within the driver stage IC die 410 (referred to as the “integrated portion” of the interstage impedance matching circuit 450), and an inductive connection 423 between the driver stage die 410 and the final stage die 470. In other embodiments, all portions of the interstage impedance matching circuit 450 may be implemented separately from the driver stage IC die 410. For example, components of the interstage impedance matching circuit 450 may be implemented using a separate integrated passive device (IPD) located between the driver stage die 410 and the final stage die 470, and inductive connections (e.g., bonding wires) from the driver stage die 410 to the IPD and from the IPD to the final stage die 470. In other embodiments, the interstage impedance matching circuit 457 may include an inductive connection (e.g., bonding wires) between the driver stage IC die 410 and the final stage IC die 470, and multiple components integrally formed within the final stage IC die 470. Although only the illustrated embodiments are described in detail below, the various alternative embodiments mentioned above are intended to be included within the scope of the subject matter of this invention.

[0074] Along the forward amplification path, the RF signal input terminal 402 is electrically coupled to the input terminal 420 of the driver stage IC die 410 via a connector 403 (e.g., a bonding wire, a bonding wire array, or other electrical connector). The input terminal 420 is coupled to the input impedance matching circuit 430. The input impedance matching circuit 430 is coupled to the input 444 (e.g., the gate or control terminal) of the driver stage transistor 440. The output 446 (e.g., the drain or the first current conduction terminal) of the driver stage transistor 440 is coupled to the integrated portion of the interstage impedance matching circuit 450, and the integrated portion of the interstage impedance matching circuit 450 is coupled to the output terminal 422.

[0075] The output terminal 422 of the driver stage die 410 is electrically coupled to the input terminal 490 of the final stage IC die 470 via a connector 423 (e.g., a bonding wire array or other conductive connector). Connector 423 represents a non-integrated portion of the interstage matching circuit between the output (e.g., drain terminal) of the driver stage transistor 440 and the input (e.g., gate terminal) of the final stage transistor 472. Continuing along the forward amplification path, the input terminal 490 of the final stage IC die 470 is coupled to the input 474 (e.g., gate or control terminal) of the final stage transistor 472, and the output 476 (e.g., drain or first current conduction terminal) of the final stage transistor 472 is coupled to the output terminal 492. The output terminal 492 is electrically coupled to the RF signal output terminal 404 via a connector 479 (e.g., a bonding wire array or other electrical connector).

[0076] During operation, the RF signal received through RF signal input 402 and driver stage die input 420 is transmitted through input impedance matching circuit 430, which is configured to increase the impedance of amplifier 400 to a higher impedance level (e.g., 50 ohms or another impedance level) to enhance gain flatness and power delivery across frequency bands. The resulting RF signal is then amplified by driver stage transistor 440 (i.e., driver stage transistor 440 acts as a driver amplifier, which applies a first gain to the RF signal). For example, driver stage transistor 440 can apply a gain to the RF signal in the range of about 40 dB to about 55 dB (e.g., about 50 dB in some embodiments), but the gain applied by driver stage transistor 440 can also be lower or higher.

[0077] The amplified RF signal generated at the output 446 of the driver stage transistor 440 is then transmitted through the integrated portion of the interstage impedance matching circuit 450. The resulting RF signal generated at the output terminal 422 is then transmitted to the input terminal 490 of the final stage IC die 470 via connector 423. The integrated portion of the interstage impedance matching circuit 450 and the connector 423 between dies 410 and 470 are configured to match the output impedance (or drain impedance) of the driver stage transistor 440 with the input impedance of the final stage transistor 472 to enhance gain flatness and power delivery across frequency bands. In some embodiments, connector 423 is a non-integrated series inductor component in the interstage matching circuit between the output of the driver stage transistor 440 and the input 474 of the final stage transistor 472.

[0078] The preamplified RF signal received at input 490 of the final-stage IC die 470 is amplified by the final-stage transistor 472 (i.e., the final-stage transistor 472 acts as the final amplifier, which applies a second gain to the RF signal). For example, the final-stage transistor 472 can apply a gain in the range of about 40 dB to about 45 dB (e.g., about 44 dB in some embodiments) to the RF signal, thereby producing a total gain through the device 400 in the range of about 50 dB to about 40 dB (e.g., about 65 dB in some embodiments), but the gain applied by the final-stage transistor 472 and / or the total device gain can also be lower or higher. The amplified RF signal generated at the output 476 of the final-stage transistor 472 is then transmitted to the RF signal output 404 via output 492 and connector 479.

[0079] According to a specific embodiment, power transistor 440 includes a silicon laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor having a power density in the range of about 1.0 W / mm to about 3.0 W / mm (e.g., about 2.0 W / mm). Additionally, according to a specific embodiment, power transistor 472 includes a GaN-based high electron mobility transistor (HEMT) having a power density in the range of about 5.0 W / mm to about 15.0 W / mm (e.g., about 10.0 W / mm) and an input impedance in the range of about 1.0 ohm to about 5.0 ohms (e.g., about 1.4 ohms), but the input impedance can also be smaller or larger. Although power transistor 440 or power transistor 472 can be implemented using semiconductor technologies other than silicon LDMOS or GaN HEMT (including using the same semiconductor technologies), an important aspect of the invention is that the power densities of the driver stage transistor 440 and the final stage transistor 472 are significantly different. More specifically, the power density of the driver stage transistor 440 is significantly lower than that of the final stage transistor 472 (or conversely, the power density of the final stage transistor 472 is significantly higher than that of the driver stage transistor 440). According to embodiments, the power density ratio of the driver stage transistor 440 to the final stage transistor 472 is in the range of 1:2 to 1:8 (e.g., 1:5). For example, when the driver stage transistor 440 has a power density of 2.0 W / mm and the final stage transistor has a power density of 10.0 W / mm, the power density ratio will be 1:5.

[0080] According to another specific embodiment, both power transistors 440 and 472 are configured to have output impedances and breakdown voltages suitable for supporting operation using the same drain bias voltage. For example, driver stage transistor 440 may have a real part of its output impedance in the range of about 50 ohms to about 100 ohms (e.g., about 75 ohms), and final stage transistor 472 may have a real part of its output impedance in the range of about 1.0 ohms to about 5.0 ohms (e.g., about 1.4 ohms). As will be discussed in more detail later, interstage impedance matching circuitry 450 (including connector 423) is configured to provide impedance transformation between the output impedance of driver stage transistor 440 and the input impedance of final stage transistor 472.

[0081] The biasing of the driver-level IC die and the final-level IC dies 410, 470 will now be described. According to an embodiment, the driver-level IC die 410 further includes an integrated bias circuit 460 (or “driver-level drain bias circuit”) configured to deliver a bias voltage to the output 446 (e.g., the drain terminal) of the driver-level transistor 440. More specifically, the driver-level IC die 410 includes a bias circuit input 458 (referred to simply as the “bias input”) and a bias voltage control circuit 460 electrically coupled between the bias input 458 and the output 446 of the driver-level transistor 440.

[0082] Similarly, the final-stage IC die 470 further includes an integrated bias circuit 462 (or "final-stage drain bias circuit") configured to deliver a bias voltage to the output 476 (e.g., the drain terminal) of the final-stage transistor 472. More specifically, the final-stage IC die 470 includes a bias input 478 and an integrated bias circuit 462 electrically coupled between the bias input 478 and the output 476 of the final-stage transistor 472.

[0083] In the embodiment, integrated bias circuits 460, 462 (and more specifically, bias inputs 458, 478) are all electrically connected to a DC drain bias voltage source 480 (e.g., Figure 1 , 2 DC drain bias voltage sources 180, 280) are used to receive the same output / drain DC bias voltage. In alternative embodiments, such as those provided by... Figure 4 As indicated by the dashed line, the output / drain DC bias voltage for the final stage transistor 472 can be supplied through output terminal 404, connector 479 and output terminal 492.

[0084] In addition to the drain bias circuitry and drain bias voltage sources (e.g., circuits 460, 462 and voltage source 480), amplifier 400 may also include one or more gate bias circuits 434, 465, which (e.g., via bias inputs 438, 494, respectively) are coupled to one or more DC gate bias voltage sources 439, 482. For example, DC gate bias voltage source 439 may provide a DC bias voltage to input 444 (e.g., the gate) of driver stage transistor 440 via input 438 and driver stage gate bias circuit 434. For example, the DC gate bias voltage for driver stage Vg1 may have a positive value of up to about 6.2V or greater (e.g., about 1.5V). DC gate bias voltage source 482 may provide a DC bias voltage to input 474 (e.g., the gate) of final stage transistor 472 via input 494 and final stage gate bias circuit 465. When the final stage transistor 472 is a depletion-mode, normally-on III-V device, the gate bias voltage Vg2 used for receiving and transmitting in the final stage is a negative DC bias voltage, which acts to pinch off the final stage transistor 472. For example, the DC gate bias voltage Vg2 used in the final stage can have a negative value as low as about -5.0V or less (e.g., about -3.5V). Conversely, when the final stage transistor 472 is an enhancement-mode, normally-on device, the gate bias voltage received and transmitted is a positive DC bias voltage.

[0085] Now we will combine Figure 5 A circuit diagram describing a more specific embodiment of amplifier 400 is provided in detail. More specifically, Figure 5 This is a circuit diagram of an embodiment of a two-stage cascaded amplifier 500 having a silicon-based driver stage and a GaN-based final stage, according to an example embodiment.

[0086] Amplifier 500 includes a silicon driver stage IC die 510 (e.g., Figure 4 IC die 410) and GaN final stage IC die 570 (e.g., Figure 4 IC die 470), which has an RF signal input terminal 502 (e.g., Figure 4 The input terminal 402) and the RF signal output terminal 504 (e.g., Figure 4The output terminals 404 are electrically coupled together in a cascaded arrangement. As used herein, the terms "integrated circuit die" and "IC die" mean a single, distinct die in which one or more circuit components (e.g., transistors, passive devices, etc.) are integrated and / or directly physically connected. According to embodiments, multiple circuits, each comprising passive and / or active electrical components, are integrated within a silicon driver-stage IC die 510 and a GaN final-stage IC die 570. It should be noted that although die 510 is described as a "silicon" die and die 570 as a "GaN" die, in other embodiments, different semiconductor materials (e.g., other Group III-V semiconductor materials, such as gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), and indium antimonide (InSb) for GaN dies) may be used to form one or both dies. Similarly, different semiconductor materials may be used to form transistors 540 and 572 within dies 510 and 570.

[0087] The silicon driver-level IC die 510 includes multiple circuits integrated within a silicon IC die (e.g., a high-resistivity silicon die). In an embodiment, the integrated circuit system of die 510 includes an input terminal 520 (e.g., ...) in the embodiment. Figure 4 Input terminal 420), output terminal 522 (e.g., Figure 4 Output terminal 422), first DC blocking / AC decoupling capacitor 524, second DC blocking / AC decoupling capacitor 526, input impedance matching circuit 530 (e.g., Figure 4 Circuit 430), power transistor 540 (e.g., Figure 4 Transistor 440), interstage impedance matching circuit 550 (e.g., Figure 4 Circuit 450), gate bias circuit 534 (e.g., Figure 4 Circuit 434) and drain bias circuit 560 (e.g., Figure 4 The integrated portion of the circuit 460. As previously mentioned, the integrated portion of the interstage impedance matching circuit 550 may alternatively not be integrated in die 510, but may be implemented using a different circuit system than die 510 (e.g., the IPD between die 510 and die 570, or a circuit system integrated with die 570).

[0088] Power transistor 540 is the primary amplification component of silicon driver-level IC die 510. In an embodiment, power transistor 540 includes a FET having a gate terminal 544 (control terminal), a drain terminal 546 (first current conduction terminal), and a source terminal 548 (second current conduction terminal). The source terminal 548 is electrically coupled to a ground node 528 (e.g., the source terminal 548 is electrically coupled to a conductive layer on the bottom surface of the silicon IC die 510 through one or more through-substrate vias (TSVs). According to a specific embodiment, power transistor 540 includes a silicon LDMOS transistor having a power density in the range of about 1.0 W / mm to about 3.0 W / mm (e.g., about 2.0 W / mm). Additionally, power transistor 540 has the real part of its output impedance in the range of about 50 ohms to about 100 ohms (e.g., about 75 ohms), but the input impedance may also be smaller or larger.

[0089] The RF signal input terminal 502 is electrically coupled to the input terminal 520 of the silicon driver stage IC die 510 via a connector 503 (e.g., multiple bonding wires or another electrical connector). A first DC blocking / AC decoupling capacitor 524 has a first terminal electrically coupled to the input terminal 520 and a second terminal electrically coupled to the input impedance matching circuit 530. The first DC blocking / AC decoupling capacitor 524 can provide some impedance transformation, but its primary function is to block the driver stage gate bias voltage Vg1 from the input terminal 520.

[0090] The input impedance matching circuit 530 is electrically coupled between the second terminal of the DC blocking / AC decoupling capacitor 524 and the gate terminal 544 of the driver stage power transistor 540. The input impedance matching circuit 530 includes a first DC blocking / AC decoupling capacitor 524, a second capacitor 531, a first inductor 532, a first resistor 533, and a shunt circuit comprising a series combination of a second resistor 535, a second inductor 536, and a third capacitor 537. The second capacitor 531 includes a first terminal coupled to the second terminal of the DC blocking / AC decoupling capacitor 524 and a second terminal coupled to a ground node 528. The first inductor 532 includes a first terminal coupled to the second terminal of the DC blocking / AC decoupling capacitor 524 (and coupled to the first terminal of the capacitor 531) and a second terminal coupled to the gate terminal 544 of the power transistor 540 via the first resistor 533. The shunt circuit includes a second resistor 535, a second inductor 536, and a third capacitor 537 (e.g., a DC blocking capacitor) electrically coupled between the gate terminal 544 of the power transistor 540 and the ground node 528. In alternative embodiments, the second resistor 535 may be omitted, or the order of the second resistor 535, the second inductor 536, and the third capacitor 537 may be different. Figure 5 The order described in the text is different.

[0091] The input impedance matching circuit 530 is used to increase the impedance of the amplifier 500, as previously mentioned, and also to apply amplitude and phase distortion to the RF signal that is opposite to the amplitude and phase distortion applied by the GaN-based final-stage transistor 572 of the GaN final-stage IC die 570. The input impedance matching circuit 530 may include a low-pass circuit, a high-pass circuit, a band-pass circuit, or a combination thereof. Generally, the inductor, capacitor, and resistor values ​​are adjusted proportionally according to the center frequency of the operating amplifier 500. Additionally, although in Figure 5 The input impedance matching circuit 530 shown has a specific configuration, but in other embodiments, the input impedance matching circuit 530 may be configured differently while still performing substantially the same function.

[0092] In this embodiment, a gate bias voltage Vg1 for the power transistor 540 is provided to the gate terminal 544 of the power transistor 540 via a shunt circuit of the input impedance matching circuit 530. More specifically, the gate bias voltage can be provided via an input terminal 538, which is electrically coupled to a node of the shunt circuit (e.g., the node between the second inductor 536 and the third capacitor 537). For example, the gate bias voltage Vg1 can be provided by an external voltage source 539, and the gate bias voltage Vg1 can have a positive value of up to about 6.2V or greater, but it can also be lower or higher. More typically, the gate bias voltage Vg1 will be less than about 2.0V (e.g., about 1.5V).

[0093] Interstage impedance matching circuit 550 is electrically coupled between the drain terminal 546 of power transistor 540 and the gate terminal 574 of transistor 572. The integrated portion of interstage impedance matching circuit 550 includes a first inductor 551, a shunt circuit, and a second DC blocking / AC decoupling capacitor 526. The first inductor 551 includes a first terminal coupled to the drain terminal 546 of power transistor 540 and a second terminal coupled to the first terminal of the second DC blocking / AC decoupling capacitor 526. The shunt circuit includes a series combination of a second inductor 552 and a first capacitor 553 (e.g., a DC blocking capacitor) electrically coupled between the second terminal of the first inductor 551 (and the first terminal of the second DC blocking / AC decoupling capacitor 526) and a ground node 528.

[0094] An interstage impedance matching circuit 550, coupled to connector 523, is used to match the impedance of the drain terminal 546 of power transistor 540 to the gate terminal 574 of transistor 572 for appropriate interband power delivery. Furthermore, the interstage impedance matching circuit 550 is used to shape the input RF waveform into the GaN final-stage IC die 570. According to an embodiment, the interstage impedance matching circuit 550 (including connector 523) is configured to perform impedance transformation between the real part of the output impedance of the driver stage transistor 540 and the input impedance of the final-stage transistor 572 within a range of about 50 ohms to about 100 ohms (e.g., at about 73.6 ohms when the output impedance of transistor 540 is 75 ohms and the input impedance of transistor 572 is 1.4 ohms). The interstage impedance matching circuit 550 (including connector 523) can be configured as a low-pass circuit, a high-pass circuit, a band-pass circuit, or a combination thereof. In various embodiments:

[0095] - The first inductor 551 may have an inductance value in the range of about 3nH to about 5nH (e.g., for a center operating frequency f0 of about 3.5 GHz, the inductance value is about 4nH);

[0096] - The second inductor 552 may have an inductance value in the range of about 1.3nH to about 2.3nH (e.g., for a center operating frequency f0 of about 3.5 GHz, the inductance value is about 1.86nH);

[0097] - The first capacitor 553 may have a capacitance value in the range of about 15 pF to about 25 pF (e.g., for a center operating frequency f0 of about 3.5 GHz, the capacitance value is about 20 pF); and

[0098] - The DC blocking / AC decoupling capacitor 526 can have a capacitance value in the range of about 3.4pF to about 4.4pF (e.g., for a center operating frequency f0 of about 3.5 GHz, the capacitance value is about 3.9pF).

[0099] In various embodiments, the inductor, capacitor, and resistor values ​​can be lower or higher. Generally, the inductor, capacitor, and resistor values ​​are adjusted proportionally to the center frequency of the operating amplifier 500. Additionally, although the interstage impedance matching circuit 550... Figure 5 The diagram shows a specific configuration, but in other embodiments, the interstage impedance matching circuit 550 can be configured differently while still performing essentially the same function.

[0100] The second DC blocking / AC decoupling capacitor 526 can provide some impedance transformation, but its main function is to block the drain bias voltage Vd1 of the driver stage power transistor 540 from the gate bias voltage Vg2 of the final stage power transistor 572 of the GaN final stage IC die 570.

[0101] In this embodiment, the drain bias voltage Vd1 of the power transistor 540 is provided to the drain terminal 546 of the power transistor 540 via a shunt circuit of the interstage impedance matching circuit 550. In other words, the shunt circuit acts as the drain bias circuit 560 of the drive stage (e.g., Figure 4 (Circuit 460). More specifically, a drain bias voltage can be provided through input 558, which is electrically coupled to a node of the shunt circuit (e.g., the node between the second inductor 552 and the capacitor 553). For example, the drain bias voltage can be provided by an external voltage source 580, and the drain bias voltage can have a value in the range of about 30V to about 60V (e.g., about 48V), but the drain bias voltage can also be lower or higher.

[0102] Silicon driver-level IC die 510 (e.g., Figure 4 The silicon IC die 410 is electrically coupled to the GaN final-stage IC die 570 (e.g., via a connector 523 between the output terminal 522 of the silicon IC die 510 and the input terminal 590 of the GaN IC die 570) through a connector 523. Figure 4 (GaNIC die 470). For example, connector 523 may include inductive connectors, such as bonded wire arrays (e.g., Figure 4 The bonding line array 423 may be included, or it may include another type of connector (e.g., microstrip lines, printed coils, parallel-coupled resistor / capacitor circuits, etc.). Connector 523 provides an embossed portion of the interstage impedance matching circuit 550. According to an embodiment, connector 523 has an inductance value in the range of about 0.2nH to about 0.3nH (e.g., about 0.25nH), but the inductance value may also be smaller or larger.

[0103] The GaN final-stage IC die 570 includes multiple circuits integrated within the GaN IC die, which differs from a silicon IC die. In an embodiment, the integrated circuit system of die 570 includes an input terminal 590 (e.g., ...) in the embodiment. Figure 4 Input terminal 490), output terminal 592 (e.g., Figure 4 Output terminal 492), final stage gate bias circuit 565, power transistor 572 (e.g., Figure 4 The transistor 472) and the final stage drain bias circuit 562.

[0104] Power transistor 572 is the main amplification component of GaN final-stage IC die 570. In an embodiment, power transistor 572 includes a FET having a gate terminal 574 (control terminal), a drain terminal 576 (first current conduction terminal), and a source terminal 578 (second current conduction terminal). Input terminal 590 is coupled to the gate terminal 574 of GaN transistor 572. Drain terminal 576 of GaN transistor 572 is coupled to output terminal 592, and source terminal 578 of GaN transistor 572 is electrically coupled to ground node 596 (e.g., source terminal 578 is electrically coupled to a conductive layer on the bottom surface of GaN IC die 570 via one or more TSVs). Output terminal 592 is electrically coupled to the RF signal output terminal 504 of amplifier 500 via connector 579 (e.g., bonding wire array or other electrical connector).

[0105] According to a specific embodiment, the power transistor 572 includes a GaN-based high electron mobility transistor (HEMT) having a power density in the range of about 5.0 W / mm to about 15.0 W / mm (e.g., about 10.0 W / mm). Additionally, the power transistor 572 has an input impedance in the range of about 1.0 ohm to about 5.0 ohms (e.g., about 1.4 ohms), but the input impedance may also be smaller or larger.

[0106] According to an embodiment, via the final-stage gate bias circuit 565 (e.g., Figure 4 Circuit 465 provides the gate bias voltage Vg2 for the power transistor 572 of the GaN final-stage IC die 570. In this embodiment, the final-stage gate bias circuit 565 includes an input terminal 594, a resistor 566, an inductor 567, and a capacitor 568. In an alternative embodiment, resistor 566 may be omitted, or the order of resistor 566, inductor 567, and capacitor 568 may be different. Figure 5 The order in which they are depicted is different.

[0107] During operation, an external voltage source 582 can provide a DC voltage through input 594, which is electrically coupled to a node of bias circuit 565 (e.g., the node between inductor 567 and capacitor 568). The final-stage gate bias voltage circuit 565 can convert the received voltage into a DC gate bias voltage Vg2 for the GaN transistor 572. For example, the DC gate bias voltage for the final stage Vg2 can have a negative value as low as approximately -5.0V or less (e.g., approximately -3.5V), but the gate bias voltage can also be lower or higher and / or positive.

[0108] In an embodiment, through the final stage drain bias circuit 562 (e.g., Figure 4Circuit 462 provides a drain bias voltage Vd2 for power transistor 572 to the drain terminal 576 of power transistor 572. The final-stage drain bias circuit 562 includes an input terminal 594 and a series combination of an inductor 563 and a capacitor 564 (e.g., a DC blocking capacitor) electrically coupled between the drain terminal 576 of the final-stage transistor 572 and a ground node 596. More specifically, the drain bias voltage Vg2 can be provided through an input terminal 578, which is electrically coupled to a node of the bias circuit 562 (e.g., the node between inductor 563 and capacitor 564). In alternative embodiments, and as... Figure 5 As indicated by the dashed line, the drain bias voltage Vg2 for the GaN power transistor 572 can be provided to the drain terminal 576 of the power transistor 572 via the RF output terminal 592. As previously discussed, and according to the embodiment, the final-stage drain bias voltage can be provided by the same external voltage source 580 used to provide the driver stage drain bias voltage. Therefore, the driver stage drain bias voltage and the final-stage drain bias voltage can be equal (e.g., Vg1 = Vg2 = 48V or some other value).

[0109] Figure 4 and Figure 5 The amplifiers 400 and 500 depicted each include a single amplification path. Other amplifier embodiments may include two or more amplification paths. For example, in some embodiments, multiple amplification paths may be electrically coupled together as part of a multipath amplifier system. For example, combined with Figure 4 and Figure 5 The described amplifier embodiments, in many examples, can be implemented in a Doherty power amplifier or in another type of multipath amplifier. For example, in combination with Figure 4 and Figure 5 A first instance of the described amplifier embodiment may be incorporated into the main amplification path of a Doherty power amplifier, and one or more additional instances of the amplifier embodiment may be incorporated into one or more peak amplification paths.

[0110] For example, Figure 6This is a simplified schematic of a Doherty power amplifier 600, which may include one or more instances of RF amplifiers 400 and 500. The Doherty amplifier 600 includes an input node 602, an output node 604, a power divider 606 (or splitter), a main amplifier path 620 with two main amplifier stages 622 (including a driver stage amplifier 630 and a final stage amplifier 660), a peak amplifier path 621 with two peak amplifier stages 623 (including a driver stage amplifier 631 and a final stage amplifier 661), and a combination node 686. A load 690 may be coupled to the combination node 686 (e.g., via an impedance transformer, not shown) to receive amplified RF signals from the amplifier 600.

[0111] Power divider 606 is configured to divide the power of the input RF signal received at input node 602 into a main portion and a peak portion of the input signal. The main input signal is provided to the main amplifier path 620 at power divider output 608, and the peak input signal is provided to the peak amplifier path 621 at power divider output 609. During full-power mode operation, when both the main amplifier and the peak amplifiers 620, 621 are supplying current to the load 690, power divider 606 distributes the input signal power between amplifier paths 620, 621. For example, power divider 606 may divide the power equally, such that approximately half of the input signal power is provided to each path 620, 621 (e.g., for a symmetrical Doherty amplifier configuration). Alternatively, power divider 606 may distribute the power unequally (e.g., for an asymmetrical Doherty amplifier configuration). Basically, the power divider 606 distributes the input RF signal supplied at the input node 602 and amplifies the distributed signal along the main amplifier path and the peak amplifier paths 620 and 621, respectively. The amplified signals are then combined in phase at the combination node 686.

[0112] Amplifier 600 is designed to maintain phase coherence between the main amplifier path and peak amplifier paths 620, 621 in the relevant frequency band, ensuring that the amplified main signal and peak signal arrive in phase at combination node 686, thereby ensuring proper operation of the Doherty amplifier. More specifically, Doherty amplifier 600 has a “non-inverting” load network configuration. In the non-inverting configuration, the input circuitry is configured such that the input signal supplied to peak amplifier path 621 is delayed by 90 degrees relative to the input signal supplied to main amplifier path 620 at the center frequency f0 of amplifier 600's operation. To ensure that the main input RF signal and peak input RF signal are supplied to the main amplifier path and peak amplifier paths 620, 621 with a phase difference of approximately 90 degrees, which is the basis for proper Doherty amplifier operation, phase delay element 682 applies a phase delay of approximately 90 degrees to the peak input signal (i.e., the signal generated at power divider output 609). For example, phase delay element 682 may comprise a quarter-wavelength transmission line, or another suitable type of delay element with an electrical length of approximately 90 degrees.

[0113] A 90-degree phase delay difference at the inputs of the main amplifier path and peak amplifier paths 620, 621 is used to compensate for a 90-degree phase delay in the signal between the output of the main amplifier 622 and the combination node 686. This is achieved through an additional delay element 684 between the output of the main amplifier 622 and the combination node 686. The additional delay element 684 can also be configured to perform impedance inversion, and therefore element 684 can be a component or structure referred to as "phase delay and impedance inversion".

[0114] Each of the main amplifier path 620 and the peak amplifier path 621 includes input impedance matching networks 610, 611 (input MNm and input MNp) and multi-stage power amplifiers 622, 623 (e.g., Figure 4 , 5 Examples of amplifiers 400 and 500. Input impedance matching networks 610 and 611 can be implemented between the power divider outputs 608 and 609 and the inputs of the main amplifiers and peak amplifiers 622 and 623 (e.g., the gates of the main driver stage amplifiers and peak driver stage amplifiers 630 and 632). In each case, matching networks 610 and 611 can be used to incrementally increase the circuit impedance toward the load impedance and source impedance. All or part of the input impedance matching networks 610 and 611 can be integrally formed with the main amplifiers and / or peak amplifiers 622 and 623. For example, with input impedance matching networks 430 and 530 ( Figure 4 , 5Similarly, all or part of the input impedance matching network 610 can be integrated with the IC corresponding to the main amplifier 622, and all or part of the input impedance matching network 611 can be integrated with the IC corresponding to the peak amplifier 623. Alternatively, all or part of the input impedance matching networks 610 and 611 can be implemented on the PCB or other substrate on which the IC is mounted.

[0115] Multistage power amplifiers 622, 623 (e.g., Figure 4 , 5 Two instances of amplifiers 400 and 500 are configured to amplify RF signals conducted through the main amplifier path and peak amplifier paths 620 and 621. According to various embodiments, the main driver stage amplifier and the peak driver stage amplifiers 630 and 632 may each use, for example, field-effect transistors (e.g., MOSFETs). Figure 4 , 5 The two examples of FET440 and 540 are used for implementation, and the main final stage amplifier and the peak final stage amplifier 660 and 661 can each use another field-effect transistor (e.g., FET440 and FET540). Figure 4 , 5 This is implemented using two examples of FETs 472 and 572. As discussed in detail above, the outputs of the FETs corresponding to each driver stage amplifier 630, 631 and each final stage amplifier 660, 661 are configured to operate using the same output bias voltage (e.g., drain bias voltage). This can be achieved, for example, by a single DC drain bias voltage source 680 (e.g., Figure 1 , 2 The DC drain bias voltage sources 180, 280, 480, and 580 provide the output bias voltage.

[0116] During operation of the Doherty amplifier 600, the main amplifier 622 is biased to operate in Class AB mode, and the peak amplifier 623 is biased to operate in Class C mode. At low power levels, where the power of the input signal at node 602 is lower than the turn-on threshold level of the peak amplifier 623, amplifier 600 operates in low-power (back-off) mode, where the main amplifier 622 is the only amplifier supplying current to the load 690. When the power of the input signal exceeds the threshold level of the peak amplifier 623, amplifier 600 operates in high-power mode, where both the main amplifier 622 and the peak amplifier 623 supply current to the load 690. At this time, the peak amplifier 623 provides active load modulation at the combined node 686 to allow the current of the main amplifier 622 to continue to increase linearly.

[0117] As used herein, the term “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one should not be bound by any expressed or implied theory presented in the foregoing technical field, background art, or specific embodiments.

[0118] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that numerous alternative or additional functional relationships or physical connections may exist in embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only, and therefore these terms are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0119] As used herein, a “node” means any internal or external reference point, connection point, interface, signal line, conductive element, etc., where a given signal, logic level, voltage, data mode, current, or quantity exists. Furthermore, two or more nodes can be implemented using a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0120] The foregoing description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly connected to) another element, and not necessarily mechanically engaged. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly connected to) another element electrically or otherwise, and not necessarily mechanically engaged. Therefore, although the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, means, features, or components may be present in embodiments of the depicted subject matter.

[0121] While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A multi-stage amplifier, characterized in that, include: A driver-level transistor having a first gate terminal, a first drain terminal and a first source terminal, wherein the driver-level transistor has a first power density, the first gate terminal is configured to receive an input RF signal, and the first source terminal is electrically coupled to a ground node. A first drain bias circuit is coupled to the first drain terminal of the driver stage transistor and configured to provide a first drain bias voltage from a first bias input terminal to the first drain terminal, wherein the driver stage transistor and the first drain bias circuit are integrally formed in a first semiconductor die. A final-stage transistor having a second gate terminal, a second drain terminal, and a second source terminal, wherein the final-stage transistor is integrally formed in a second semiconductor die, the second source terminal is electrically coupled to a ground node, and wherein the minimum ratio of the first power density of the driving stage transistor to the second power density of the final-stage transistor is 1:

2. A second drain bias circuit, coupled to the second drain terminal of the final stage transistor and configured to provide a second drain bias voltage from a second bias input terminal to the second drain terminal, wherein the second drain bias voltage is equal to the first drain bias voltage, and wherein the second drain bias circuit is integrally formed in the second semiconductor die; and An interstage impedance matching circuit is coupled between the first drain terminal and the second gate terminal.

2. The amplifier according to claim 1, characterized in that, The ratio of the first power density of the driving stage transistor to the second power density of the final stage transistor is in the range of 1:2 to 1:

8.

3. The amplifier according to claim 1, characterized in that: The driving stage transistor is a silicon-based semiconductor field-effect transistor; and The final stage transistor is a III-V group semiconductor field-effect transistor.

4. The amplifier according to claim 3, characterized in that: The driving stage transistor is a laterally diffused metal-oxide-semiconductor field-effect transistor, and the first power density is in the range of about 1.0 W / mm to about 3.0 W / mm; and The final stage transistor is a gallium nitride-based high electron mobility transistor, and the second power density is in the range of about 5.0 W / mm to about 15.0 W / mm.

5. The amplifier according to claim 1, characterized in that, The first drain bias voltage and the second drain bias voltage are in the range of 30 volts to 60 volts.

6. The amplifier according to claim 1, characterized in that: The interstage impedance matching circuit includes a connector between the first semiconductor die and the second semiconductor die.

7. The amplifier according to claim 6, characterized in that, In addition, including: A final-stage gate bias circuit, wherein the final-stage gate bias circuit is coupled to the second gate terminal and is integrally formed in the second semiconductor die; as well as A decoupling capacitor is coupled between the first drain bias circuit and the final gate bias circuit.

8. A Doherty power amplifier, characterized in that, include: A first amplification path on a first semiconductor die, the first amplification path including A first driving stage transistor, having a first gate terminal and a first drain terminal, wherein the first driving stage transistor is characterized by having a first power density. A first drain bias circuit is coupled to the first drain terminal of the first driver stage transistor and configured to provide a first drain bias voltage to the first drain terminal. A first terminal transistor having a second gate terminal and a second drain terminal, wherein the first terminal transistor is characterized by having a second power density that is greater than the first power density. A second drain bias circuit is coupled to the second drain terminal of the first final stage transistor and is configured to provide a second drain bias voltage to the second drain terminal. as well as A second amplification path on a second semiconductor die, the second amplification path including The second driving stage transistor has a third gate terminal and a third drain terminal, wherein the third driving stage transistor is characterized by having the first power density. A third drain bias circuit is coupled to the third drain terminal of the second driver stage transistor and configured to provide a third drain bias voltage from the third drain bias input terminal to the third drain terminal. The second final-stage transistor has a fourth gate terminal and a fourth drain terminal, wherein the second final-stage transistor has the second power density, and A fourth drain bias circuit, coupled to the fourth drain terminal of the second final-stage transistor, is configured to provide a fourth drain bias voltage from the fourth drain bias input terminal to the fourth drain terminal. The second driving stage transistor, the third drain bias circuit, the second final stage transistor, and the fourth drain bias circuit together form a second multistage amplifier including the features of the multistage amplifier according to claims 1 to 7, and The first drain bias voltage, the second drain bias voltage, the third drain bias voltage, and the fourth drain bias voltage are all equal.

9. The Doherty power amplifier according to claim 8, characterized in that, The ratio of the first power density to the second power density is in the range of 1:2 to 1:

8.

10. A transceiver array, characterized in that, include: Transceiver array substrate; A first transceiver, the first transceiver being coupled to the transceiver array substrate and having a first multi-stage amplifier, the first multi-stage amplifier comprising the features of a multi-stage amplifier according to claims 1 to 7. A second transceiver, coupled to the transceiver array substrate and having a second multistage amplifier, the second multistage amplifier comprising the features of a multistage amplifier according to claims 1 to 7; and An interconnect bias power line network, coupled to the transceiver array substrate and electrically connected to the first and second multistage amplifiers, helps to provide a single drain bias voltage.

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