Scan drive unit

Abstract

The scan driver according to the present invention includes stage circuits, wherein each of the stage circuits includes a first transistor and a capacitor, the first transistor having a gate electrode connected to a first clock line, an electrode connected to a first node, and another electrode connected to an input carry line, the capacitor having an electrode connected to the first node and another electrode connected to a second node, wherein the second node is connected to an output carry line, and the second node is connected to one of a first power supply voltage line and a second power supply voltage line.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a scan driver. Background Art

[0002] As information technology develops, the importance of display devices as a connection medium between users and information has become prominent. Due to the importance of display devices, the use of various display devices such as liquid crystal display (LCD) devices, organic light emitting display devices, and plasma display devices has increased.

[0003] The display device writes a data voltage corresponding to each pixel and allows each pixel to emit light. Each pixel emits light having a brightness corresponding to the written data voltage. The displayed image can be represented by a combination of light emissions of these pixels.

[0004] The scan driver includes a plurality of stage circuits, each of which generates a scan signal for determining a pixel to which a data voltage is to be written. Since each scan signal should be transmitted to a plurality of pixels, they have a larger RC delay than that of other signals. Therefore, when the driving capability of each stage circuit is insufficient, overlap between scan signals may occur, and thus an erroneous data voltage may be written to the pixel. Summary of the invention

[0005] Technical issues

[0006] Various embodiments of the present disclosure relate to a scan driver in which a stage circuit is implemented as a CMOS circuit to have excellent driving capability.

[0007] Solutions to technical problems

[0008] A scan driver according to an embodiment of the present disclosure may include a plurality of stage circuits, wherein each of the plurality of stage circuits may include a first transistor and a capacitor, wherein a first electrode of the first transistor is coupled to a first node, a second electrode of the first transistor is coupled to an input carry line, and a gate electrode of the first transistor is coupled to a first clock line, wherein a first electrode of the capacitor is coupled to the first node, and a second electrode of the capacitor is coupled to a second node, wherein the second node is coupled to an output carry line, and wherein the second node is coupled to any one of a first power supply voltage line and a second power supply voltage line.

[0009] The scan driver may further include a second transistor, wherein a first electrode of the second transistor is coupled to the second node, a second electrode of the second transistor is coupled to the second power supply voltage line, and a gate electrode of the second transistor is coupled to a second clock line.

[0010] The scan driver may further include a third transistor, wherein a first electrode of the third transistor is coupled to the first power supply voltage line, a second electrode of the third transistor is coupled to the second node, and a gate electrode of the third transistor is coupled to a third node.

[0011] The scan driver may further include a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the second node, a second electrode of the fourth transistor is coupled to the second power supply voltage line, and a gate electrode of the fourth transistor is coupled to the third node.

[0012] The scan driver may further include a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the first power supply voltage line, a second electrode of the fifth transistor is coupled to the third node, and a gate electrode of the fifth transistor is coupled to the first node.

[0013] The scan driver may further include a sixth transistor, wherein a first electrode of the sixth transistor is coupled to the third node, a second electrode of the sixth transistor is coupled to the second clock line, and a gate electrode of the sixth transistor is coupled to the first node.

[0014] The first transistor, the third transistor, and the fifth transistor may be P-type transistors, and the second transistor, the fourth transistor, and the sixth transistor may be N-type transistors.

[0015] The scan driver may further include a first inverter, wherein an input terminal of the first inverter is coupled to the second node and an output terminal of the first inverter is coupled to a scan line.

[0016] The scan driver may further include a second inverter, wherein an input terminal of the second inverter is coupled to the scan line and an output terminal of the second inverter is coupled to an inverted scan line.

[0017] Pulses of the first clock signal applied to the first clock line may not overlap in time with pulses of the second clock signal applied to the second clock line.

[0018] Effects of the Invention

[0019] Since the stage circuit is implemented as a CMOS circuit, the scan driver according to the present disclosure has excellent driving capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0021] Figure 2is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0022] Figure 3 is a diagram showing a stage circuit according to an embodiment of the present disclosure.

[0023] Figure 4 Is shown driving Figure 3 A diagram of the method of the stage circuit.

[0024] Figure 5 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0025] Figure 6 Is shown driving Figure 5 Schematic diagram of the pixel method.

[0026] Figure 7 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0027] Figure 8 is a diagram illustrating a scan driver according to another embodiment of the present disclosure.

[0028] Fig. 9 is a diagram illustrating a stage circuit according to another embodiment of the present disclosure.

[0029] Fig.10 Is shown driving Fig. 9 A diagram of the method of the stage circuit.

[0030] Fig.11 is a diagram illustrating a pixel according to another embodiment of the present disclosure.

[0031] Fig.12 Is shown driving Fig.11 Schematic diagram of the pixel method. DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various different forms without being limited to the following embodiments.

[0033] In addition, parts not related to the present disclosure will be omitted in the accompanying drawings to explain the present disclosure more clearly. Reference should be made to the accompanying drawings in which similar reference numerals are used to refer to similar parts in all different drawings. Therefore, the reference numerals described in the previous drawings may be used in other drawings.

[0034] In addition, since the sizes and thicknesses of corresponding components are arbitrarily indicated in the drawings for the convenience of description, the present disclosure is not limited by the drawings. The sizes, thicknesses, etc. of components in the drawings may be exaggerated to make the description of various layers and regions clear.

[0035] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] Reference Figure 1 , a display device 9 according to an embodiment of the present disclosure includes a timing controller 10 , a pixel part 20 , a data driver 30 , a scan driver 40 , and an emission control driver 50 .

[0037] The timing controller 10 converts control signals and image signals supplied from a processor (eg, application processor) according to specifications of the display device 9 , and supplies required control signals and required image signals to the data driver 30 , the scan driver 40 , and the emission control driver 50 .

[0038] The pixel component 20 may include pixels PX11, PX12, ..., PX1m, PX21, PX22, ..., PX2m, ..., PXn1, PXn2, ..., PXnm. Each of the pixels may be connected to a data line and a scan line corresponding thereto. Each pixel may receive a data voltage from a corresponding data line in response to a scan signal received from a corresponding scan line. Each pixel may emit light having a brightness corresponding to the data voltage in response to an emission control signal received from a corresponding emission control line. Each pixel may be connected to a first drive voltage line ELVDD, a second drive voltage line ELVSS, and an initialization voltage line VINT, and may then be supplied with a desired voltage.

[0039] The data driver 30 may receive a control signal and an image signal from the timing controller 10 and may then generate data voltages to be supplied to the data lines D1, D2, ..., Dm. The data voltages generated based on pixel rows may be simultaneously applied to the data lines D1, D2, ..., Dm.

[0040] The scan driver 40 receives a control signal from the timing controller 10 and then generates a scan signal to be supplied to the scan lines S0, S1, S2, . . . , Sn. Figure 2 The scan driver 40 according to the embodiment is described in detail.

[0041] The emission control driver 50 may supply an emission control signal for determining the emission period of the pixels PX11, PX12, ..., PX1m, PX21, PX22, ..., PX2m, ..., PXn1, PXn2, ..., PXnm through the emission control lines E1, E2, ..., En. For example, each pixel may include an emission control transistor, and whether the current will flow into the organic light emitting diode is determined according to the on / off operation of the emission control transistor, and thus emission control may be performed. According to an embodiment, the emission control driver 50 may be configured as a sequential emission type in which each pixel row sequentially emits light, and according to other embodiments, the emission control driver 50 may be configured as a simultaneous emission type in which all pixel rows emit light simultaneously.

[0042] Figure 2 is a diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0043] Reference Figure 2 , the scan driver 40 according to the embodiment includes stage circuits ST0 , ST1 , ST2 , ST3 , . . .

[0044] Each stage circuit is connected to a first clock line CLK1, a second clock line CLK2, a first power supply voltage line VGH, a second power supply voltage line VGL, corresponding carry lines CR0, CR1, CR2, CR3, ... and corresponding scan lines S0, S1, S2, S3, ... However, the first stage circuit ST0 is connected to the start signal line FLM because there is no input carry line therein.

[0045] A high voltage is applied to the first power supply voltage line VGH, and a voltage lower than the voltage of the first power supply voltage line VGH is applied to the second power supply voltage line VGL. A first clock signal generating a pulse at a first period may be applied to the first clock line CLK1. A second clock signal generating a pulse at a second period may be applied to the second clock line CLK2. The pulse may be a falling pulse with a low level. The first period and the second period may be equal to each other. Here, the pulses of the first clock signal and the pulses of the second clock signal may not overlap each other in time.

[0046] When a start pulse is applied through the start signal line FLM coupled to the first stage circuit ST0 , the first stage circuit ST0 outputs a carry signal generated by an internal operation to the carry line CR0 , and outputs a scan signal to the scan line S0 .

[0047] When a carry signal is applied through the carry line CR0 coupled to the next-stage circuit ST1 , the next-stage circuit ST1 outputs the carry signal generated by an internal operation to the carry line CR1 , and outputs the scan signal to the scan line S1 .

[0048] This operation is repeatedly performed by the next stage circuits ST2, ST3, . . . .

[0049] Since the stage circuits ST0, ST1, ST2, ST3, . . . have substantially the same internal structure, description will be made on the assumption that an arbitrary i-th stage circuit is provided.

[0050] Figure 3 is a diagram showing a stage circuit according to an embodiment of the present disclosure.

[0051] Reference Figure 3 According to an embodiment, the stage circuit STi may selectively include transistors T1, T2, T3, T4, T5 and T6, a capacitor C1 and a first inverter INV1.

[0052] The first transistor T1 may be coupled to the first node N1 at a first electrode thereof, coupled to the input carry line CR(i-1) at a second electrode thereof, and coupled to the first clock line CLK1 at a gate electrode thereof.

[0053] The capacitor C1 may be coupled to the first node N1 at a first electrode thereof, and coupled to the second node N2 at a second electrode thereof.

[0054] The second node N2 may be coupled to the output carry line CRi. The second node N2 may be coupled to one of the first power voltage line VGH and the second power voltage line VGL.

[0055] The second transistor T2 may be coupled to the second node N2 at a first electrode thereof, coupled to the second power supply voltage line VGL at a second electrode thereof, and coupled to the second clock line CLK2 at a gate electrode thereof.

[0056] The third transistor T3 may be coupled to the first power voltage line VGH at a first electrode thereof, coupled to the second node N2 at a second electrode thereof, and coupled to a third node N3 at a gate electrode thereof.

[0057] The fourth transistor T4 may be coupled to the second node N2 at a first electrode thereof, coupled to the second power supply voltage line VGL at a second electrode thereof, and coupled to the third node N3 at a gate electrode thereof.

[0058] The fifth transistor T5 may be coupled at a first electrode thereof to the first power supply voltage line VGH, at a second electrode thereof to the third node N3 , and at a gate electrode thereof to the first node N1 .

[0059] The sixth transistor T6 may be coupled to the third node N3 at a first electrode thereof, coupled to the second clock line CLK2 at a second electrode thereof, and coupled to the first node N1 at a gate electrode thereof.

[0060] The first inverter INV1 may be coupled to the second node N2 at an input terminal thereof, and coupled to the scan line Si at an output terminal thereof.

[0061] The first transistor T1 , the third transistor T3 , and the fifth transistor T5 may be P-type transistors, and the second transistor T2 , the fourth transistor T4 , and the sixth transistor T6 may be N-type transistors.

[0062] The term "P-type transistor" generally refers to a transistor through which an increasing amount of current flows when the voltage difference between the gate electrode and the source electrode increases in a negative direction. The term "N-type transistor" generally refers to a transistor through which an increasing amount of current flows when the voltage difference between the gate electrode and the source electrode increases in a positive direction. Each transistor may be implemented as any of various types of transistors, such as a thin film transistor (TFT), a field effect transistor (FET), and a bipolar junction transistor (BJT).

[0063] According to the present embodiment, the third transistor T3 and the fourth transistor T4 can be implemented with a CMOS type, the fifth transistor T5 and the sixth transistor T6 can be implemented with a CMOS type, and the first inverter INV1 can be implemented with a CMOS type. In each CMOS type, the P-type transistors T3, T5, ... are responsible for and perform the pull-up function, and the N-type transistors T4, T6, ... are responsible for and perform the pull-down function, and therefore the current driving capability is better than the current driving capability of the existing stage circuit composed of only P-type transistors or only N-type transistors. In addition, since the channel width of the buffer transistor can be reduced, there is an advantage that the circuit area and power consumption can be reduced.

[0064] Figure 4 Is shown driving Figure 3 A diagram of the method of the stage circuit.

[0065] Reference Figure 4 , shows a first clock signal applied to a first clock line CLK1, a second clock signal applied to a second clock line CLK2, an input carry signal applied to an input carry line CR(i-1), an output carry signal applied to an output carry line CRi, and a scan signal applied to a scan line Si. The next scan signal applied to a scan line S(i+1) is shown for timing comparison.

[0066] During the period P1, the first clock signal is at a low level, and the second clock signal is at a high level. That is, a falling pulse is generated in the first clock signal. At this time, the input carry signal is at a high level.

[0067] Therefore, the first transistor T1 is turned on in response to the first clock signal, and the first node N1 is charged to a high level in response to the input carry signal. In addition, since the second transistor T2 is turned on in response to the second clock signal and the second node N2 is coupled to the second power supply voltage line VGL, the second node N2 is charged to a low level.

[0068] Therefore, during the period P1 , the scan signal is maintained at a high level and the output carry signal is maintained at a low level.

[0069] During the period P2, the first clock signal turns to a high level, and thus the first transistor T1 is turned off. Here, the voltage of the first node N1 is maintained by the voltage stored in the capacitor C1 and the second power voltage line VGL, and then remains at a high level.

[0070] During the period P3, the first clock signal is at a high level, and the second clock signal is at a low level. That is, a falling pulse is generated in the second clock signal.

[0071] At present, in response to the high level voltage of the first node N1, the sixth transistor T6 is in a conducting state. Therefore, the low level second clock signal is applied to the third node N3, and thus the third transistor T3 is turned on. Through the turned-on third transistor T3, the first power supply voltage line VGH is coupled to the second node N2, and the second node N2 is charged to a high level.

[0072] Therefore, during the period P3, the scan signal turns to a low level, and the output carry signal turns to a high level. That is, a falling pulse is generated in the scan signal, and a rising pulse is generated in the output carry signal.

[0073] During period P4, the second clock signal turns to a high level, and thus the second transistor T2 is turned on and the second node N2 is coupled to the second power voltage line VGL. Therefore, the second node N2 is charged to a low level, and the voltage of the first node N1 also turns to a low level due to coupling caused by the capacitor C1.

[0074] Therefore, during the period P4, the scan signal transitions to a high level, and the output carry signal transitions to a low level.

[0075] During the period P5, the first clock signal is at a low level, and the second clock signal is at a high level. That is, a falling pulse is generated in the first clock signal.

[0076] However, unlike in the period P1, the input carry signal is at a low level. Therefore, the first node N1 is charged to a low level.

[0077] During the period P6, the first clock signal is at a high level and the second clock signal is at a low level. That is, a falling pulse is generated in the second clock signal.

[0078] However, at this time, unlike in period P3, in response to the low level voltage of the first node N1, the sixth transistor T6 is in the off state. Therefore, the low level second clock signal cannot be applied to the third node N3, and thus the third transistor T3 remains in the off state. Therefore, the second node N2 not connected to the first power supply voltage line VGH remains at a low level.

[0079] Therefore, during the period P6 , the scan signal is maintained at a high level and the output carry signal is maintained at a low level.

[0080] Figure 5 is a diagram illustrating a pixel according to an embodiment of the present disclosure.

[0081] Reference Figure 5 , the pixel PXij may include transistors M1, M2, M3, M4, M5, M6, and M7, a storage capacitor Cst1, and an organic light emitting diode OLED1. The transistors M1 to M7 may be P-type transistors.

[0082] The storage capacitor Cst1 may be coupled at a first electrode thereof to the first driving voltage line ELVDD and at a second electrode thereof to the gate electrode of the transistor M1 .

[0083] The transistor M1 may be coupled at its first electrode to the second electrode of the transistor M5, at its second electrode to the first electrode of the transistor M6, and at its gate electrode to the second electrode of the storage capacitor Cst1. The transistor M1 may be referred to as a driving transistor. The transistor M1 determines the amount of driving current flowing between the first driving voltage line ELVDD and the second driving voltage line ELVSS according to the potential difference between its gate electrode and source electrode.

[0084] The transistor M2 may be coupled to the data line Dj at its first electrode, coupled to the first electrode of the transistor M1 at its second electrode, and coupled to the scan line Si at its gate electrode. The transistor M2 may be referred to as a scan transistor. When a scan signal having a turn-on level is applied to the scan line Si, the transistor M2 inputs a data voltage of the data line Dj to the pixel PXij.

[0085] The transistor M3 is coupled to the second electrode of the transistor M1 at its first electrode, to the gate electrode of the transistor M1 at its second electrode, and to the scan line Si at its gate electrode. When a scan signal having a turn-on level is applied to the scan line Si, the transistor M3 allows the transistor M1 to be coupled in the form of a diode.

[0086] The transistor M4 is coupled to the gate electrode of the transistor M1 at its first electrode, to the initialization voltage line VINT at its second electrode, and to the scan line S(i-1) at its gate electrode. In other embodiments, the gate electrode of the transistor M4 may be coupled to another scan line. When a scan signal having an on level is applied to the scan line S(i-1), the transistor M4 initializes the amount of charge in the gate electrode of the transistor M1 by transmitting the initialization voltage to the gate electrode of the transistor M1.

[0087] The transistor M5 is coupled to the first driving voltage line ELVDD at its first electrode, to the first electrode of the transistor M1 at its second electrode, and to the emission control line Ei at its gate electrode. The transistor M6 is coupled to the second electrode of the transistor M1 at its first electrode, to the anode of the organic light emitting diode OLED1 at its second electrode, and to the emission control line Ei at its gate electrode. Each of the transistors M5 and M6 may be referred to as an emission control transistor. When an emission control signal having a turn-on level is applied to the transistors M5 and M6, the transistors M5 and M6 form a driving current path between the first driving voltage line ELVDD and the second driving voltage line ELVSS, thereby allowing the organic light emitting diode OLED1 to emit light.

[0088] The transistor M7 is coupled to the anode of the organic light emitting diode OLED1 at its first electrode, to the initialization voltage line VINT at its second electrode, and to the scan line Si at its gate electrode. In other embodiments, the gate electrode of the transistor M7 may be coupled to another scan line. When a scan signal having an on level is applied to the transistor M7, the transistor M7 initializes the amount of charge accumulated in the organic light emitting diode OLED1 by transmitting the initialization voltage to the anode of the organic light emitting diode OLED1.

[0089] The organic light emitting diode OLED1 may be coupled at an anode thereof to the second electrode of the transistor M6 , and at a cathode thereof to the second driving voltage line ELVSS.

[0090] Figure 6 Is shown driving Figure 5 Schematic diagram of the pixel method.

[0091] During the period PP1, the data voltage DATA(i-1)j for the previous pixel row is applied to the data line Dj, and a scan signal having a turn-on level (low level) is applied to the scan line S(i-1).

[0092] Since the scan signal having a turn-off level (high level) is applied to the scan line Si, the transistor M2 is in a turn-off state and the data voltage DATA(i-1)j for the previous pixel row is prevented from being input into the pixel PXij.

[0093] At this time, since the transistor M4 is in the on state, the initialization voltage is applied to the gate electrode of the transistor M1, and thus the charge amount is initialized. Since the emission control signal having the off level is applied to the emission control line Ei, the transistors M5 and M6 are in the off state, and unnecessary emission of the organic light emitting diode OLED1 due to the process of applying the initialization voltage is prevented.

[0094] During period PP2, a data voltage DATAij for a current pixel row is applied to the data line Dj, and a scan signal having an on level is applied to the scan line Si. Therefore, transistors M2, M1, and M3 are turned on, and thus the data line Dj and the gate electrode of the transistor M1 are electrically coupled to each other. Therefore, the data voltage DATAij is applied to the second electrode of the storage capacitor Cst1, and the storage capacitor Cst1 accumulates a charge amount corresponding to the difference between the voltage of the first driving voltage line ELVDD and the data voltage DATAij.

[0095] At this time, since the transistor M7 is in the on state, the initialization voltage is applied to the anode of the organic light emitting diode OLED1, and the organic light emitting diode OLED1 is precharged or initialized to a charge amount corresponding to a difference between the initialization voltage and the voltage of the second driving voltage line ELVSS.

[0096] When an emission control signal having an on level is applied to the emission control line Ei after the period PP2, the transistors M5 and M6 are turned on, and the amount of driving current passing through the transistor M1 is adjusted according to the amount of charge accumulated in the storage capacitor Cst1, and thus the driving current flows through the organic light emitting diode OLED1. The organic light emitting diode OLED1 emits light until an emission control signal having an off level is applied to the emission control line Ei.

[0097] Figure 7 is a diagram illustrating a display device according to another embodiment of the present disclosure.

[0098] Reference Figure 7 , a display device 9 ′ according to another embodiment of the present disclosure includes a timing controller 10 , a pixel part 20 ′, a data driver 30 , a scan driver 40 ′, and an emission control driver 50 .

[0099] Due to Figure 1Compared with the display device 9 of FIG. 1 , the display device 9 ′ is substantially the same as the display device 9 except for the configuration of the pixel part 20 ′ and the scan driver 40 ′, and thus a repeated description thereof will be omitted.

[0100] For any pixel row, the pixel component 20' and the scan driver 40' are connected to each other through the scan lines S1, S2, ..., Sn and the inverted scan lines SB0, SB1, SB2, ..., SBn. Figure 8 The changed pixel structure of the pixel part 20' and the stage circuit structure of the scan driver 40' are described with reference to the following figures.

[0101] Figure 8 is a diagram illustrating a scan driver according to another embodiment of the present disclosure.

[0102] Reference Figure 8 , the scan driver 40' includes stage circuits ST0', ST1', ST2', ST3', . . .

[0103] Since the scan driver 40' is connected to the inverted scan lines SB0, SB1, SB2, SB3, ..., the scan driver 40' is connected to the inverted scan lines SB0, SB1, SB2, SB3, ... Figure 2 The scan driver 40 is the same as that of FIG. 4 , and thus a repeated description thereof will be omitted.

[0104] Each level of the scan driver 40' is provided with an inverted scan line as an output line in addition to the corresponding scan line. According to the embodiment, the scan line of the first stage circuit ST0' may also be used only to generate an inverted scan signal without extending to the pixel component 20'. The use of each output line may be configured differently according to the signal required for each pixel.

[0105] Fig. 9 is a diagram illustrating a stage circuit according to another embodiment of the present disclosure.

[0106] Reference Fig. 9 The stage circuit STi′ may include transistors T1 to T6, a capacitor C1, a first inverter INV1, and a second inverter INV2.

[0107] The second inverter INV2 may be coupled to the scan line Si at an input terminal thereof, and coupled to the inverted scan line SBi at an output terminal thereof.

[0108] Since the other components of the stage circuit STi' are Figure 3 Those components of the stage circuit STi are substantially the same, and thus repeated description thereof will be omitted.

[0109] Fig.10 Is shown driving Fig. 9 A diagram of the method of the stage circuit.

[0110] Reference Fig.10 , shows a first clock signal applied to the first clock line CLK1, a second clock signal applied to the second clock line CLK2, an input carry signal applied to the input carry line CR(i-1), an output carry signal applied to the output carry line CRi, a scan signal applied to the scan line Si, and an inverted scan signal applied to the inverted scan line SBi. The next scan signal applied to the scan line S(i+1) and the next inverted scan signal applied to the inverted scan line SB(i+1) are shown for timing comparison.

[0111] because Fig.10 The driving method and Figure 4 The driving method is substantially the same, so repeated description thereof will be omitted.

[0112] Fig.11 is a diagram showing a pixel according to another embodiment of the present disclosure, and Fig.12 Is shown driving Fig.11 Schematic diagram of the pixel method.

[0113] Reference Fig.11 , the pixel PXij′ includes transistors M1 , M2 , M3 , M4 ′, M5 , M6 , and M7 ′, a storage capacitor Cst1 , and an organic light emitting diode OLED1 .

[0114] and Figure 5 Compared with the pixel PXij of EMBODIMENT 2, the pixel PXij′ has substantially the same configuration except for the transistors M4′ and M7′, and thus a repeated description thereof will be omitted.

[0115] The transistor M4' may be implemented as an N-type transistor. A gate electrode of the transistor M4' may be coupled to the inversion scan line SB(i-1).

[0116] The transistor M7' may be implemented as an N-type transistor. A gate electrode of the transistor M7' may be coupled to the inversion scan line SBi.

[0117] For example, channels of the transistors M4 ′ and M7 ′ may be formed of an oxide semiconductor, and thus leakage current flowing into the initialization voltage line VINT may be minimized.

[0118] Reference Fig.12 The on-time and off-time of the transistors M1, M2, M3, M4', M5, M6 and M7' are substantially the same as those of the transistors M1, M2, M3, M4, M5, M6 and M7 according to the first embodiment. Therefore, repeated description will be omitted here.

[0119] The drawings and detailed description of the present disclosure to which reference has been made are merely exemplary for the present disclosure and are intended only to describe the present disclosure, rather than to limit the meaning of the present disclosure described in the claims or to limit its scope. Therefore, it will be understood by those skilled in the art that various modifications and other embodiments may be implemented from these embodiments. Therefore, the scope of the present disclosure should be limited by the technical spirit of the appended claims.

Claims

1. A scanning driver, comprising: Multiple stage circuits, Wherein, each of the plurality of stage circuits comprises: a first transistor, wherein a first electrode of the first transistor is coupled to a first node, a second electrode of the first transistor is coupled to an input carry line, and a gate electrode of the first transistor is coupled to a first clock line; a capacitor, wherein a first electrode of the capacitor is coupled to the first node and a second electrode of the capacitor is coupled to a second node; and a second transistor, wherein a first electrode of the second transistor is coupled to the second node, a second electrode of the second transistor is coupled to a second power supply voltage line, and a gate electrode of the second transistor is coupled to a second clock line, wherein the second node is connected to an output carry line, wherein the second node is connected to any one of the first power supply voltage line and the second power supply voltage line, and The pulses of the first clock signal applied to the first clock line and the pulses of the second clock signal applied to the second clock line do not overlap in time.

2. The scan driver according to claim 1, further comprising: a third transistor, wherein a first electrode of the third transistor is coupled to the first power supply voltage line, a second electrode of the third transistor is coupled to the second node, and a gate electrode of the third transistor is coupled to a third node.

3. The scan driver according to claim 2, further comprising: a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the second node, a second electrode of the fourth transistor is coupled to the second power supply voltage line, and a gate electrode of the fourth transistor is coupled to the third node.

4. The scan driver according to claim 3, further comprising: a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the first power supply voltage line, a second electrode of the fifth transistor is coupled to the third node, and a gate electrode of the fifth transistor is coupled to the first node.

5. The scan driver according to claim 4, further comprising: A sixth transistor, wherein a first electrode of the sixth transistor is coupled to the third node, a second electrode of the sixth transistor is coupled to the second clock line, and a gate electrode of the sixth transistor is coupled to the first node.

6. The scan driver according to claim 5, wherein: The first transistor, the third transistor and the fifth transistor are P-type transistors, and The second transistor, the fourth transistor and the sixth transistor are N-type transistors.

7. The scan driver according to claim 6, further comprising: A first inverter, wherein an input terminal of the first inverter is coupled to the second node and an output terminal of the first inverter is coupled to a scan line.

8. The scan driver according to claim 7, further comprising: A second inverter, wherein an input terminal of the second inverter is coupled to the scan line and an output terminal of the second inverter is coupled to an inverted scan line.

Images