Imaging system and method for reading out image signals with variable timing

Abstract

An imaging system and method for reading out image signals with variable timing are disclosed. The imaging system can have an array of image sensor pixels arranged in rows and columns and column readout circuitry coupled to the array. The pixel rows can receive drive signals from a row driver circuit and can send the drive signals from a timing circuit based on the position of the row within the array. In particular, rows closer to the readout circuitry can require less settling time and thus be driven faster than rows further away from the readout circuitry. All rows can be driven in a single direction, or the pixel array can have a cutout, in which case the rows above the cutout can be driven upward and the rows below the cutout can be driven downward. A frame buffer can be used to store the signals generated by the pixel rows and can resolve the asynchronous readout of the image data.

Description

[0001] This application claims the benefit and priority of U.S. Patent Application 16 / 949540, filed November 3, 2020, and Indian Patent Application 202011004380, filed January 31, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates generally to imaging systems and methods for reading out image signals in a variable timing sequence, and more specifically, to imaging sensors with circuitry capable of reading out image signals in a variable timing sequence. Background Technology

[0003] Image sensors are commonly used in electronic devices such as mobile phones, cameras, and computers to capture images. In a typical arrangement, an image sensor comprises an array of image pixels arranged in rows and columns. Circuitry can be coupled to each pixel column to read out the image signal generated by the image pixels.

[0004] A typical image sensor includes column readout circuitry that performs various readout operations that allow the image signal generated from the image pixels to be transferred to an image processor. In conventional systems, column readout operations may take longer than expected, resulting in a longer readout time than the image sensor's intended frame rate.

[0005] Therefore, it is desirable to provide an imaging device with improved readout circuitry. Summary of the Invention

[0006] According to one aspect, an imaging system is provided, comprising: a pixel array arranged in rows and columns and configured to generate an image signal in response to incident light; a variable timing circuit configured to drive an input to a pixel row in the pixel array at a variable rate; and a column output circuit configured to output the image signal generated by the pixels in the pixel row in response to the input.

[0007] According to another aspect, a method for reading out an image signal with variable timing is provided, comprising: generating an image signal using an image pixel array comprising rows and columns of image pixels; generating a readout signal with variable timing based on the position of the rows in the image pixel array using a row driver circuit; reading out the image signal of the rows of the image pixels using a column readout circuit; and storing the image signal in a frame buffer.

[0008] According to another aspect, an imaging system is provided, comprising: an image sensor including: an image pixel array including rows and columns of image pixels configured to generate an image signal; a column output circuit configured to output the image signal generated by pixels in the rows of the image pixels; a row driver circuit configured to drive the image signal from the rows to the column output circuit; a variable timing circuit configured to drive the row driver circuit at a variable rate determined based on the position of a given row in the image pixel array; and a data interface receiving the image signal from the column output circuit; and an image processor including: a frame buffer configured to store the image signal when it is read out.

[0009] Embodiments of the present invention provide an imaging system with a variable readout timing circuit that can reduce the frame rate of an image sensor. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an exemplary electronic device according to one embodiment, which has an image sensor and processing circuitry for capturing images using an image pixel array.

[0011] Figure 2 This is a schematic diagram of an exemplary pixel array according to one embodiment and an associated readout circuit for reading image signals from the pixel array.

[0012] Figure 3 This is a schematic diagram of an exemplary pixel array with variable timing readout circuitry according to one embodiment.

[0013] Figure 4 This is a flowchart illustrating exemplary steps that can be performed by a variable pixel array and timing readout circuitry according to one embodiment.

[0014] Figure 5 This is a graph illustrating an exemplary relationship between multiple variable timing elements across a pixel array and the associated frame rate according to one embodiment. Detailed Implementation

[0015] Embodiments of the present invention relate to imaging apparatuses, and more specifically, to imaging apparatuses having variable readout timing circuitry. Those skilled in the art will recognize that exemplary embodiments of the invention may be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring the embodiments.

[0016] Imaging systems with digital camera modules are widely used in electronic devices such as digital cameras, computers, mobile phones, and other electronic devices. A digital camera module may include one or more image sensors that collect incident light to capture an image. The image sensor may include an array of image pixels. Pixels in the image sensor may include photosensitive elements, such as photodiodes that convert incident light into electrical charge. An image sensor may have any number (e.g., hundreds or thousands or more) of pixels. A typical image sensor may have hundreds, thousands, or millions of pixels (e.g., megapixels). The image sensor may include control circuitry (e.g., circuitry for operating the image pixels) and readout circuitry for reading out an image signal corresponding to the electrical charge generated by the photosensitive elements. In some cases, the readout circuitry may read out the image signal from the pixels line by line, and each line may be read out at the same speed. However, in some cases, it may be desirable to increase the readout speed of the circuitry, thereby increasing the frame rate of the camera. Therefore, the image sensor may include variable timing readout circuitry to increase the readout speed of at least some lines in the pixel array.

[0017] Figure 1 This is a schematic diagram of an exemplary imaging system (such as an electronic device) that uses an image sensor to capture images. Figure 1 The electronic device 10 can be a portable electronic device, such as a camera, cellular phone, tablet computer, webcam, camcorder, video surveillance system, vehicle imaging system, video game system with imaging capabilities, or any other desired imaging system or device for capturing digital image data. The camera module 12 can be used to convert incident light into digital image data. The camera module 12 may include one or more lenses 14 and one or more corresponding image sensors 16. The lenses 14 may include fixed lenses and / or adjustable lenses, and may include microlenses formed on the imaging surface of the image sensor 16. During image capture operation, light from the scene can be focused onto the image sensor 16 through the lenses 14. The image sensor 16 may include circuitry for converting analog pixel data into corresponding digital image data to be provided to the storage and processing circuitry 18. If desired, the camera module 12 may be configured with an array of lenses 14 and an array of corresponding image sensors 16.

[0018] The storage and processing circuitry 18 may include one or more integrated circuits (e.g., image processing circuitry, a microprocessor, a storage device such as random access memory and non-volatile memory, etc.) and may be implemented using components separate from and / or forming part of the camera module 12 (e.g., circuitry forming part of an integrated circuit including the image sensor 16 or an integrated circuit within the module 12 associated with the image sensor 16). The processing circuitry 18 may be used to process and store image data captured by the camera module 12 (e.g., using an image processing engine on the processing circuitry 18, using an imaging mode selection engine on the processing circuitry 18, etc.). The processed image data may be provided to external devices (e.g., a computer, an external display, or other devices) as needed using wired and / or wireless communication paths coupled to the processing circuitry 18.

[0019] like Figure 2 As shown, the image sensor 16 may include an image array 20 containing image sensor pixels 22 arranged in rows and columns (sometimes referred to herein as image pixels or pixels) and control and processing circuitry 24. The array 20 may contain, for example, hundreds or thousands of rows and hundreds or thousands of columns of image sensor pixels 22. The control circuitry 24 may be coupled to row control circuitry 26 (sometimes referred to herein as row decoder) and image readout circuitry 28 (sometimes referred herein as column control circuitry, column control and readout circuitry, column readout circuitry, readout circuitry, processing circuitry, or column decoder circuitry). The row control circuitry 26 may receive row addresses from the control circuitry 24 and provide corresponding row control signals, such as reset control signals, row selection control signals, charge transfer control signals, double conversion gain control signals, and readout control signals, to the pixels 22 via row control path 30 to drive the readout of pixels in the pixel rows. One or more wires (such as column lines 32) may be coupled to each column of pixels 22 in the array 20. Column line 32 can be used to read image signals from pixel 22 and to provide bias signals (e.g., bias current or bias voltage) to pixel 22. If needed, during pixel readout operation, row control circuitry 26 can be used to select a pixel row in array 20, and the image signal generated by the image pixel 22 in that pixel row can be read along column line 32.

[0020] Image readout circuit 28 (sometimes referred to as column readout and control circuit 28) receives image signals (e.g., analog pixel values ​​generated by pixel 22) via column lines 32. Image readout circuit 28 may include sample-and-hold circuitry for sampling and temporarily storing image signals read from array 20, amplifier circuitry, analog-to-digital converter (ADC) circuitry, bias circuitry, column memory, latch circuitry for selectively enabling or disabling column circuitry, or other circuitry coupled to one or more pixel columns in array 20 for operating pixel 22 and for reading image signals from pixel 22. The ADC circuitry in readout circuit 28 converts the analog pixel values ​​received from array 20 into corresponding digital pixel values ​​(sometimes referred to as digital image data or digital pixel data). Image readout circuit 28 provides digital pixel data for pixels in one or more pixel columns to control and processing circuitry 24 and / or processor 18. Figure 1 ).

[0021] If desired, image pixel 22 may include one or more photosensitive areas to generate charge in response to image light. The photosensitive areas within image pixel 22 may be arranged in rows and columns on array 20. Pixel array 20 may be provided with a color filter array having multiple color filter elements, allowing a single image sensor to sample different colors of light. For example, image sensor pixels (such as image pixels in array 20) may be provided with a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels arranged in a Bayer mosaic pattern. The Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. In another suitable example, the green pixels in the Bayer pattern are replaced with broadband image pixels having broadband color filter elements (e.g., transparent color filter elements, yellow color filter elements, etc.). In another example, the image pixels may have filter elements that allow light outside the visible wavelengths (e.g., infrared or ultraviolet light) to pass through to the pixels below, while blocking visible wavelengths. Alternatively, array 20 may be a monochromatic array. A monochromatic array may have broadband color filters that are visible-light transparent and transmit light within the visible spectrum (e.g., a broadband color filter allows white light to pass to the pixels below). However, generally, a monochromatic array may have any desired color filter. The color filter may also include light redirection structures, such as Fresnel lenses, to focus light onto the pixels below. These examples are merely exemplary, and in general, any desired color and any desired pattern of filter elements can be formed over any desired number of image pixels 22.

[0022] Image sensor 16 can be configured to support global shutter operation (e.g., pixel 22 can operate in global shutter mode). For example, each image pixel 22 in array 20 may include a photodiode, a floating diffusion region, and a local charge storage region. Using a global shutter scheme, all pixels in the image sensor are simultaneously reset. Then, using a charge transfer operation, the charge collected in the photodiode of each image pixel is simultaneously transferred to the associated charge storage region. Data can then be read out line by line from each storage region, for example.

[0023] Typically, the image readout circuit 28 can use correlated double sampling to determine the charge generated by each pixel 22. Specifically, the pixel value (e.g., the value corresponding to the charge generated by the pixel) at each location in the array 20 can be calculated by comparing a known reset voltage with the voltage generated by the pixel. However, to perform this comparison, the readout circuit 28 must first be charged to the reset voltage and then charged to the pixel voltage as each row within the readout array 20 is read. Changing the charge value from the reset voltage to the pixel voltage requires a settling time. For example, this settling time can be proportional to the difference between the reset voltage and the pixel voltage. Generally, each row of pixels is read out at the same rate. However, due to the distance required for the charge to travel, rows closer to the column readout point have a lower RC time constant (the product of circuit resistance and circuit capacitance) than rows farther from the column readout point. Therefore, rows closer to the column readout point require less settling time than rows farther from the column readout point. Therefore, the image sensor can include variable timing circuitry to variably reduce the readout time of rows closer to the column readout point, thereby increasing the frame rate of the image sensor.

[0024] exist Figure 3 An exemplary image sensor with variable timing circuitry is shown in the figure. Figure 3 As shown, pixel array 20 can be coupled to row driver circuits 26A and 26B and to column readout circuits 28A and 28B. For example, row driver circuits 26A and 26B can be... Figure 2 It is part of the row control circuit 26, and the column readout circuits 28A and 28B can be Figure 2 It is part of the column readout and control circuit 28.

[0025] Pixels 22 of array 20 can generate charge in response to incident light. In a global shutter image sensor, all pixels 22 can generate charge and transfer the charge to the storage node simultaneously. Row drivers 26A and 26B can address a row of pixels to read the charge associated with that row via column readout circuits 28A and 28B. Sequencer 34 can be coupled to row driver circuits 26A and 26B and may include row counter 36 and timing generator 38.

[0026] Row counter 36 determines which row of array 20 should be addressed and read by column readout circuit 28. Timing generator 38 times the signals provided to row driver circuits 26A and 26B by sequencer 34. Specifically, timing generator 38 can vary the time length for reading a row of pixels based on the row's distance from column readout circuit 28A. Specifically, pixel rows closer to column readout circuit 28 can have a lower RC time constant and therefore require less settling time compared to pixel rows farther from readout circuit 28. Thus, the readout time for rows closer to column readout circuit 28 can be reduced relative to rows farther from column readout circuit 28 (e.g., signals can be provided to row driver 26 from timing generator 38 more quickly, resulting in faster readout). If desired, readout time can be applied to groups of rows in array 20. For example, groups of two, three, five, ten, more than five, less than ten, or any other desired number of rows of pixels can all have the same readout timing. For example, when the timing generator 38 receives the next group of rows corresponding to the row from the row counter 36, the readout timing can be adjusted based on a lookup table that provides the readout timing based on a given row. In this way, the frame rate of the image sensor 16 can be reduced compared to reading all rows of array 20 using the same readout time (e.g., the length of time used to adapt to the settling time of the row farthest from the column readout circuitry).

[0027] After being addressed by row driver circuits 26A and 26B, the signal for a given pixel row can be read out by column readout circuits 28A and 28B and then fed through data interface 40. Data interface 40 can then pass the signal to frame storage device 42 in image processor 18. Frame storage device 42 may include frame buffers that store signals generated by pixel 22 when other pixel rows are read out. Frame buffers in frame storage device 42 may be arranged side-by-side to address timing differences in readout pixel rows. Alternatively, if frame buffers are not arranged side-by-side, the full bandwidth of the data interface can be used to pass signals from at least some of the pixel rows through data interface 40 if needed. Thus, when signals arrive at the frame buffer, they can all be normalized (e.g., all can be data packets of the same size). In either case, frame buffers in frame storage device 42 may accommodate asynchronously arriving data from pixel rows. For example, frame buffers may receive data in packets and store blank data when no data is received. Then, the processing circuitry in the image processor 18 can reconstruct the data rows from the row data and the blank data from the frame buffer.

[0028] Data generated by array 20 can be read out in several ways via column readout circuits 28A and / or 28B. First, each row can be read entirely upwards or downwards (e.g., entirely towards column readout circuit 28A or towards column readout circuit 28B). In this case, only one of column readout circuits 28A or 28B may be needed. If the signal is read upwards (e.g., towards column readout circuit 28A), the top row of array 20 may have the shortest path to column readout circuit 28A, resulting in the lowest RC time constant and requiring the least settling time. The bottom row of array 20 may have the longest path to column readout circuit 28A, resulting in the largest RC time constant and requiring the most settling time. Therefore, timing generator 38 can drive the row driver signals from row driver circuits 26A and / or 26B at a faster rate for rows closer to the top row than for rows closer to the bottom row. For example, timing generator 38 can send read row driver signals at a first rate for a first group of rows, and at a second rate slower than the first rate for a second group of rows, and so on. A group of rows can be an equal division of rows, such as each group comprising five rows, ten rows, more than ten rows, less than fifteen rows, or any other desired number of rows. Alternatively, the group of rows can have a different number of rows. If needed, the rate for each row of pixels can be stored in a lookup table referenced by timing generator 38.

[0029] If the signal is read upwards from column readout circuit 28A, column readout circuit 28B can be omitted. Additionally, although row driver circuits 28A and 28B are shown as located on opposite sides of array 20, this is merely exemplary. If desired, row driver circuitry may be included on only one side of array 20.

[0030] Furthermore, although image sensor 16 is described as reading signals upwards toward column readout circuit 28A, signals can alternatively be read downwards toward column readout circuit 28B. Column readout circuit 28A can be omitted if necessary. If signals are read downwards (e.g., toward column readout circuit 28B), the bottom row of array 20 may have the shortest path to column readout circuit 28B, thus having the lowest RC time constant and requiring the least settling time. The top row of array 20 may have the longest path to column readout circuit 28B, thus having the largest RC time constant and requiring the most settling time. Therefore, timing generator 38 can drive row driver signals from row driver circuits 26A and / or 26B at a faster rate for rows closer to the bottom row than for rows closer to the top row.

[0031] Array 20 may also include an optional cutout 44 at the center of the array. The optional cutout 44 allows reading of pixel rows above the cutout 44 upwards toward column readout circuit 28A and downwards toward column readout circuit 28B below the cutout 44. If the optional cutout 44 is included, the furthest row from both column readout circuit 28A and column readout circuit 28B will be located at the center of array 20. Therefore, the center row will have the highest RC time constant and require the longest settling time. Consequently, the top and bottom rows of pixels (e.g., the rows closest to column readout circuit 28A and column readout circuit 28B, respectively) can be driven at the fastest rate, while the row at the center of the array can be driven at the slowest rate. When reading rows through column readout circuits 28A and 28B, the buffer in frame storage device 42 can simultaneously receive signals from pixel rows. For example, the frame buffer can simultaneously receive signals from the top and bottom rows of pixels and simultaneously receive signals from the center row. In this way, the frame rate of the image sensor 16 can be further reduced by reading multiple lines simultaneously in a variable timing.

[0032] Furthermore, instead of reading the rows above and below cutout 44 in a mirror manner as previously described (i.e., first reading the top and bottom rows of the array simultaneously, and finally reading the center row simultaneously), the rows closest to one of the column readout circuits 28A and 28B can be read simultaneously with the rows closest to cutout 44. For example, if the top row of the array is read first, the rows closest to cutout 44 on the lower half of array 20 can be read simultaneously (i.e., the rows closest to cutout 44 on the lower half of array 20 can be driven to be read simultaneously with the top row of the array). Each consecutive row below the top row can be read, wherein each consecutive row below the row closest to cutout 44 on the lower half of the array can be read, until the row closest to cutout 44 on the upper half of the array is read simultaneously with the bottom row of the array (i.e., the bottom row of the array can be driven to be read when the row closest to cutout 44 is read). However, the reverse arrangement can also be used, in which if the bottom row of the array is read first, the row closest to cut 44 in the upper half of array 20 can be read simultaneously. Each consecutive row above the bottom row can be read simultaneously with each consecutive row above the row closest to cut 44 in the upper half of the array, until the row closest to cut 44 in the lower half of the array is read simultaneously with the top row of the array.

[0033] In this scheme, the rows closest to column readout circuits 28A and 28B will still be read faster than the rows closest to cutout 44. Therefore, the timing will be asynchronous (e.g., fast rows will be read simultaneously with slow rows). To address this timing difference, while a slow row is being read, sequencer 34 can generate read row driver signals for multiple fast rows. For example, the first three fast rows can be read simultaneously with the previous slow row. However, this is merely illustrative. In general, any number of rows can be read simultaneously with slower rows.

[0034] The bandwidth of the data interface 40 can be distributed proportionally between the top and bottom portions of the array according to the speed at which the rows are being read. For example, rows read at a faster speed may require more bandwidth, and rows read at a slower speed may require less bandwidth. To address these differences, the data interface 40 can use time-domain multiplexing (TDM) to divide the bandwidth. In this way, the data interface 40 can transmit asynchronous signals from rows read at different rates to the frame storage device 42.

[0035] The frame storage device 42 can consider asynchronous signals while storing data generated by pixel 22. For example, the frame buffer in the frame storage device 42 can receive data in a packet and store blank data when no data is received. Then, the processing circuitry in the image processor 18 can reconstruct the data rows from the row data and the blank data from the frame buffer.

[0036] Although three methods for reading out the signal generated by array 20 have been described, any desired method can generally be used. The frame rate of image sensor 16 can be increased when coupled with timing of a variable line driver generated by timing generator 38. Figure 4 The flowchart illustrates the steps that can be used to read out image signals in a variable timing sequence. Combined with... Figure 2 and Figure 3 The components shown describe the steps.

[0037] like Figure 4 As shown, at step 46, the image pixel array 20 can be used to generate an image signal in response to incident light.

[0038] At step 48, row counter 36 determines the address of the pixel row to be read. The first row to be read can be either the topmost pixel row of array 20 or the bottommost pixel row of array 20. If multiple rows are read simultaneously (e.g., if cutout 44 is used), the topmost and bottommost rows can be read simultaneously first, the center rows on either side of cutout 44 can be read simultaneously, either the topmost or bottommost row and one of the center rows adjacent to cutout 44 can be read first, or any other desired combination of rows can be read first. After reading the first row, row counter 36 can address the next row.

[0039] At step 50, timing generator 38 can adjust the timing of the read row driver signals based on the distance to the read point. The read point can be either column readout circuit 28A or column readout circuit 28B. Because pixel rows closer to the column readout circuits have a lower RC time constant, rows closer to the read point require less settling time and can therefore be read out faster than rows farther from the read point. If needed, timing generator 38 can apply the readout timing to groups of rows in array 20. For example, groups of three, five, ten, more than five, less than ten, or any other desired number of rows of pixels can all have the same readout timing. For example, when timing generator 38 receives the row corresponding to the next group of rows from row counter 36, the readout timing can be adjusted based on a lookup table that provides readout timing based on a given row.

[0040] At optional step 52, the image signal can be read from the pixel row via column readout circuits 28A and 28B and via data interface 40. If desired, the image signal can be read through the entire bandwidth of data interface 40. For example, it may be desirable to use a non-contiguous frame buffer to store the signal (e.g., the buffer itself cannot handle and store image signals with different timing sequences). By using the full bandwidth of data interface 40, the signals arriving at the frame buffer can all be normalized upon arrival (e.g., all can be data packets of the same size), thus allowing the frame buffer to store the signal. However, step 52 can be omitted if a contiguous frame buffer is used, or if other means are used to ensure that the non-contiguous buffer receives compatible image signals.

[0041] At step 54, the image signal can be read and stored in the frame buffer of the image storage device 42. The image signal can be read through column readout circuits 28A and 28B and through the data interface 40.

[0042] This process can be repeated along line 56 until all rows of array 20 have been read and the associated signals have been stored in the frame buffer. Figure 3 Any desired readout method (e.g., reading all rows in one direction without cuts, reading rows in a mirrored manner with cuts, or reading rows asynchronously with cuts) or other desired methods may be used with Figure 4 The steps described above are used in combination. Figure 5 The graph shown illustrates the effect of variable timing on the frame rate of the image sensor 16.

[0043] like Figure 5As shown, an exemplary relationship between the number of array timing elements and the frame rate of image sensor 16 is given by curve 58. Array timing elements can be groups of rows that receive different timing signals. For example, there may be three groups of rows receiving different timing signals, six groups of rows receiving different timing signals, ten or more groups of rows receiving different timing signals, or eight or fewer groups of rows receiving different timing signals. Generally, array 20 can be divided into any number of elements that receive different timing signals.

[0044] As shown by curve 58, the more array timing elements used, the higher the frame rate (frames per second) of the image sensor. However, most of the increase in the frame rate of image sensor 16 can occur at points a and b. Points a and b can correspond to three elements, six elements, or any other desired number of elements. Therefore, it may be desirable to use multiple timing elements corresponding to points a or b. However, this is merely exemplary. In general, any number of timing elements can be used in array 20. For example, each row in array 20 can have a unique timing sequence, or there can be three or six sets of rows with unique timing sequences in array 20. In this way, the frame rate of image sensor 16 can be increased relative to a fixed readout timing scheme.

[0045] Although the variable timing has been described in conjunction with a global shutter image sensor, this is merely an example. A rolling shutter image sensor can be used with the same variable timing circuitry if desired.

[0046] Various implementations have been described, illustrating an imaging system with variable readout timing circuitry that reduces the frame rate of an image sensor. Various methods of using variable readout timing circuitry have also been described.

[0047] According to one embodiment, the imaging system may include: a pixel array arranged in rows and columns and configured to generate an image signal in response to incident light; a variable timing circuit configured to drive an input to a pixel row in the pixel array at a variable rate; and a column output circuit configured to output the image signal generated by the pixel in the pixel row in response to the input.

[0048] According to some implementation schemes, the variable timing circuit can be configured to select a variable rate for a given row based on the distance of the given row spacing column output circuit.

[0049] According to some implementation schemes, the variable timing circuit can be configured to output a unique rate to at least two sets of rows of the pixel array.

[0050] According to some implementation schemes, the first set of rows in at least two sets of rows may be at a first distance from the column output circuit, the second set of rows in at least two sets of rows may be at a second distance from the column output circuit, the second distance may be greater than the first distance, and the first set of rows may be configured to be read out at a faster rate than the second set of rows.

[0051] According to some implementation schemes, the column output circuit may be located at the top of the pixel array, the first group of rows may include the top row of the array, and the second group of pixels may include the bottom row of the array.

[0052] According to some implementation schemes, the column output circuit may be located at the bottom of the pixel array, the first group of rows may include the bottom row of the array, and the second group of pixels may include the top row of the array.

[0053] According to some implementations, the column output circuit may include a first column output circuit located at the upper end of the pixel array, and the image sensor may also include a second column output circuit located at the lower end of the pixel array.

[0054] According to some implementations, the pixel array may include a notch, image pixels above the notch may be configured to be read out via a first column output circuit, and image pixels below the notch may be configured to be read out via a second column output circuit.

[0055] According to some implementation schemes, the topmost and bottommost pixel rows of the array can be configured to be read out simultaneously, and the rows adjacent to the cutouts in the upper and lower halves of the array can be configured to be read out simultaneously.

[0056] According to some implementations, the top row of pixels in the array and the row in the lower half of the array adjacent to the cutout can be configured to be read out simultaneously, and the bottom row of pixels in the array can be configured to be read out when the row in the upper half of the array adjacent to the cutout is read out.

[0057] According to some implementations, the imaging system may also include a frame buffer configured to store the output of pixel rows, and a data interface interposed between the frame buffer and the column output circuitry.

[0058] According to some implementation schemes, the frame buffer can be a co-located frame buffer.

[0059] According to some implementations, the frame buffer can be a non-co-located frame buffer, and the output of the pixel row can be configured to use the full bandwidth of the data interface through the data interface.

[0060] According to one embodiment, a method may include using row driver circuitry to generate an image signal using an image pixel array comprising rows and columns of image pixels, generating a readout signal with variable timing based on the position of the row in the array, reading out the image signal of the pixel row through column readout circuitry, and storing the image signal in a frame buffer.

[0061] According to some implementation schemes, the method may also include reading the image signal through a data interface after reading the image signal of the pixel row through the column readout circuit.

[0062] According to some implementation schemes, generating readout signals with variable timing may include generating readout signals with unique timing for at least two sets of rows in the array.

[0063] According to some implementation schemes, reading out the image signal may include reading out all lines in an upward or downward direction.

[0064] According to some implementations, reading out the image signal may include reading rows above the cutout toward the first column circuitry in the upper portion of the array, and reading rows below the cutout toward the second column circuitry in the lower portion of the array.

[0065] According to one embodiment, an imaging system may include an image sensor and an image processor. The image sensor may include: an image pixel array including rows and columns of image pixels configured to generate an image signal; a column output circuit configured to output the image signal generated by pixels in a pixel row; a row driver circuit configured to drive the image signal from the row to the column output circuit; a variable timing circuit configured to drive the row driver circuit at a variable rate determined based on the position of a given row in the array; and a data interface receiving the image signal from the column readout circuit. The image processor may include a frame buffer configured to store the image signal as it is read out.

[0066] According to some implementations, the variable timing circuit can be configured to drive the row driver circuit at a unique rate for at least three different groups of rows in the array.

[0067] According to one embodiment, the imaging system includes: a pixel array arranged in rows and columns and configured to generate an image signal in response to incident light; a variable timing circuit configured to drive an input to a pixel row in the pixel array at a variable rate; and a column output circuit configured to output the image signal generated by the pixel in the pixel row in response to the input.

[0068] According to another embodiment, the variable timing circuit is configured to select a variable rate for a given row based on the distance of a given row spacing column output circuit. The variable timing circuit is configured to output a unique rate to at least two sets of rows of the pixel array, wherein a first set of rows is at a first distance from the column output circuit, a second set of rows is at a second distance from the column output circuit, the second distance being greater than the first distance, and the first set of rows is configured to be read out at a faster rate than the second set of rows.

[0069] According to another embodiment, the column output circuit is located at the top of the pixel array, wherein the first group of rows includes the topmost row of the array, and wherein the second group of pixels includes the bottommost row of the array.

[0070] According to another embodiment, the column output circuit is located at the bottom of the pixel array, the first group of rows includes the bottom row of the array, and the second group of pixels includes the top row of the array.

[0071] According to another embodiment, the column output circuit is located at the bottom of the pixel array, the first group of rows includes the bottom row of the array, and the second group of pixels includes the top row of the array.

[0072] According to another embodiment, a variable timing circuit is configured to select a variable rate for a given row based on the distance of a given row-to-column output circuit. The variable timing circuit is configured to output a unique rate to at least two sets of rows in the pixel array. The column output circuit is a first column output circuit located at the top of the pixel array, and the image sensor also includes a second column output circuit located at the bottom of the pixel array. The pixel array includes a notch, above which image pixels are configured to be read out via the first column output circuit, and below which image pixels are configured to be read out via the second column output circuit. The topmost and bottommost pixel rows of the array are configured to be read out simultaneously, and rows adjacent to the notch in the upper and lower halves of the array are configured to be read out simultaneously.

[0073] According to another embodiment, a variable timing circuit is configured to select a variable rate for a given row based on the distance of a given row-to-column output circuit. The variable timing circuit is configured to output a unique rate to at least two sets of rows of the pixel array. The column output circuit is a first column output circuit located at the upper end of the pixel array, and the image sensor also includes a second column output circuit located at the lower end of the pixel array. The pixel array includes a notch, image pixels above the notch are configured to be read out via the first column output circuit, and image pixels below the notch are configured to be read out via the second column output circuit. The uppermost pixel row of the array and rows in the lower half of the array adjacent to the notch are configured to be read out simultaneously, and the lowermost pixel row of the array is configured to be read out when rows in the upper half of the array adjacent to the notch are read out.

[0074] According to one embodiment, a method includes using row driver circuitry to generate an image signal using an image pixel array comprising rows and columns of image pixels, generating a readout signal with variable timing based on the position of rows in the array, reading out the image signal of the pixel rows via column readout circuitry, and storing the image signal in a frame buffer.

[0075] According to another embodiment, generating a readout signal with variable timing includes generating a readout signal with unique timing for at least two sets of rows in the array, and reading out the image signal includes reading all rows in an upward or downward direction.

[0076] According to another embodiment, generating readout signals with variable timing includes generating readout signals with unique timing for at least two sets of rows in the array, and reading out image signals includes reading rows above the cutout toward the first column circuitry in the upper portion of the array, and reading rows below the cutout toward the second column circuitry in the lower portion of the array.

[0077] According to one embodiment, the imaging system may include: an image sensor having an image pixel array comprising rows and columns of image pixels configured to generate an image signal; a column output circuit configured to output the image signal generated by the pixels in the pixel row; a row driver circuit configured to drive the image signal from the row to the column output circuit; a variable timing circuit configured to drive the row driver circuit at a variable rate determined based on the position of a given row in the array; and a data interface receiving the image signal from the column readout circuit. The imaging system may also include an image processor having a frame buffer configured to store the image signal when it is read out.

[0078] The above description is merely illustrative and various modifications can be made to the described implementation scheme. The above implementation scheme can be implemented individually or in any combination.

Claims

1. An imaging system, characterized in that, The imaging system includes: A pixel array, arranged in rows and columns on an upper and lower half separated by cutouts and configured to generate an image signal in response to incident light; Variable timing circuitry, configured to drive input to rows of pixels in the pixel array at a variable rate; and A column output circuit configured to output the image signal generated by the pixels in the pixel row in response to the input; Wherein, the topmost pixel row and the bottommost pixel row of the pixel array are configured to be read out simultaneously, and the rows adjacent to the cut in the upper and lower halves of the pixel array are configured to be read out simultaneously; or, The topmost pixel row of the pixel array is configured to be read when a row adjacent to the cut in the lower half of the pixel array is read, and the bottommost pixel row of the pixel array is configured to be read when a row adjacent to the cut in the upper half of the pixel array is read.

2. The imaging system of claim 1, wherein the variable timing circuit is configured to select the variable rate for a given row based on a given row distance from the column output circuit, wherein the variable timing circuit is configured to output a unique rate to at least two sets of rows of the pixel array, wherein a first set of rows of the at least two sets of rows is at a first distance from the column output circuit, wherein a second set of rows of the at least two sets of rows is at a second distance from the column output circuit, wherein the second distance is greater than the first distance, and wherein the first set of rows is configured to be read out at a faster rate than the second set of rows.

3. The imaging system of claim 2, wherein the column output circuit is located at the top of the pixel array, wherein the first set of rows includes the topmost row of the pixel array, and wherein the second set of rows includes the bottommost row of the pixel array.

4. The imaging system of claim 2, wherein the column output circuit is located at the lower end of the pixel array, wherein the first set of rows includes the bottommost row of the pixel array, and wherein the second set of rows includes the topmost row of the pixel array.

5. The imaging system of claim 3, wherein the variable timing circuit is configured to select the variable rate for a given row based on the distance of the given row from the column output circuit, wherein the variable timing circuit is configured to output a unique rate to at least two sets of rows of the pixel array, wherein the column output circuit is a first column output circuit located at the upper end of the pixel array, the imaging system further comprising: A second column output circuit is located at the lower end of the pixel array, wherein the image pixels above the cut are configured to be read out by the first column output circuit, and wherein the image pixels below the cut are configured to be read out by the second column output circuit.

6. A method for reading out image signals in a variable timing sequence, characterized in that, The method includes: An image signal is generated using an array of image pixels comprising rows and columns of image pixels arranged in an upper and lower half separated by cutouts. Using a row driver circuit, a readout signal with variable timing is generated based on the position of the row in the image pixel array; The image signal of the row of image pixels is read out by the column readout circuit, wherein reading out the image signal includes: When the image signal of the bottommost pixel row of the pixel array is read, the image signal of the topmost pixel row of the pixel array is also read, and simultaneously the image signals of the rows adjacent to the cut in the upper and lower halves of the pixel array are read; or When the image signal of the row adjacent to the cut in the lower half of the pixel array is read, the image signal of the topmost pixel row of the pixel array is read; and when the image signal of the row adjacent to the cut in the upper half of the pixel array is read, the image signal of the bottommost pixel row of the pixel array is read; and The image signal is stored in a frame buffer.

7. The method of claim 6, wherein generating the readout signal with variable timing comprises generating the readout signal with unique timing for at least two sets of rows in the image pixel array.

8. An imaging system, characterized in that, The imaging system includes: Image sensor, the image sensor comprising: An image pixel array comprising rows and columns of image pixels arranged on an upper and lower half separated by slits and configured to generate image signals; A column output circuit configured to output the image signal generated by pixels in rows of the image pixels; A row driver circuit, the row driver circuit being configured to drive the image signal from the row to the column output circuit; A variable timing circuit, configured to drive the row driver circuit at a variable rate determined based on the position of a given row in the image pixel array; and A data interface that receives the image signal from the column output circuit; and an image processor comprising: A frame buffer, configured to store the image signal when the image signal is read out; Wherein, the topmost and bottommost rows of the image pixel array are configured to be read out simultaneously, and rows in the upper and lower halves of the image pixel array adjacent to the cutout are configured to be read out simultaneously; or, wherein the topmost row of the image pixel array is configured to be read out when rows in the lower half of the image pixel array adjacent to the cutout are read out, and the bottommost row of the image pixel array is configured to be read out when rows in the upper half of the image pixel array adjacent to the cutout are read out.

Images