A hardware circuit and program upgrade method for a transmission acquisition module of a phased array radar

Abstract

The present disclosure provides a hardware circuit and program upgrade method for a transmission acquisition module of a phased array radar, wherein the first processor in the hardware circuit of the transmission acquisition module is connected to the second processor, the FLASH memory and the DDR memory respectively. The first processor obtains a program data packet and caches it in the DDR memory, and then stores the program data packet in the DDR memory in the FLASH memory. The first processor reads the FLASH memory, and if the first program upgrade status setting parameter is read to indicate that the upgrade is turned on, the starting address of the first upgrade program data packet is read, the first upgrade program data packet is loaded and run, and after the loading is completed, if the second program upgrade status setting parameter is read to indicate that the upgrade is turned on, the second upgrade program data packet in the FLASH memory is read and written to the second processor, triggering the second processor to run the second upgrade program data packet, which can improve the program upgrade efficiency of the transmission acquisition module.

Description

Technical Field

[0001] The present disclosure relates to the technical field of phased array radars, and in particular to a hardware circuit and a program upgrade method for a transmission and acquisition module of a phased array radar. Background Art

[0002] Active phased array radar includes a large number of transmission and acquisition modules. During the research and development stage of active phased array radar, the transmission and acquisition modules need to be continuously improved and perfected. After the active phased array radar is applied, the programs in the transmission and acquisition modules also need to be maintained and updated.

[0003] Currently, if it is necessary to upgrade the programs of multiple transmission and acquisition modules in an active phased array radar, it is necessary to disassemble the transmission and acquisition modules one by one, connect the simulator to the simulator interface of the processor in the transmission and acquisition module to build a communication link, and then use professional software to upgrade the program of the processor through the communication link. Summary of the invention

[0004] In view of the above problems, the present disclosure provides a hardware circuit and program upgrade method for a transmission acquisition module of a phased array radar that overcomes the above problems or at least partially solves the above problems. The technical solution is as follows:

[0005] A transmission acquisition module hardware circuit of a phased array radar, the transmission acquisition module hardware circuit comprising: a first processor, a second processor, a FLASH memory and a DDR memory;

[0006] The DDR memory is used to cache program data packets acquired by the first processor, wherein the program data packets at least include a first upgrade program data packet, a first factory program data packet, a second upgrade program data packet, and a second factory program data packet;

[0007] The FLASH memory is provided with sectors divided by a preset data mapping relationship, and is used to store the pre-acquired first program upgrade state setting parameter, the target upgrade program storage address data packet, the second program upgrade state setting parameter, and the program data packet cached in the DDR memory in different sectors, wherein the target upgrade program storage address data packet includes a starting address for storing the first upgrade program data packet;

[0008] The first processor is connected to the second processor, the FLASH memory and the DDR memory respectively. The first processor reads the first program upgrade status setting parameter in the FLASH memory. If the first program upgrade status setting parameter indicates to start the upgrade, the first processor reads the target upgrade program storage address data packet in the FLASH memory, and according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet, loads and runs the first upgrade program data packet in the FLASH memory. After the loading is completed, the second program upgrade status setting parameter in the FLASH memory is read. If the second processor upgrade status setting parameter indicates to start the upgrade, the second upgrade program data packet in the FLASH memory is read and written to the second processor, triggering the second processor to run the second upgrade program data packet.

[0009] Optionally, a first preset pin of the first processor is connected to a communication pin of the second processor, at least one second preset pin of the first processor is connected one-to-one to at least one startup setting pin of the second processor, and a third preset pin of the first processor is connected to a reset pin of the second processor.

[0010] When the first processor reads the second program upgrade state setting parameter to indicate that the upgrade is enabled, the first processor sets the at least one startup setting pin of the second processor to a program write position through at least one second preset pin of the first processor, so that the second processor is in a program write mode, and writes the second upgrade program data packet to the second processor through the first preset pin of the first processor and the communication pin of the second processor;

[0011] The first processor sets the at least one startup setting pin of the second processor for program startup through at least one second preset pin of the first processor, so that the second processor is in program startup mode, and resets the second processor through the third preset pin of the first processor and the reset pin of the second processor, so that the second processor runs the second upgrade program data packet after resetting.

[0012] Optionally, the transmission acquisition module hardware circuit further includes: an optical fiber interface circuit, and the first processor is connected to the host computer via the optical fiber interface circuit.

[0013] The first processor obtains the program data packet sent by the host computer through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer in the form of an optical signal into the program data packet in the form of a differential pair digital signal.

[0014] Optionally, the first processor is connected to a first LED circuit, and the first LED circuit is used to display the operating status of the first processor;

[0015] And / or, the second processor is connected to a second LED circuit, and the second LED circuit is used to display the operating status of the second processor.

[0016] A method for program upgrading of a hardware circuit of a transmission and acquisition module of a phased array radar is applied to any of the hardware circuits of the transmission and acquisition module described above, and the method for program upgrading comprises:

[0017] The first processor acquires the program data packet, caches the program data packet in the DDR memory, and after the cache is completed, stores the program data packet in the DDR memory in the FLASH memory;

[0018] The first processor reads the first program upgrade status setting parameter in the FLASH memory, and if the first program upgrade status setting parameter indicates to start the upgrade, reads the target upgrade program storage address data packet in the FLASH memory, and loads and runs the first upgrade program data packet in the FLASH memory according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet. After the loading is completed, reads the second program upgrade status setting parameter in the FLASH memory, and if the second processor upgrade status setting parameter indicates to start the upgrade, reads the second upgrade program data packet in the FLASH memory, writes it to the second processor, and triggers the second processor to run the second upgrade program data packet.

[0019] Optionally, the program upgrade method further includes:

[0020] When the first processor reads the first program upgrade status setting parameter and finds that the first program upgrade status setting parameter does not indicate starting the upgrade, the first processor loads and runs the first factory program data package in the FLASH memory, and after the loading is completed, reads the second program upgrade status setting parameter in the FLASH memory.

[0021] Optionally, the program upgrade method further includes:

[0022] When the first processor reads the second program upgrade status setting parameter and finds that the upgrade is not started, the first processor reads the second factory program data package in the FLASH memory, writes it into the second processor, and triggers the second processor to run the second factory program data package.

[0023] Optionally, the program upgrade method further includes:

[0024] When the first processor reads the second program upgrade state setting parameter to indicate that the upgrade is enabled, the first processor sets the at least one startup setting pin of the second processor to a program write position through at least one second preset pin of the first processor, so that the second processor is in a program write mode, and writes the second upgrade program data packet to the second processor through the first preset pin of the first processor and the communication pin of the second processor;

[0025] The first processor sets the at least one startup setting pin of the second processor for program startup through at least one second preset pin of the first processor, so that the second processor is in program startup mode, and resets the second processor through the third preset pin of the first processor and the reset pin of the second processor, so that the second processor runs the second upgrade program data packet after resetting.

[0026] Optionally, the transmission acquisition module hardware circuit further includes: an optical fiber interface circuit, and the first processor is connected to the host computer via the optical fiber interface circuit.

[0027] The first processor obtains the program data packet, including:

[0028] The first processor obtains the program data packet sent by the host computer through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer in the form of an optical signal into the program data packet in the form of a differential pair digital signal.

[0029] Optionally, if the transmission and acquisition module hardware circuit further includes a first LED circuit connected to the first processor, the first LED circuit is used to display the operating status of the first processor;

[0030] If the hardware circuit of the transmission and acquisition module further includes a second LED circuit connected to the second processor, the second LED circuit is used to display the operating status of the second processor.

[0031] By means of the above technical scheme, the present disclosure provides a hardware circuit and program upgrade method of a transmission acquisition module of a phased array radar, wherein the hardware circuit of the transmission acquisition module includes a first processor, a second processor, a FLASH memory and a DDR memory, and the first processor is respectively connected to the second processor, the FLASH memory and the DDR memory. The first processor obtains a program data packet and caches it in the DDR memory. After the cache is completed, the program data packet in the DDR memory is stored in the FLASH memory. The first processor reads the first program upgrade status setting parameter in the FLASH memory. If it indicates to start the upgrade, the starting address of the first upgrade program data packet in the target upgrade program storage address data packet in the FLASH memory is read, the first upgrade program data packet in the FLASH memory is loaded and run, and after the loading is completed, the second program upgrade status setting parameter in the FLASH memory is read. If it indicates to start the upgrade, the second upgrade program data packet in the FLASH memory is read and written to the second processor, triggering the second processor to run the second upgrade program data packet. The present disclosure improves the program upgrade efficiency of the transmission acquisition module by controlling itself and the second processor to perform program upgrades through the first processor.

[0032] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0034] Figure 1 A schematic diagram of the structure of the hardware circuit of the transmission and acquisition module of the phased array radar provided in an embodiment of the present disclosure is shown;

[0035] Figure 2 A schematic diagram showing sectors of a FLASH memory using a preset data mapping relationship provided in an embodiment of the present disclosure is shown;

[0036] Figure 3 A circuit schematic diagram of a DDR memory provided by an embodiment of the present disclosure is shown;

[0037] Figure 4 Another circuit schematic diagram of a DDR memory provided by an embodiment of the present disclosure is shown;

[0038] Figure 5 A schematic diagram of a control circuit for controlling a DDR memory using an FPGA according to an embodiment of the present disclosure is shown;

[0039] Figure 6 A circuit schematic diagram of a FLASH memory provided by an embodiment of the present disclosure is shown;

[0040] Figure 7 A schematic diagram of a control circuit for controlling a FLASH memory using an FPGA according to an embodiment of the present disclosure is shown;

[0041] Figure 8 The schematic diagram of the circuit of the STM32 microcontroller provided by the embodiment of the present disclosure is shown;

[0042] Fig. 9 A schematic diagram of the structure of optical fiber communication between a first processor and a host computer provided in an embodiment of the present disclosure is shown;

[0043] Fig.10 A circuit schematic diagram of a fiber optic interface circuit provided by an embodiment of the present disclosure is shown;

[0044] Fig.11 A circuit schematic diagram of the connection between BANK113 and the optical fiber interface circuit in the FPGA provided by the embodiment of the present disclosure is shown;

[0045] Fig.12 A schematic diagram showing a structure in which a first LED circuit and a second LED circuit provided by an embodiment of the present disclosure are respectively connected to a first processor and a second processor in an emission collection module;

[0046] Fig.13 A circuit schematic diagram of a first LED circuit provided by an embodiment of the present disclosure is shown;

[0047] Fig.14 A circuit schematic diagram of a second LED circuit provided by an embodiment of the present disclosure is shown;

[0048] Fig.15 A circuit schematic diagram of a first JTAG download circuit provided by an embodiment of the present disclosure is shown;

[0049] Fig.16 A circuit schematic diagram of a second JTAG download circuit provided by an embodiment of the present disclosure is shown;

[0050] Fig.17 A schematic diagram showing an implementation of a method for program upgrading a hardware circuit of a transmission acquisition module of a phased array radar provided by an embodiment of the present disclosure is shown;

[0051] Fig.18Another schematic diagram of an implementation of a method for upgrading a program of a hardware circuit of a transmission and acquisition module of a phased array radar provided in an embodiment of the present disclosure is shown;

[0052] Fig.19 A schematic diagram showing another implementation of a method for program upgrading of a hardware circuit of a transmission acquisition module of a phased array radar provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0053] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0054] like Figure 1 As shown, the hardware circuit of the transmission acquisition module of the phased array radar provided in the embodiment of the present disclosure includes: a first processor 100, a second processor 200, a FLASH memory 300 and a DDR memory 400.

[0055] The first processor 100 and the second processor 200 are programmable chips, the first processor 100 may be an FPGA (Field Programmable Gate Array), and the second processor 200 may be an STM32 single-chip microcomputer.

[0056] The FLASH memory 300 is also called a flash memory. The FLASH memory 300 has a fast read and write speed and data is not easily lost.

[0057] The DDR memory 400 (Double Date Rate Synchronous Dynamic Random Access Memory) generally refers to a DDR SDRAM memory. The DDR memory 400 selected in the embodiment of the present disclosure may specifically be DDR3.

[0058] The DDR memory 400 is used to cache program data packets acquired by the first processor 100 , and the program data packets at least include a first upgrade program data packet, a first factory program data packet, a second upgrade program data packet, and a second factory program data packet.

[0059] The first upgrade program data packet is used to upgrade the program of the first processor 100. The data size of the first upgrade program data packet can be determined according to the actual program upgrade requirements of the first processor 100. The first factory program data packet is used to restore the first processor 100 to the factory default state. The data size of the first factory program data packet is usually fixed.

[0060] The second upgrade program data packet is used to upgrade the program of the second processor 200. The data size of the second upgrade program data packet can be determined according to the actual program upgrade requirements of the second processor 200. The second factory program data packet is used to restore the factory default state of the second processor 200. The data size of the second factory program data packet is usually fixed.

[0061] The FLASH memory 300 is provided with sectors divided by a preset data mapping relationship, and is used to store pre-acquired first program upgrade status setting parameters, target upgrade program storage address data packets, second program upgrade status setting parameters and program data packets cached in the DDR memory 400 in different sectors, wherein the target upgrade program storage address data packet includes a starting address for storing the first upgrade program data packet.

[0062] Optionally, the sectors divided by the preset data mapping relationship may correspond to the following from low to high in order: the first program upgrade state setting parameter, the target upgrade program storage address data packet, the first factory program data packet, the first upgrade program data packet, the second program upgrade state setting parameter, the second factory program data packet and the second upgrade program data packet. Optionally, the sectors divided by the preset data mapping relationship of the FLASH memory 300 may correspond to the following from low to high in order: the first program upgrade state setting parameter, the target upgrade program storage address data packet, the first factory program data packet, the first upgrade program data packet, the second program upgrade state setting parameter, the second factory program data packet and the second upgrade program data packet. Figure 2 As shown. Figure 2 As shown, the 0th sector stores a pre-acquired first processor 100 program upgrade switch data packet, wherein the first program upgrade state setting parameter is located in the first processor 100 program upgrade switch data packet. The 1st sector stores a pre-acquired target upgrade program storage address data packet. The 2nd sector to the Mth sector stores a first factory program data packet. The M+1th sector to the Nth sector stores a first upgrade program data packet. The N+1th sector stores a pre-acquired second processor 200 program upgrade switch data packet, wherein the second program upgrade state setting parameter is located in the second processor 200 program upgrade switch data packet. The N+2th sector to the Pth sector stores a second factory program data packet. The P+1th sector to the Qth sector stores a second upgrade program data packet.

[0063] Among them, the first processor 100 program upgrade switch data packet is a custom data combination, and the data combination of the first processor 100 program upgrade switch data packet can be shown in Table 1. The first processor 100 program upgrade switch data packet occupies the 0th sector alone. Optionally, when the first program upgrade status setting parameter is 0x000000BB, it indicates that the upgrade is turned on. The first program upgrade status setting parameter is usually 0 when the upgrade is not indicated to be turned on. The FLASH data bus bandwidth is usually matched with the characteristics of the FLASH memory 300. For an 8-bit FLASH memory 300, the FLASH data bus bandwidth can be set to 0x11111111; for a 16-bit FLASH memory 300, the FLASH data bus bandwidth can be set to 0x22222222; for a 32-bit FLASH, the FLASH data bus bandwidth can be set to 0x44444444. Under normal circumstances, since the FLASH memory 300 in the transmission acquisition module is 16 bits wide, the FLASH data bus bandwidth is set to 0x22222222. For the redundant space in sector 0, all 0xFFFFFFFF can be written.

[0064] Table 1

[0065]

[0066] The target upgrade program storage address data packet is a custom data combination, and the data combination of the target upgrade program storage address data packet can be shown in Table 2. The target upgrade program storage address data packet includes the starting address for storing the first upgrade program data packet. For the redundant space in the first sector, 0xFFFFFFFF can be written in full.

[0067] Table 2

[0068]

[0069] The first factory program data package and the first upgrade program data package may be stored in the sector in a “.mcs” format.

[0070] Among them, the second processor 200 program upgrade switch data packet is a custom data combination, and the data combination of the second processor 200 program upgrade switch data packet can be shown in Table 3. The second processor 200 program upgrade switch data packet occupies the N+1 sector alone. Optionally, when the second program upgrade status setting parameter is 0x000000AA, it indicates that the upgrade is turned on. The second program upgrade status setting parameter is usually 0 when the upgrade is not indicated to be turned on. For the redundant space in the N+1 sector, 0xFFFFFFFF can be written in full.

[0071] Table 3

[0072]

[0073] The second factory program data package and the second upgrade program data package may be stored in the sector in a ".hex" format.

[0074] It is understandable that, in addition to the above-mentioned sectors 0 to Q, there may be remaining storage space in the FLASH memory 300. The disclosed embodiment may store other versions of program data packets and other data in the remaining storage space. In the case where other versions of program data packets are stored in the remaining storage space, different versions of program data packets may be selected by modifying the starting address of the startup program in the target upgrade program storage address data packet, which is conducive to the time-sharing operation of multiple versions of program data packets and the performance differences of different versions of program data packets are compared. Of course, when the remaining storage space does not store other versions of program data packets and other data, all 0xFFFFFFFF may be written to the remaining storage space.

[0075] The first processor 100 is connected to the second processor 200, the FLASH memory 300 and the DDR memory 400 respectively. The first processor 100 reads the first program upgrade status setting parameter in the FLASH memory 300. If the first program upgrade status setting parameter indicates to start the upgrade, the target upgrade program storage address data packet in the FLASH memory 300 is read, and according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet, the first upgrade program data packet in the FLASH memory 300 is loaded and run. After the loading is completed, the second program upgrade status setting parameter in the FLASH memory 300 is read. If the upgrade status setting parameter of the second processor 200 indicates to start the upgrade, the second upgrade program data packet in the FLASH memory 300 is read and written into the second processor 200, triggering the second processor 200 to run the second upgrade program data packet.

[0076] Optionally, the circuit of DDR memory 400 can be as follows Figure 3 As shown, it can also be Figure 4 When the first processor 100 is an FPGA, the control circuit of the FPGA controlling the DDR memory 400 may be as follows. Figure 5 shown.

[0077] Optionally, the circuit of the FLASH memory 300 may be as follows Figure 6 When the first processor 100 is an FPGA, the control circuit of the FPGA controlling the FLASH memory 300 may be as follows. Figure 7As shown. It can be understood that the storage capacity of the FLASH memory 300 can at least accommodate the pre-acquired first program upgrade state setting parameter, the target upgrade program storage address data packet, the second program upgrade state setting parameter and the program data packet cached in the DDR memory 400. Optionally, the storage capacity of the FLASH memory 300 selected in the embodiment of the present disclosure can be 512MB. Optionally, the embodiment of the present disclosure can select a FLASH memory 300 that can be read and written in parallel. Figure 6 As shown, the model of the FLASH memory 300 may be S29GL512S10DHI020. By selecting the FLASH memory 300 capable of parallel reading and writing, the reading and writing speed can be increased and the time consumed for program upgrade can be reduced.

[0078] Optionally, the configuration file length of the FPGA selected in the embodiment of the present disclosure may be 149880032 bits. The program memory size of the STM32 microcontroller selected in the embodiment of the present disclosure may be 512KB.

[0079] Optionally, when the second processor 200 is an STM32 single-chip microcomputer, the circuit of the STM32 single-chip microcomputer can be as follows: Figure 8 shown.

[0080] Optionally, the first preset pin of the first processor 100 is connected to the communication pin of the second processor 200, at least one second preset pin of the first processor 100 is connected one-to-one to at least one startup setting pin of the second processor 200, and the third preset pin of the first processor 100 is connected to the reset pin of the second processor 200.

[0081] In order to facilitate intuitive understanding, Figure 7 and Figure 8 To illustrate: The first preset pin of the first processor 100 can be the R26 pin and the R27 pin of U17_6 in the BANK15 of the FPGA. The communication pin of the second processor 200 can be the serial communication pins PA9 and PA10 of USART1. The FPGA communicates using the RS232 serial port protocol by connecting the serial port of the STM32 microcontroller. The startup setting pin of the second processor 200 can be the BOOT pin of U46 in the STM32 microcontroller, and the BOOT pin includes the BOOT0 pin and the BOOT1 pin. The second preset pin of the first processor 100 can be the T26 pin and the T25 pin of U17_6 in the BANK15 of the FPGA. The third preset pin of the first processor 100 can be the U25 pin of U17_6 in the BANK15 of the FPGA. The reset pin of the second processor 200 can be the STM32_RESET# pin in the STM32 microcontroller.

[0082] When the first processor 100 reads the second program upgrade status setting parameter to indicate that the upgrade is started, it sets the program write of at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in program write mode, and writes the second upgrade program data packet to the second processor 200 through the first preset pin of the first processor 100 and the communication pin of the second processor 200.

[0083] The first processor 100 sets the program startup position of at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in the program startup mode, and resets the second processor 200 through the third preset pin of the first processor 100 and the reset pin of the second processor 200, so that the second processor 200 runs the second upgrade program data packet after resetting.

[0084] Optional, such as Fig. 9 As shown, the first processor 100 can communicate with the host computer 500 via an optical fiber. Optionally, the optical fiber can be a 10G rate optical fiber.

[0085] Optionally, the transmission acquisition module hardware circuit further includes: an optical fiber interface circuit, and the first processor 100 is connected to the host computer 500 via the optical fiber interface circuit.

[0086] The first processor 100 obtains the program data packet sent by the host computer 500 through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer 500 in the form of an optical signal into a program data packet in the form of a differential pair digital signal.

[0087] Optionally, the fiber optic interface circuit can be Fig.10 As shown, in the case where the first processor 100 is an FPGA, the connection part between BANK113 in the FPGA and the optical fiber interface circuit is as shown in FIG. Fig.11 As shown. Combined Fig.10 and Fig.11To explain: The host computer 500 is connected to U27 via optical fiber, and U27 converts the high-speed optical signal into high-speed differential pair digital signals SFP1+_RX+ and SFP1+_RX-, and the SFP1+_RX+ pin and SFP1+_RX- pin are connected to BANK113 of FPGA. U27 can also convert the high-speed differential pair digital signals SFP1+_RX+ and SFP1+_RX- into high-speed optical signals and send them to the host computer 500. BANK113 of FPGA is a dedicated serial high-speed transceiver circuit that supports 10G optical fiber communication. It should be noted that the communication between the optical fiber interface circuit and the host computer 500 is long-distance communication and is transmitted by optical signals. The communication between the optical fiber interface circuit and the first processor 100 is short-distance communication and is transmitted by differential pair digital signals. Both optical signals and differential pair digital signals have strong anti-interference capabilities against electromagnetic interference, which can reduce the impact of the strong electromagnetic interference of the radar itself.

[0088] Optionally, the first processor 100 is connected to a first LED circuit, and the first LED circuit is used to display the operating status of the first processor 100 .

[0089] Optionally, the second processor 200 is connected to a second LED circuit, and the second LED circuit is used to display the operating status of the second processor 200 .

[0090] Among them, combined Figure 1 As shown, Fig.12 It is a schematic diagram showing that the first LED circuit 600 and the second LED circuit 700 are respectively connected to the first processor 100 and the second processor 200 in the emission collection module.

[0091] Optionally, the first LED circuit 600 may be specifically as follows: Fig.13 Optionally, the second LED circuit 700 may be specifically as follows Fig.14 shown.

[0092] Optionally, the first processor 100 may further include a first JTAG download circuit. The second processor 200 may further include a second JTAG download circuit. Optionally, the first JTAG download circuit may be as follows: Fig.15 The second JTAG download circuit can be as follows Fig.16 It is understandable that the embodiment of the present disclosure can also download the program to the processor for execution through the JTAG download circuit.

[0093] In order to realize efficient remote upgrade of the transmission and acquisition module of the phased array radar, the embodiment of the present disclosure provides a program upgrade method for the hardware circuit of the transmission and acquisition module of the phased array radar, which is applied to the hardware circuit of the transmission and acquisition module. Fig.17As shown, a schematic diagram of an implementation method of a program upgrade method of a hardware circuit of a transmission acquisition module of a phased array radar provided in an embodiment of the present disclosure, the program upgrade method includes:

[0094] S100: The first processor 100 obtains a program data packet.

[0095] Optionally, the transmission acquisition module hardware circuit may further include: an optical fiber interface circuit, and the first processor 100 is connected to the host computer 500 via the optical fiber interface circuit.

[0096] The first processor 100 obtains the program data packet sent by the host computer 500 through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer 500 in the form of an optical signal into a program data packet in the form of a differential pair digital signal.

[0097] The embodiment of the present disclosure uses optical fiber communication between the host computer 500 and the first processor 100 to transmit various radar data and instructions between the host computer 500 and the first processor 100, and assist in remote program upgrades of the first processor 100 and the second processor 200 in the emission acquisition module. The data transmission speed is fast and is not limited by the transmission distance, which can significantly improve the efficiency of program upgrades for the first processor 100 and the second processor 200 in the emission acquisition module.

[0098] S101, cache the program data packet into the DDR memory 400, and after the cache is completed, execute step S102.

[0099] Optionally, the embodiment of the present disclosure can determine that the program data packet is cached in the DDR memory 400 after determining that the communication between the first processor 100 and the host computer 500 is completed. It is understandable that the communication between the host computer 500 and the first processor 100 is in accordance with a custom communication protocol. According to the frame header and frame tail set in the communication protocol, the first processor 100 can determine that the communication is completed when receiving the frame tail. It is understandable that after determining that the communication related to the program data packet is completed, the first processor 100 can determine that the program data packet has been completely cached in the DDR memory 400.

[0100] S102 , storing the program data packet in the DDR memory 400 into the FLASH memory 300 .

[0101] Optionally, the first processor 100 may transfer the program data packet in the DDR memory 400 to the FLASH memory 300 , or may copy the program data packet in the DDR memory 400 to the FLASH memory 300 .

[0102] Optionally, after step S102, the first processor 100 performs a CRC check on the first upgrade program data packet in the FLASH memory 300 to obtain a first check result. When the first check result is passed, the first processor 100 sets the first program upgrade state setting parameter to indicate that the upgrade is enabled. It is understandable that the first processor 100 may set the first program upgrade state setting parameter not to indicate that the upgrade is enabled when the first check result is not passed.

[0103] Optionally, after step S102, the first processor 100 performs a CRC check on the second upgrade program data packet in the FLASH memory 300 to obtain a second check result. When the second check result is passed, the first processor 100 sets the second program upgrade state setting parameter to indicate that the upgrade is enabled. It is understandable that the first processor 100 may set the second program upgrade state setting parameter not to indicate that the upgrade is enabled when the second check result is not passed.

[0104] S103, the first processor 100 reads the first program upgrade status setting parameter in the FLASH memory 300, and if the first program upgrade status setting parameter indicates that the upgrade is enabled, step S104 is executed.

[0105] The first processor 100 can read the FLASH memory 300 from the low bit to the high bit in the sectors divided according to the preset data mapping relationship.

[0106] S104 , reading the target upgrade program storage address data packet in the FLASH memory 300 .

[0107] S105 , according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet, load and run the first upgrade program data packet in the FLASH memory 300 , and after the loading is completed, execute step S106 .

[0108] based on Figure 2 As shown, the FLASH memory 300 is divided into sectors using a preset data mapping relationship. After reading the starting address of the first upgrade program data packet, the first processor 100 can locate the starting sector where the first upgrade program data packet is stored in the FLASH memory 300: the M+1th sector, thereby skipping the 2nd sector to the Mth sector and directly reading the first upgrade program data packet from the M+1th sector.

[0109] Optional, such as Fig.18 As shown, another implementation scheme of the program upgrade method of the transmission acquisition module hardware circuit of the phased array radar provided in the embodiment of the present disclosure is shown, and the program upgrade method also includes:

[0110] S108. When the first processor 100 reads the first program upgrade status setting parameter and finds that the upgrade is not started, the first processor 100 loads and runs the first factory program data package in the FLASH memory 300. After the loading is completed, the first processor 100 executes step S106.

[0111] It is understandable that, when the first processor 100 reads the first program upgrade status setting parameter and does not indicate starting the upgrade, it can continue to read the first factory program data packet from the low bit to the high bit direction according to the sectors divided by the preset data mapping relationship.

[0112] S106, reading the second program upgrade status setting parameter in the FLASH memory 300, if the upgrade status setting parameter of the second processor 200 indicates to start the upgrade, executing step S107.

[0113] S107 , reading the second upgrade program data packet in the FLASH memory 300 , writing it into the second processor 200 , and triggering the second processor 200 to run the second upgrade program data packet.

[0114] Since the data size of the second factory program data packet is usually fixed, and based on the preset data mapping relationship, in the FLASH memory 300, the sector where the second upgrade program data packet is stored is higher than the sector where the second factory program data packet is stored, and the sector corresponding to the end address of the second factory program data packet is continuous with the sector corresponding to the start address of the second upgrade program data packet, the start position where the second upgrade program data packet is stored in the FLASH memory 300 is fixed. The first processor 100 can read the second upgrade program data packet according to the start position of the second upgrade program data packet.

[0115] Optionally, when the first processor 100 reads the second program upgrade state setting parameter to indicate that the upgrade is turned on, the first processor 100 performs a program write setting on at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in a program write mode, and writes the second upgrade program data packet to the second processor 200 through the first preset pin of the first processor 100 and the communication pin of the second processor 200. The first processor 100 performs a program start setting on at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in a program start mode, and resets the second processor 200 through the third preset pin of the first processor 100 and the reset pin of the second processor 200, so that the second processor 200 runs the second upgrade program data packet after resetting.

[0116] Combination Figure 7 and Figure 8, when the FPGA reads the second program upgrade status setting parameter to indicate that the upgrade is turned on, it can set the BOOT1 of the STM32 microcontroller to 1 to perform program write setting, so that the second processor 200 is in program write mode, and the FPGA writes the second upgrade program data packet into the STM32 microcontroller through the serial port connected to the STM32 microcontroller. Then the FPGA sets the BOOT1 of the STM32 microcontroller to 0 to perform program start setting, so that the STM32 microcontroller is in program start mode, and then resets the STM32 microcontroller, so that the STM32 microcontroller runs the second upgrade program data packet after resetting.

[0117] Optional, such as Fig.19 As shown, another implementation scheme of the program upgrade method of the transmission acquisition module hardware circuit of the phased array radar provided in the embodiment of the present disclosure is shown, and the program upgrade method also includes:

[0118] S109, when the first processor 100 reads the second program upgrade status setting parameter and does not indicate starting the upgrade, the first processor 100 reads the second factory program data package in the FLASH memory 300, writes it into the second processor 200, and triggers the second processor 200 to run the second factory program data package.

[0119] Optionally, when the first processor 100 reads that the second program upgrade state setting parameter does not indicate that the upgrade is turned on, the first processor 100 performs a program write setting on at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in a program write mode, and writes the second factory program data packet to the second processor 200 through the first preset pin of the first processor 100 and the communication pin of the second processor 200. The first processor 100 performs a program start setting on at least one startup setting pin of the second processor 200 through at least one second preset pin of the first processor 100, so that the second processor 200 is in a program start mode, and resets the second processor 200 through the third preset pin of the first processor 100 and the reset pin of the second processor 200, so that the second processor 200 runs the second factory program data packet after resetting.

[0120] Combination Figure 7 and Figure 8, when the FPGA reads the second program upgrade status setting parameter as not indicating to start the upgrade, it can set the BOOT1 of the STM32 microcontroller to 1 to perform program write setting, so that the second processor 200 is in program write mode, and the FPGA writes the second factory program data packet into the STM32 microcontroller through the serial port connected to the STM32 microcontroller. Then the FPGA sets the BOOT1 of the STM32 microcontroller to 0 to perform program start setting, so that the STM32 microcontroller is in program start mode, and then resets the STM32 microcontroller, so that the STM32 microcontroller runs the second factory program data packet after resetting.

[0121] Optionally, if the hardware circuit of the transmission acquisition module further includes a first LED circuit 600 connected to the first processor 100, the first LED circuit 600 is used to display the operating status of the first processor 100. If the hardware circuit of the transmission acquisition module further includes a second LED circuit 700 connected to the second processor 200, the second LED circuit 700 is used to display the operating status of the second processor 200.

[0122] The present disclosure provides a method for program upgrading of a hardware circuit of a transmitting and collecting module of a phased array radar. The hardware circuit of the transmitting and collecting module includes a first processor 100, a second processor 200, a FLASH memory 300 and a DDR memory 400. The first processor 100 is connected to the second processor 200, the FLASH memory 300 and the DDR memory 400 respectively. The first processor 100 obtains a program data packet and caches it in the DDR memory 400. After the cache is completed, the program data packet in the DDR memory 400 is stored in the FLASH memory 300. The first processor 100 reads a first program upgrade state setting parameter in the FLASH memory 300. If it indicates to start the upgrade, the first processor 100 reads the starting address of the first upgrade program data packet in the target upgrade program storage address data packet in the FLASH memory 300, loads the first upgrade program data packet in the FLASH memory 300 and runs it. After the loading is completed, the second program upgrade state setting parameter in the FLASH memory 300 is read. If it indicates to start the upgrade, the second upgrade program data packet in the FLASH memory 300 is read and written into the second processor 200, triggering the second processor 200 to run the second upgrade program data packet. The present disclosure improves the program upgrade efficiency of the transmission acquisition module by controlling the first processor 100 itself and the second processor 200 to perform program upgrade.

[0123] In the description of the present disclosure, it should be understood that the terms "up", "down", "front", "back", "left" and "right" etc. indicating directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the positions or elements referred to must have specific directions, be constructed and operate in specific directions. Therefore, they should not be understood as limitations of the present disclosure.

[0124] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0125] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0126] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hardware circuit of a transmission and acquisition module of a phased array radar, characterized in that: The hardware circuit of the transmission acquisition module includes: a first processor, a second processor, a FLASH memory and a DDR memory; The DDR memory is used to cache program data packets acquired by the first processor, wherein the program data packets at least include a first upgrade program data packet, a first factory program data packet, a second upgrade program data packet, and a second factory program data packet; The FLASH memory is provided with sectors divided by a preset data mapping relationship, and is used to store the pre-acquired first program upgrade state setting parameter, the target upgrade program storage address data packet, the second program upgrade state setting parameter, and the program data packet cached in the DDR memory in different sectors, wherein the target upgrade program storage address data packet includes a starting address for storing the first upgrade program data packet; The first processor is connected to the second processor, the FLASH memory and the DDR memory respectively. The first processor reads the first program upgrade status setting parameter in the FLASH memory. If the first program upgrade status setting parameter indicates to start the upgrade, the first processor reads the target upgrade program storage address data packet in the FLASH memory, and according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet, loads and runs the first upgrade program data packet in the FLASH memory. After the loading is completed, the second program upgrade status setting parameter in the FLASH memory is read. If the second processor upgrade status setting parameter indicates to start the upgrade, the second upgrade program data packet in the FLASH memory is read and written to the second processor, triggering the second processor to run the second upgrade program data packet.

2. The transmission acquisition module hardware circuit according to claim 1, characterized in that: A first preset pin of the first processor is connected to a communication pin of the second processor, at least one second preset pin of the first processor is connected one-to-one to at least one startup setting pin of the second processor, and a third preset pin of the first processor is connected to a reset pin of the second processor. When the first processor reads the second program upgrade state setting parameter to indicate that the upgrade is enabled, the first processor sets the at least one startup setting pin of the second processor to a program write position through at least one second preset pin of the first processor, so that the second processor is in a program write mode, and writes the second upgrade program data packet to the second processor through the first preset pin of the first processor and the communication pin of the second processor; The first processor sets the at least one startup setting pin of the second processor for program startup through at least one second preset pin of the first processor, so that the second processor is in program startup mode, and resets the second processor through the third preset pin of the first processor and the reset pin of the second processor, so that the second processor runs the second upgrade program data packet after resetting.

3. The transmission acquisition module hardware circuit according to claim 1, characterized in that: The hardware circuit of the transmission acquisition module also includes: an optical fiber interface circuit, and the first processor is connected to the host computer through the optical fiber interface circuit. The first processor obtains the program data packet sent by the host computer through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer in the form of an optical signal into the program data packet in the form of a differential pair digital signal.

4. The transmission acquisition module hardware circuit according to claim 1, characterized in that: The first processor is connected to a first LED circuit, and the first LED circuit is used to display the operating status of the first processor; And / or, the second processor is connected to a second LED circuit, and the second LED circuit is used to display the operating status of the second processor.

5. A method for program upgrading of a hardware circuit of a transmitting and collecting module of a phased array radar, characterized in that: Applied to the transmission acquisition module hardware circuit described in any one of claims 1 to 4, the program upgrade method comprises: The first processor acquires the program data packet, caches the program data packet in the DDR memory, and after the cache is completed, stores the program data packet in the DDR memory in the FLASH memory; The first processor reads the first program upgrade status setting parameter in the FLASH memory, and if the first program upgrade status setting parameter indicates to start the upgrade, reads the target upgrade program storage address data packet in the FLASH memory, and loads and runs the first upgrade program data packet in the FLASH memory according to the starting address of the first upgrade program data packet in the target upgrade program storage address data packet. After the loading is completed, reads the second program upgrade status setting parameter in the FLASH memory, and if the second processor upgrade status setting parameter indicates to start the upgrade, reads the second upgrade program data packet in the FLASH memory, writes it to the second processor, and triggers the second processor to run the second upgrade program data packet.

6. The program upgrade method according to claim 5, characterized in that: Also includes: When the first processor reads the first program upgrade status setting parameter and finds that the first program upgrade status setting parameter does not indicate starting the upgrade, the first processor loads and runs the first factory program data packet in the FLASH memory, and after the loading is completed, reads the second program upgrade status setting parameter in the FLASH memory.

7. The program upgrade method according to claim 5, characterized in that: Also includes: When the first processor reads the second program upgrade status setting parameter and finds that the upgrade is not started, the first processor reads the second factory program data package in the FLASH memory, writes the data package into the second processor, and triggers the second processor to run the second factory program data package.

8. The program upgrade method according to claim 5, characterized in that: Also includes: When the first processor reads the second program upgrade state setting parameter to indicate that the upgrade is enabled, the first processor sets the at least one startup setting pin of the second processor to a program write position through at least one second preset pin of the first processor, so that the second processor is in a program write mode, and writes the second upgrade program data packet to the second processor through the first preset pin of the first processor and the communication pin of the second processor; The first processor sets the at least one startup setting pin of the second processor for program startup through at least one second preset pin of the first processor, so that the second processor is in program startup mode, and resets the second processor through the third preset pin of the first processor and the reset pin of the second processor, so that the second processor runs the second upgrade program data packet after resetting.

9. The program upgrade method according to claim 5, characterized in that: The hardware circuit of the transmission acquisition module also includes: an optical fiber interface circuit, and the first processor is connected to the host computer through the optical fiber interface circuit. The first processor obtains the program data packet, including: The first processor obtains the program data packet sent by the host computer through the optical fiber interface circuit, wherein the optical fiber interface circuit converts the program data packet received from the host computer in the form of an optical signal into the program data packet in the form of a differential pair digital signal.

10. The program upgrade method according to claim 5, characterized in that: If the transmission and acquisition module hardware circuit further includes a first LED circuit connected to the first processor, the first LED circuit is used to display the operating status of the first processor; If the hardware circuit of the transmission and acquisition module further includes a second LED circuit connected to the second processor, the second LED circuit is used to display the operating status of the second processor.

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