Display device

Abstract

A display device is provided, the display device including: a substrate; first, second, and third data lines extending in a first direction on the substrate and disposed adjacent along a second direction crossing the first direction; a semiconductor layer disposed on the first, second, and third data lines; a first insulating layer disposed on the semiconductor layer; first, second, and third lower storage electrodes disposed on the first insulating layer and arranged adjacent along the first direction; a second insulating layer disposed on the first, second, and third lower storage electrodes; a first scan line extending in the second direction on the second insulating layer; a first pixel connected to the first scan line and the first data line; a second pixel connected to the first scan line and the second data line; and a third pixel connected to the first scan line and the third data line.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0057650, filed on May 14, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a display device. Background Technology

[0003] Display devices display images, and among display devices, light-emitting diode (LED) displays have received attention.

[0004] Light-emitting diode (LED) displays are self-emissive, and unlike liquid crystal displays (LCDs), they do not require a separate light source (i.e., backlight), allowing for reduced thickness and weight. Furthermore, LED displays exhibit high-quality characteristics such as low power consumption, high brightness, and fast response time.

[0005] Typically, a light-emitting diode (LED) display comprises multiple pixels, and each pixel includes multiple transistors and light-emitting elements. These transistors are connected to scan lines and data lines, and can transmit drive current to the light-emitting elements. Data lines are generally stacked with other wiring or electrodes to form parasitic capacitors, which can delay signal transmission or cause crosstalk.

[0006] The information disclosed in this background section is only for understanding the background technology of the present invention concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] The device constructed according to an exemplary embodiment of the invention can provide a display device with improved display quality by reducing the capacitance of parasitic capacitors formed by wiring (such as scan lines that intersect with data lines) superimposed on data lines.

[0008] In addition, the present invention will provide a display device capable of improving display quality by reducing the capacitance of a parasitic capacitor formed by stacking a common electrode and a data line completely disposed on a substrate.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0010] A display device according to an exemplary embodiment includes: a substrate; a first data line, a second data line, and a third data line extending on the substrate in a first direction and configured to be adjacent to each other along a second direction intersecting the first direction; a semiconductor layer disposed on the first data line, the second data line, and the third data line; a first insulating layer disposed on the semiconductor layer; a first lower storage electrode, a second lower storage electrode, and a third lower storage electrode disposed on the first insulating layer and arranged to be adjacent to each other along the first direction; a second insulating layer disposed on the first lower storage electrode, the second lower storage electrode, and the third lower storage electrode; a first scan line extending on the second insulating layer in a second direction; a first pixel connected to the first scan line and the first data line; a second pixel connected to the first scan line and the second data line; and a third pixel connected to the first scan line and the third data line.

[0011] The display device according to an exemplary embodiment may further include: a first auxiliary scanning pattern, which is superimposed on the first scanning line and connected to the first scanning line, and the first auxiliary scanning pattern may be disposed on the same layer as the first lower storage electrode and is not superimposed on the first data line, the second data line and the third data line.

[0012] The display device according to an exemplary embodiment may further include: a first upper storage electrode stacked with a first lower storage electrode; a second upper storage electrode stacked with a second lower storage electrode; and a third upper storage electrode stacked with a third lower storage electrode, wherein the first upper storage electrode, the second upper storage electrode, and the third upper storage electrode may be arranged sequentially along a first direction and disposed on the same layer as the first scan line.

[0013] The display device according to an exemplary embodiment may further include: a first light-blocking layer stacked with a first lower storage electrode; a second light-blocking layer stacked with a second lower storage electrode; and a third light-blocking layer stacked with a third lower storage electrode, wherein the first light-blocking layer, the second light-blocking layer and the third light-blocking layer may be arranged sequentially along a first direction and disposed on the same layer as the first data line, the second data line and the third data line.

[0014] The display device according to an exemplary embodiment may further include: a driving voltage line and an initialization voltage line extending in a first direction; a first pixel may include a first driving transistor, a first switching transistor, and a first initialization transistor, the first driving transistor being connected between the driving voltage line and a first upper storage electrode, the first switching transistor being connected between a first lower storage electrode and a first data line, and the first initialization transistor being connected between the initialization voltage line and the first upper storage electrode; a second pixel includes a second driving transistor, a second switching transistor, and a second initialization transistor, the second driving transistor being connected between the driving voltage line and the second upper storage electrode, the second switching transistor being connected between the second lower storage electrode and the second data line, and the second initialization transistor being connected between the initialization voltage line and the second upper storage electrode; a third pixel includes a third driving transistor, a third switching transistor, and a third initialization transistor, the third driving transistor being connected between the driving voltage line and the third upper storage electrode, the third switching transistor being connected between the third lower storage electrode and the third data line, and the third initialization transistor being connected between the initialization voltage line and the third upper storage electrode.

[0015] The first driving transistor, the second driving transistor, and the third driving transistor can be arranged sequentially along the first direction, the first switching transistor, the second switching transistor, and the third switching transistor can be arranged sequentially along the first direction and connected to the first scan line, and the first initialization transistor, the second initialization transistor, and the third initialization transistor can be arranged sequentially along the first direction.

[0016] The display device according to an exemplary embodiment may further include: a second scan line extending in a second direction, and the second scan line may be disposed on the same layer as the first scan line and connected to the first initialization transistor, the second initialization transistor and the third initialization transistor.

[0017] The display device according to an exemplary embodiment may further include: a second auxiliary scanning pattern, superimposed on the second scanning line and connected to the second scanning line, and the second auxiliary scanning pattern may be disposed on the same layer as the first lower storage electrode and not superimposed on the first data line, the second data line and the third data line.

[0018] The display device according to an exemplary embodiment may further include: a third insulating layer disposed on the first scan line, and the first pixel may further include a first pixel electrode disposed on the third insulating layer and connected to the first driving transistor, and the first pixel electrode may be stacked with a second pixel or a third pixel.

[0019] The display device according to an exemplary embodiment may further include: a common voltage line extending in a first direction and disposed on the same layer as a first data line; a common voltage connection pattern connected to the common voltage line and disposed on the same layer as a first pixel electrode; an emission layer disposed on the first pixel electrode; and a common electrode disposed on the emission layer and connected to the common voltage connection pattern.

[0020] The display device according to an exemplary embodiment may further include: an auxiliary common voltage line extending in a second direction, disposed on the same layer as the first scan line, and connected to the common voltage line.

[0021] The display device according to an exemplary embodiment may further include: an auxiliary driving voltage line extending in a second direction, disposed on the same layer as the first scan line, and connected to the driving voltage line.

[0022] The display device according to an exemplary embodiment may further include: an auxiliary common voltage line extending from the common voltage connection pattern and disposed on the same layer as the first pixel electrode.

[0023] In the display device according to an exemplary embodiment, the second pixel may further include a second pixel electrode connected to the second driving transistor, the third pixel may further include a third pixel electrode connected to the third driving transistor, and the data line may be superimposed on one of the first pixel electrode, the second pixel electrode and the third pixel electrode, but not superimposed on the remaining pixel electrodes.

[0024] The display device according to an exemplary embodiment may further include: a connecting electrode to connect a first data line to a first switching transistor, and the connecting electrode may be disposed on the same layer as the first scan line.

[0025] In a display device according to an exemplary embodiment, the second insulating layer may include a single opening superimposed on a connection electrode, a first data line, and a first switching transistor, through which the connection electrode may be connected to the first data line and the first switching transistor, and the connection electrode may contact the side surface of the first switching transistor in the opening.

[0026] A display device according to an exemplary embodiment includes: a substrate; a driving voltage line, a first data line, a second data line, and a third data line extending on the substrate in a first direction; a first scan line and a second scan line extending in a second direction intersecting the first direction; and a first pixel, a second pixel, and a third pixel disposed between the driving voltage line and the first data line, disposed between the first scan line and the second scan line, and connected to the driving voltage line, the first scan line, and the second scan line, wherein the first pixel is connected to the first data line via at least one transistor, the second pixel is connected to the second data line via at least one transistor, and the third pixel is connected to the third pixel via at least one transistor.

[0027] The display device according to an exemplary embodiment may further include: an initialization voltage line extending in a first direction, and a first pixel including a first driving transistor, a first switching transistor, and a first initialization transistor, the first driving transistor being connected to the driving voltage line, the first switching transistor being connected between a first data line and the first driving transistor, and the first initialization transistor being connected between the initialization voltage line and the first driving transistor; a second pixel including a second driving transistor, a second switching transistor, and a second initialization transistor, the second driving transistor being connected to the driving voltage line, the second switching transistor being connected between a second data line and the second driving transistor, and the second initialization transistor being connected between the initialization voltage line and the second driving transistor; and a third pixel including a third driving transistor, a third switching transistor, and a third initialization transistor, the third driving transistor being connected to the driving voltage line, the third switching transistor being connected between a third data line and the third driving transistor, and the third initialization transistor being connected between the initialization voltage line and the third driving transistor.

[0028] The first driving transistor, the second driving transistor, and the third driving transistor can be arranged sequentially along a first direction. The first switching transistor, the second switching transistor, and the third switching transistor can be arranged sequentially along the first direction and connected to the first scan line. The first initialization transistor, the second initialization transistor, and the third initialization transistor can be arranged sequentially along the first direction and connected to the second scan line.

[0029] The display device according to an exemplary embodiment may further include: a buffer layer, a first insulating layer, and a second insulating layer, disposed between the first data line and the first scan line.

[0030] The display device according to an exemplary embodiment may further include: a common voltage line extending in a first direction; a first pixel electrode connected to a first driving transistor; an emitter layer disposed on the first pixel electrode; and a common electrode disposed on the emitter layer and connected to the common voltage line.

[0031] The display device according to an exemplary embodiment may further include: a common voltage connection pattern for connecting a common voltage line and a common electrode; and an auxiliary common voltage line extending in a second direction and connected to the common voltage line.

[0032] A display device according to an exemplary embodiment includes: a substrate; a common voltage line, a driving voltage line, and a data line extending in a first direction on the substrate and disposed on the same layer; a first common voltage auxiliary pattern superimposed on the common voltage line; a first insulating layer disposed between the common voltage line and the first common voltage auxiliary pattern; a second common voltage auxiliary pattern superimposed on the common voltage line and the first common voltage auxiliary pattern and connected to the common voltage line and the first common voltage auxiliary pattern; a second insulating layer disposed between the first common voltage auxiliary pattern and the second common voltage auxiliary pattern; a first scan line extending in a second direction intersecting the first direction and disposed on the second insulating layer; a pixel connected to the driving voltage line, the data line, and the first scan line via at least one transistor; an auxiliary common voltage line extending in the second direction and connected to the common voltage line; a common voltage connection pattern connected to the common voltage line; a third insulating layer disposed between the second common voltage auxiliary pattern and the common voltage connection pattern; a common electrode connected to the second common voltage auxiliary pattern; and a fourth insulating layer disposed between the common voltage connection pattern and the common electrode.

[0033] The auxiliary common voltage line can be set on the same layer as the second common voltage auxiliary pattern and the first scan line.

[0034] The display device according to an exemplary embodiment may further include: an auxiliary driving voltage line extending in a second direction, disposed on the same layer as the first scan line, and connected to the driving voltage line.

[0035] The auxiliary common voltage line can extend from the common voltage connection pattern and be set on the same layer as the common voltage connection pattern.

[0036] According to an exemplary embodiment, display quality can be improved by reducing the capacitance of parasitic capacitors formed by stacking data lines and wiring (such as scan lines that intersect with the data lines).

[0037] In addition, display quality can be improved by reducing the capacitance of parasitic capacitors, which are formed by stacking a common electrode and a data line that are completely disposed on the substrate.

[0038] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0039] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and form part of this specification.

[0040] Figure 1 This is a circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0041] Figure 2 This is a top plan view showing a portion of a display device according to an exemplary embodiment.

[0042] Figure 3 It is along Figure 2 A cross-sectional view of the display device according to an exemplary embodiment, taken by line III-III'.

[0043] Figure 4 It is along Figure 2 A cross-sectional view of a display device according to an exemplary embodiment, taken by line IV-IV'.

[0044] Figure 5 It is along Figure 2 A cross-sectional view of a display device according to an exemplary embodiment, taken by line V-V'.

[0045] Figure 6 It is along Figure 2 A cross-sectional view of a display device according to an exemplary embodiment, taken by line VI-VI'.

[0046] Figures 7 to 10 This is a top plan view showing the manufacturing sequence of the display device according to an exemplary embodiment.

[0047] Figure 11 It is a graph showing the variation in capacitance of parasitic capacitors according to the size of the display device.

[0048] Figure 12 This is a top plan view showing a portion of a display device according to an exemplary embodiment.

[0049] Figure 13 It is along Figure 12 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XIII-XIII'.

[0050] Figure 14 This is a top plan view showing a portion of a display device according to an exemplary embodiment.

[0051] Figure 15 It is along Figure 14 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XV-XV'.

[0052] Figure 16 This is a top plan view showing partial constituent elements of a display device according to an exemplary embodiment.

[0053] Figure 17 It is along Figure 16 A cross-sectional view of the display device according to an exemplary embodiment, taken by lines XVII-XVII'.

[0054] Figure 18 This is a top plan view showing partial constituent elements of a display device according to an exemplary embodiment.

[0055] Figure 19 It is along Figure 18 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XIX-XIX'.

[0056] Figure 20 This is a top plan view showing partial constituent elements of a display device according to an exemplary embodiment.

[0057] Figure 21 This is a cross-sectional view showing partial constituent elements of a display device according to an exemplary embodiment. Detailed Implementation

[0058] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms as non-limiting examples of apparatuses or methods employing one or more of the inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, a particular shape, construction, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0059] Unless otherwise stated, the exemplary embodiments shown are to be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or uniformly referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0060] The use of crosshairs and / or shading in accompanying drawings is typically to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, scale, commonalities between the elements shown, or any other characteristics, properties, etc., of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed in a different order than that described when exemplary embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same elements.

[0061] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, directly connected to, or directly bonded to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without intermediate components. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system such as the x, y, and z axes, but can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms “first,” “second,” etc., can be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below can be referred to as the second element without departing from the publicly stated teaching.

[0063] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” “side” (e.g., as in “sidewall”) may be used herein to describe the relationship of one element to another, as shown in the accompanying drawings. Spatial relative terms are intended to include not only the orientation depicted in the drawings but also different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is rotated, an element described as “below” or “under” other elements or features would then be oriented “above” said other elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0064] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a” and “the” as used herein are intended to include the plural forms as well. Furthermore, when the terms “comprising,” “including,” and / or variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, and are thus used to interpret the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0065] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations, for example, due to manufacturing techniques and / or tolerances, will be anticipated. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the shapes of the specifically shown areas, but will include deviations in shape caused, for example, by manufacturing processes. In this way, the areas shown in the drawings may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, so this is not intended to be limiting.

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0067] Figure 1 This is a circuit diagram of a pixel of a display device according to an exemplary embodiment.

[0068] The display device according to an exemplary embodiment includes a plurality of pixels PX. For example... Figure 1 As shown, each of the plurality of pixels PX may include a plurality of transistors T1, T2 and T3, a capacitor Cst, and at least one light-emitting diode (LED) ED as a light-emitting element. In this exemplary embodiment, an example in which one pixel PX includes a light-emitting diode (LED) ED is primarily described.

[0069] The plurality of transistors T1, T2, and T3 includes a drive transistor T1, a switch transistor T2, and an initialization transistor T3. The first electrode and the second electrode, which will be described below, are used to distinguish the two electrodes located on both sides of the channel of each of transistors T1, T2, and T3, and can be either source electrodes or drain electrodes.

[0070] The gate electrode of the driving transistor T1 is connected to one terminal of the capacitor Cst, the first electrode of the driving transistor T1 is connected to the driving voltage line that transmits the driving voltage ELVDD, and the second electrode of the driving transistor T1 is connected to the anode of the light-emitting diode (LED) ED and the other terminal of the capacitor Cst. The driving transistor T1 can receive the data voltage DAT according to the switching operation of the switching transistor T2, so as to supply driving current to the light-emitting diode (LED) ED according to the voltage stored in the capacitor Cst.

[0071] The gate electrode of switching transistor T2 is connected to the first scan line that transmits the first scan signal SC. The first electrode of switching transistor T2 is connected to a data line capable of transmitting data voltage DAT or a reference voltage. The second electrode of switching transistor T2 is connected to a terminal of capacitor Cst and the gate electrode of driving transistor T1. Switching transistor T2 is turned on according to the first scan signal SC, thereby transmitting the reference voltage or data voltage DAT to the gate electrode of driving transistor T1 and a terminal of capacitor Cst.

[0072] The gate electrode of the initialization transistor T3 is connected to the second scan line that transmits the second scan signal SS. The first electrode of the initialization transistor T3 is connected to the other terminal of the capacitor Cst, the second electrode of the driving transistor T1, and the anode of the light-emitting diode (LED) ED. The second electrode of the initialization transistor T3 is connected to the initialization voltage line that transmits the initialization voltage INIT. The initialization transistor T3 is turned on according to the second scan signal SS to transmit the initialization voltage INIT to the anode of the LED ED and the other terminal of the capacitor Cst, thereby initializing the voltage of the anode of the LED ED.

[0073] One terminal of capacitor Cst is connected to the gate electrode of driving transistor T1, and the other terminal is connected to the first electrode of initialization transistor T3 and the anode of light-emitting diode (LED) ED. The cathode of LED ED is connected to the common voltage line that transmits the common voltage ELVSS.

[0074] A light-emitting diode (LED) can emit light of a certain brightness according to the driving current generated by the driving transistor T1.

[0075] will describe Figure 1 The circuit diagram shown is an example of operation (specifically, an example of operation during one frame). Here, the case where transistors T1, T2, and T3 are N-channel transistors is described as an example, but it is not limited to this.

[0076] At the start of a frame, a high-level first scan signal SC and a high-level second scan signal SS are supplied during the initialization period, causing switching transistor T2 and initialization transistor T3 to conduct. Through the conducting switching transistor T2, a reference voltage from the data line is supplied to the gate electrode of driving transistor T1 and one terminal of capacitor Cst, and the initialization voltage INIT is supplied through the conducting initialization transistor T3 to the second electrode of driving transistor T1 and the anode of light-emitting diode (LED) ED.

[0077] Therefore, during the initialization period, the anode of the light-emitting diode (LED) ED and the second electrode of the driving transistor T1 are initialized to the initialization voltage INIT. The voltage difference between the reference voltage and the initialization voltage INIT is stored in the capacitor Cst.

[0078] Next, when the second scan signal SS changes from a high level to a low level while the first scan signal SC is held high during the sensing period, the switching transistor T2 remains on, and the initialization transistor T3 is off. The gate electrode of the driving transistor T1 and one terminal of the capacitor Cst maintain a reference voltage through the on-state switching transistor T2, while the second electrode of the driving transistor T1 and the anode of the light-emitting diode (LED) ED are disconnected from the initialization voltage INIT through the off-state initialization transistor T3. Therefore, if current flows from the first electrode of the driving transistor T1 to the second electrode and the voltage at the second electrode of the driving transistor T1 becomes the "reference voltage - Vth", then the driving transistor T1 is off. Vth represents the threshold voltage of the driving transistor T1. At this time, the voltage difference between the gate electrode and the second electrode of the driving transistor T1 is stored in the capacitor Cst, and the sensing of the threshold voltage Vth of the driving transistor T1 is complete. By generating a compensation data signal reflecting the characteristic information sensed during the sensing period, the characteristic deviation of the driving transistor T1, which may differ for each pixel, can be compensated externally.

[0079] Next, during the data input period, when a high-level first scan signal SC and a low-level second scan signal SS are supplied, switching transistor T2 is turned on and initialization transistor T3 is turned off. Through the turned-on switching transistor T2, the data voltage DAT from the data line is supplied to the gate electrode of driving transistor T1 and one terminal of capacitor Cst. At this time, the second electrode of driving transistor T1 and the anode of the light-emitting diode (LED) ED can maintain their potentials almost unchanged during the sensing period through the off-state driving transistor T1.

[0080] Next, during the light-emitting period, the driving transistor T1, which is turned on by the data voltage DAT transmitted to the gate electrode, generates a driving current according to the data voltage DAT, and then the light-emitting diode (LED) ED can emit light through the driving current.

[0081] Next, refer to Figures 2 to 10 as well as Figure 1 The detailed structure of a display device according to an exemplary embodiment is described.

[0082] Figure 2 This is a top plan view showing a portion of a display device according to an exemplary embodiment. Figure 3 It is along Figure 2 A cross-sectional view of the display device according to an exemplary embodiment, taken by line III-III'. Figure 4 It is along Figure 2 A cross-sectional view of a display device according to an exemplary embodiment, taken by line IV-IV'. Figure 5 It is along Figure 2A cross-sectional view of the display device according to an exemplary embodiment, taken by line V-V'. Figure 6 It is along Figure 2 A cross-sectional view of a display device according to an exemplary embodiment, taken by line VI-VI'. Figures 7 to 10 This is a top plan view showing the manufacturing sequence of the display device according to an exemplary embodiment. Figures 2 to 10 Three adjacent pixels of a display device according to an exemplary embodiment are shown, and these pixels can be repeatedly arranged.

[0083] Here, each of the plurality of pixels PX1, PX2 and PX3 may refer to a portion or region formed having constituent elements (i.e., a plurality of transistors T1, T2 and T3, a capacitor Cst and a light-emitting diode (LED) ED) included in a pixel PX as described above.

[0084] The display device according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material such as glass and plastic, and may be flexible.

[0085] A first conductive layer comprising a first data line 171a, a second data line 171b, and a third data line 171c may be disposed on the substrate 110. Figure 7 The first conductive layer is shown.

[0086] First data line 171a, second data line 171b, and third data line 171c extend in a first direction D1. That is, the first data line 171a, second data line 171b, and third data line 171c can be formed from a rod (bar) shape having a predetermined width and extending along the first direction D1. The first data line 171a, second data line 171b, and third data line 171c can be arranged adjacent to each other along a second direction D2 intersecting the first direction D1. The first data line 171a, second data line 171b, and third data line 171c can be spaced apart by a predetermined interval. Different data voltages DL1, DL2, and DL3 are applied to the first data line 171a, second data line 171b, and third data line 171c, and the first data line 171a, second data line 171b, and third data line 171c can be arranged separately to prevent short circuits between them. The first direction D1 can be a column direction, and the second direction D2 can be a row direction. The first direction D1 and the second direction D2 can be perpendicular to each other. The second data line 171b can be arranged adjacent to the right side of the first data line 171a, and the third data line 171c can be arranged adjacent to the right side of the second data line 171b. The statement that data lines 171a, 171b, and 171c are arranged adjacently means that there are no other wirings extending in a direction parallel to the data lines 171a, 171b, and 171c between them. That is, other wirings extending in a direction parallel to the data lines 171a, 171b, and 171c are not arranged between the adjacent first data line 171a and the second data line 171b. Furthermore, other wirings are not arranged between the adjacent second data line 171b and the third data line 171c.

[0087] The first conductive layer may also include a common voltage line 170, an initialization voltage line 173, a driving voltage line 172, and a light-blocking pattern (or light-blocking layer) 177.

[0088] The common voltage line 170, initialization voltage line 173, and drive voltage line 172 extend in a first direction D1. That is, the common voltage line 170, initialization voltage line 173, and drive voltage line 172 can extend in a direction parallel to the first data line 171a, the second data line 171b, and the third data line 171c. The common voltage line 170, initialization voltage line 173, and drive voltage line 172 can be configured to be adjacent along a second direction D2. The common voltage line 170, initialization voltage line 173, and drive voltage line 172 can be configured to be spaced apart at a predetermined interval. A common voltage ELVSS can be applied to the common voltage line 170, an initialization voltage INIT can be applied to the initialization voltage line 173, and a drive voltage ELVDD can be applied to the drive voltage line 172. The common voltage line 170, initialization voltage line 173, and drive voltage line 172, which have different voltages applied, can be configured to be spaced apart so that a short circuit does not occur between them. The initialization voltage line 173 can be positioned between the common voltage line 170 and the drive voltage line 172. However, their positions are not limited to this and can be changed.

[0089] A light-blocking pattern 177 can be disposed on a plane between the driving voltage line 172 and the first data line 171a. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a light-blocking pattern 177, and multiple light-blocking patterns 177 can be arranged to be adjacent to each other along a first direction D1. The light-blocking pattern 177 of the second pixel PX2 can be disposed on a plane below the light-blocking pattern 177 of the first pixel PX1, and the light-blocking pattern 177 of the third pixel PX3 can be disposed below the light-blocking pattern 177 of the second pixel PX2.

[0090] The planar shape of the light-blocking pattern 177 can be made of polygons. The planar shapes of the light-blocking patterns 177 of multiple pixels PX1, PX2, and PX3 can be the same or different. For example, the planar shapes of the light-blocking patterns 177 of the first pixel PX1 and the second pixel PX2 can be symmetrical to each other, and the planar shapes of the light-blocking patterns 177 of the second pixel PX2 and the third pixel PX3 can be the same.

[0091] The insulating layer of the buffer layer 111 can be disposed on the first conductive layer, which includes a first data line 171a, a second data line 171b, a third data line 171c, a common voltage line 170, an initialization voltage line 173, a driving voltage line 172, and a light blocking pattern 177.

[0092] A semiconductor layer may be disposed on the buffer layer 111. The semiconductor layer includes a channel 1132, a first electrode 1131 and a second electrode 1133 of the driving transistor T1 of the first pixel PX1, the second pixel PX2 and the third pixel PX3, a channel 2132, a first electrode 2131 and a second electrode 2133 of the switching transistor T2, and a channel 3132, a first electrode 3131 and a second electrode 3133 of the initialization transistor T3. Figure 8 A first conductive layer and a semiconductor layer are shown. The semiconductor layer may include semiconductor materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductors.

[0093] The channel 1132, first electrode 1131, and second electrode 1133 of the driving transistor T1 can be formed in a rod shape extending in the second direction D2. The channel 1132 of the driving transistor T1 can be disposed between the first electrode 1131 and the second electrode 1133. The first electrode 1131 of the driving transistor T1 can be stacked with the driving voltage line 172. The first electrode 1131 of the driving transistor T1 can be connected to the driving voltage line 172 and can receive the driving voltage ELVDD from the driving voltage line 172. However, the first electrode 1131 of the driving transistor T1 may not be directly connected to the driving voltage line 172. The channel 1132 and second electrode 1133 of the driving transistor T1 can be stacked with the light-blocking pattern 177.

[0094] The driving transistors T1 for the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged sequentially along the first direction D1. That is, the driving transistor T1 for the second pixel PX2 can be arranged on the plane below the driving transistor T1 for the first pixel PX1, and the driving transistor T1 for the third pixel PX3 can be arranged below the driving transistor T1 for the second pixel PX2.

[0095] The channel 2132, first electrode 2131, and second electrode 2133 of the switching transistor T2 can be formed in a rod shape extending in the second direction D2. The channel 2132 of the switching transistor T2 can be disposed between the first electrode 2131 and the second electrode 2133. The first electrode 2131 of the switching transistor T2 can be stacked with and connected to data lines 171a, 171b, and 171c. The first electrode 2131 of the switching transistor T2 of the first pixel PX1 can be connected to the first data line 171a. The first electrode 2131 of the switching transistor T2 of the second pixel PX2 can be connected to the second data line 171b. The first electrode 2131 of the switching transistor T2 of the third pixel PX3 can be connected to the third data line 171c. However, the first electrode 2131 of the switching transistor T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may not be directly connected to the respective data lines 171a, 171b, and 171c. The lengths of the first electrode 2131 of the switching transistor T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be different. For example, the length of the first electrode 2131 of the switching transistor T2 of the second pixel PX2 may be longer than the length of the first electrode 2131 of the switching transistor T2 of the first pixel PX1. The first electrode 2131 of the switching transistor T2 of the third pixel PX3 may be longer than the first electrode 2131 of the switching transistor T2 of the second pixel PX2.

[0096] The switching transistors T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged sequentially along the first direction D1. That is, the switching transistor T2 of the second pixel PX2 can be arranged on the plane below the switching transistor T2 of the first pixel PX1, and the switching transistor T2 of the third pixel PX3 can be arranged below the switching transistor T2 of the second pixel PX2. The switching transistors T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are connected to different data lines 171a, 171b, and 171c.

[0097] The channel 3132, first electrode 3131, and second electrode 3133 of the initialization transistor T3 can be formed in a rod shape extending in the second direction D2. The channel 3132 of the initialization transistor T3 can be disposed between the first electrode 3131 and the second electrode 3133. The second electrode 3133 of the initialization transistor T3 can be superimposed on the initialization voltage line 173. The second electrode 3133 of the initialization transistor T3 can be connected to the initialization voltage line 173 and receive the initialization voltage INIT. However, the second electrode 3133 of the initialization transistor T3 may not be directly connected to the initialization voltage line 173. The first electrode 3131 of the initialization transistor T3 can be superimposed on the driving voltage line 172 and the light blocking pattern 177.

[0098] The initialization transistors T3 for the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged sequentially along the first direction D1. That is, the initialization transistor T3 for the second pixel PX2 can be arranged on the plane below the initialization transistor T3 for the first pixel PX1, and the initialization transistor T3 for the third pixel PX3 can be arranged below the initialization transistor T3 for the second pixel PX2.

[0099] The first insulating layer 120 may be disposed on the semiconductor layer, which includes a channel 1132, a first electrode 1131 and a second electrode 1133 for driving transistor T1, a channel 2132, a first electrode 2131 and a second electrode 2133 for switching transistor T2, and a channel 3132, a first electrode 3131 and a second electrode 3133 for initialization transistor T3.

[0100] A second conductive layer may be disposed on the first insulating layer 120. The second conductive layer includes the gate electrode 1155 of the driving transistor T1 of the first pixel PX1, the gate electrode 2155 of the switching transistor T2, the gate electrode 3155 of the initialization transistor T3, and the lower storage electrode 1153. Figure 9 The first conductive layer, the semiconductor layer, and the second conductive layer are shown.

[0101] The gate electrode 1155 of the driving transistor T1 may be stacked with the channel 1132 of the driving transistor T1. The gate electrode 1155 of the driving transistor T1 may be connected to the lower storage electrode 1153 and may be integrally formed with the lower storage electrode 1153. The lower storage electrode 1153 may be stacked with the second electrode 2133 of the switching transistor T2. The lower storage electrode 1153 may be connected to the second electrode 2133 of the switching transistor T2. However, the lower storage electrode 1153 may not be directly connected to the second electrode 2133 of the switching transistor T2.

[0102] The planar shape of the lower storage electrode 1153 can be composed of polygons. The planar shapes of the lower storage electrodes 1153 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be the same or different. For example, the planar shapes of the lower storage electrodes 1153 of the first pixel PX1 and the second pixel PX2 can be symmetrical to each other, and the planar shapes of the lower storage electrodes 1153 of the second pixel PX2 and the third pixel PX3 can be the same.

[0103] The gate electrode 2155 of the switching transistor T2 can be stacked with the channel 2132 of the switching transistor T2. The gate electrodes 2155 of the switching transistors T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be connected to each other and can be integrally formed. Therefore, the same first scan signal SC can be applied to the gate electrodes 2155 of the switching transistors T2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The gate electrodes 2155 of the interconnected switching transistors T2 can be formed in the shape of a rod extending in the first direction D1.

[0104] The gate electrode 3155 of the initialization transistor T3 can be stacked with the channel 3132 of the initialization transistor T3. The gate electrodes 3155 of the initialization transistors T3 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be connected to each other and can be integrally formed. Therefore, the same second scan signal SS can be applied to the gate electrodes 3155 of the initialization transistors T3 of the first pixel PX1, the second pixel PX2, and the third pixel PX3. The gate electrodes 3155 of the initialization transistors T3 connected to each other can be formed in the shape of a rod extending in the first direction D1.

[0105] After the second conductive layer is formed, a doping process can be performed. The semiconductor layer covered by the second conductive layer is not doped, and the portions of the semiconductor layer not covered by the second conductive layer are doped to have the same properties as a conductor. That is, the channel 1132 of the driving transistor T1, the channel 2132 of the switching transistor T2, and the channel 3132 of the initialization transistor T3, which are not covered by the second conductive layer, are not doped. The first electrode 1131 and the second electrode 1133 of the driving transistor T1, the first electrode 2131 and the second electrode 2133 of the switching transistor T2, and the first electrode 3131 and the second electrode 3133 of the initialization transistor T3, which are not covered by the second conductive layer, are doped to have the same properties as a conductor.

[0106] The second conductive layer may further include a first auxiliary scanning pattern 151a, a second auxiliary scanning pattern 152a, and a first common voltage auxiliary pattern 170a.

[0107] The first auxiliary scanning pattern 151a and the second auxiliary scanning pattern 152a can extend in the second direction D2. The lower storage electrodes 1153 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be disposed in a plane between the first auxiliary scanning pattern 151a and the second auxiliary scanning pattern 152a. The first auxiliary scanning pattern 151a can be connected to the gate electrode 2155 of the switching transistor T2 and can be integrally formed with the gate electrode 2155.

[0108] The first common voltage auxiliary pattern 170a can be superimposed on the common voltage line 170. The first common voltage auxiliary pattern 170a can be formed as a rod shape extending in the first direction D1. The common voltage line 170 can have a shape extending from one end of the substrate 110 to the other in a plane. For every three pixels PX1, PX2, and PX3, the first common voltage auxiliary pattern 170a can be repeatedly set in an open shape. The first common voltage auxiliary pattern 170a can be connected to the common voltage line 170 and can be used to reduce the resistance of the common voltage line 170. The first common voltage auxiliary pattern 170a may not be directly connected to the common voltage line 170.

[0109] The second insulating layer 160 may be disposed on the second conductive layer, which includes the gate electrode 1155 of the driving transistor T1, the gate electrode 2155 of the switching transistor T2, the gate electrode 3155 of the initialization transistor T3, and the lower storage electrode 1153.

[0110] A third conductive layer, including a first scan line 151, a second scan line 152, and an upper storage electrode 1154, may be disposed on the second insulating layer 160. Figure 10 The first conductive layer, the semiconductor layer, the second conductive layer, and the third conductive layer are shown.

[0111] A first scan line 151 extends in a second direction D2. The first scan line 151 may intersect with data lines 171a, 171b, and 171c, and the first scan line 151 and data lines 171a, 171b, and 171c may overlap at their intersection points. The first scan line 151 may overlap with a first auxiliary scan pattern 151a. The first scan line 151 may be connected to the first auxiliary scan pattern 151a. The first auxiliary scan pattern 151a can be used to reduce the resistance of the first scan line 151. The first auxiliary scan pattern 151a may not overlap with the data lines 171a, 171b, and 171c. The first scan line 151 may have a shape extending from one end of the substrate 110 to the other. The first auxiliary scan pattern 151a may be repeatedly arranged in an intermittent shape, the length of which corresponds to the length of the region between the drive voltage line 172 and the first data line 171a. A first scan signal SC may be applied to the first scan line 151. The first scan line 151 can be connected to the gate electrode 2155 of the switching transistor T2 via the first auxiliary scan pattern 151a. Therefore, the gate electrode 2155 of the switching transistor T2 can receive the first scan signal SC from the first scan line 151.

[0112] Parasitic capacitors may be formed at the portions of each data line 171a, 171b, and 171c that overlap with the first scan line 151. In this exemplary embodiment, the data lines 171a, 171b, and 171c are disposed in the first conductive layer, and the first scan line 151 is disposed in the third conductive layer. Therefore, the first insulating layer 120 and the second insulating layer 160 may be disposed between the data lines 171a, 171b, and 171c and the first scan line 151. In contrast, when the first scan line 151 is disposed in the second conductive layer and the data lines 171a, 171b, and 171c are disposed in the third conductive layer, the second insulating layer 160 is located between the first scan line 151 and the data lines 171a, 171b, and 171c. In this exemplary embodiment, compared to the case where the first scan line 151 is disposed in the second conductive layer and the data lines 171a, 171b, and 171c are disposed in the third conductive layer, the distance between the data lines 171a, 171b, and 171c and the first scan line 151 is relatively long, thus reducing the capacitance of the parasitic capacitor. Furthermore, since the first auxiliary scan pattern 151a does not overlap with the data lines 171a, 171b, and 171c, the capacitance of the parasitic capacitor can be reduced.

[0113] The second scan line 152 extends in the second direction D2. The second scan line 152 may intersect with data lines 171a, 171b, and 171c, and the second scan line 152 and the data lines 171a, 171b, and 171c may overlap at their intersection points. The second scan line 152 may overlap with a second auxiliary scan pattern 152a. The second scan line 152 may be connected to the second auxiliary scan pattern 152a. The second auxiliary scan pattern 152a can be used to reduce the resistance of the second scan line 152. The second auxiliary scan pattern 152a may not overlap with the data lines 171a, 171b, and 171c. The second scan line 152 may have a shape extending from one end of the substrate 110 to the other. The second auxiliary scan pattern 152a has a length corresponding to the length of the region between the drive voltage line 172 and the first data line 171a, and may be repeatedly arranged in an intermittent shape. A second scan signal SS may be applied to the second scan line 152. The second scan line 152 can be connected to the gate electrode 3155 of the initialization transistor T3. Therefore, the gate electrode 3155 of the initialization transistor T3 can receive the second scan signal SS from the second scan line 152.

[0114] Parasitic capacitors may be formed at the portions where the data lines 171a, 171b, and 171c overlap with the second scan line 152. In this exemplary embodiment, the data lines 171a, 171b, and 171c are disposed in the first conductive layer, and the second scan line 152 is disposed in the third conductive layer. Therefore, the first insulating layer 120 and the second insulating layer 160 can be disposed between the data lines 171a, 171b, and 171c and the second scan line 152. Therefore, compared to the case where the second scan line 152 is disposed in the second conductive layer and the data lines 171a, 171b, and 171c are disposed in the third conductive layer, the capacitance of the parasitic capacitors between the data lines 171a, 171b, and 171c and the second scan line 152 can be reduced. In addition, since the second auxiliary scan pattern 152a does not overlap with the data lines 171a, 171b, and 171c, the capacitance of the parasitic capacitors can be reduced.

[0115] The upper storage electrode 1154 can be stacked with the lower storage electrode 1153. The lower storage electrode 1153 and the upper storage electrode 1154 can be stacked with each other via a second insulating layer 160 therebetween to form a capacitor Cst. The lower storage electrode 1153 can be stacked with a light-blocking pattern 177 with a first insulating layer 120 between them, so that the capacitor Cst can be formed in duplicate.

[0116] The upper storage electrode 1154 may be stacked with the second electrode 1133 of the driving transistor T1. The second insulating layer 160 may include an opening 165 stacked with the upper storage electrode 1154 and the second electrode 1133 of the driving transistor T1. The opening 165 may also be formed in the first insulating layer 120. The upper storage electrode 1154 can be connected to the second electrode 1133 of the driving transistor T1 through the opening 165.

[0117] The upper storage electrode 1154 may be stacked with the light-blocking pattern 177. The second insulating layer 160 may include an opening 166 stacked with the upper storage electrode 1154 and the light-blocking pattern 177. The opening 166 may also be formed in the first insulating layer 120 and the buffer layer 111. The upper storage electrode 1154 can be connected to the light-blocking pattern 177 through the opening 166.

[0118] The upper storage electrode 1154 may be stacked with the first electrode 3131 of the initialization transistor T3. The second insulating layer 160 may include an opening 167 stacked with the upper storage electrode 1154 and the first electrode 3131 of the initialization transistor T3. The opening 167 may also be formed in the first insulating layer 120. The upper storage electrode 1154 may be connected to the first electrode 3131 of the initialization transistor T3 through the opening 167.

[0119] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 includes an upper storage electrode 1154, a lower storage electrode 1153, and a light-blocking pattern 177. The upper storage electrode 1154, the lower storage electrode 1153, and the light-blocking pattern 177 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be disposed on a plane between a first scan line 151 and a second scan line 152. Furthermore, the upper storage electrode 1154, the lower storage electrode 1153, and the light-blocking pattern 177 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be disposed between a driving voltage line 172 and a first data line 171a. That is, the upper storage electrode 1154, the lower storage electrode 1153, and the light-blocking pattern 177 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are surrounded on a plane by the first scan line 151, the second scan line 152, the driving voltage line 172, and the first data line 171a. The upper storage electrodes 1154 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged adjacently along the first direction D1. The upper storage electrode 1154 of the second pixel PX2 can be disposed below the upper storage electrode 1154 of the first pixel PX1 on a plane, and the upper storage electrode 1154 of the third pixel PX3 can be disposed below the upper storage electrode 1154 of the second pixel PX2. The lower storage electrodes 1153 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be arranged adjacently along the first direction D1. On a plane, the lower storage electrode 1153 of the second pixel PX2 can be disposed below the lower storage electrode 1153 of the first pixel PX1, and the lower storage electrode 1153 of the third pixel PX3 can be disposed below the lower storage electrode 1153 of the second pixel PX2.

[0120] The planar shape of the upper storage electrode 1154 can be a polygon.

[0121] The planar shapes of the upper storage electrodes 1154 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be the same or different. For example, the planar shapes of the upper storage electrodes 1154 of the first pixel PX1 and the second pixel PX2 can be symmetrical to each other, and the planar shapes of the upper storage electrodes 1154 of the second pixel PX2 and the third pixel PX3 can be the same.

[0122] The third conductive layer may further include a first connecting electrode 178, a second connecting electrode 179, a second common voltage auxiliary pattern 170b, an auxiliary common voltage line 170c, an initialization voltage auxiliary pattern 173a, a driving voltage auxiliary pattern 172a, and an auxiliary driving voltage line 172c.

[0123] Each pixel PX1, PX2, and PX3 may include a first connection electrode 178. The first connection electrode 178 of each pixel PX1, PX2, and PX3 may be stacked with each data line 171a, 171b, and 171c. The second insulating layer 160 may include an opening 161 stacked with the first connection electrode 178 and each data line 171a, 171b, and 171c. The opening 161 may also be formed in the first insulating layer 120 and the buffer layer 111. The first connection electrode 178 can be connected to the data lines 171a, 171b, and 171c through the opening 161. The first connection electrode 178 of each pixel PX1, PX2, and PX3 may be stacked with the first electrode 2131 of the switching transistor T2. The second insulating layer 160 may include an opening 162 stacked with the first connection electrode 178 and the first electrode 2131 of the switching transistor T2. The opening 162 may also be formed in the first insulating layer 120. The first connection electrode 178 can be connected to the first electrode 2131 of the switching transistor T2 through the opening 162. Therefore, the first connection electrode 178 can be connected between each of the data lines 171a, 171b, and 171c and the first electrode 2131 of the switching transistor T2. In the first pixel PX1, the first connection electrode 178 can be connected between the first data line 171a and the first electrode 2131 of the switching transistor T2. In the second pixel PX2, the first connection electrode 178 can be connected between the second data line 171b and the first electrode 2131 of the switching transistor T2. In the third pixel PX3, the first connection electrode 178 can be connected between the third data line 171c and the first electrode 2131 of the switching transistor T2.

[0124] Each pixel PX1, PX2, and PX3 may include a second connection electrode 179. The second connection electrode 179 of each pixel PX1, PX2, and PX3 may be stacked with the second electrode 2133 of the switching transistor T2. The second insulating layer 160 may include an opening 163 stacked with the second connection electrode 179 and the second electrode 2133 of the switching transistor T2. The opening 163 may also be formed in the first insulating layer 120. The second connection electrode 179 can be connected to the second electrode 2133 of the switching transistor T2 through the opening 163. The second connection electrode 179 of each pixel PX1, PX2, and PX3 may be stacked with the lower storage electrode 1153. The second insulating layer 160 may include an opening 164 stacked with the second connection electrode 179 and the lower storage electrode 1153. The second connection electrode 179 can be connected to the lower storage electrode 1153 through the opening 164. Therefore, in each pixel PX1, PX2 and PX3, the second connection electrode 179 can be connected between the second electrode 2133 of the switching transistor T2 and the lower storage electrode 1153.

[0125] The second common voltage auxiliary pattern 170b can be stacked with the first common voltage auxiliary pattern 170a. The second insulating layer 160 may include an opening 1161 stacked with the first common voltage auxiliary pattern 170a and the second common voltage auxiliary pattern 170b. The second common voltage auxiliary pattern 170b can be connected to the first common voltage auxiliary pattern 170a through the opening 1161. The second common voltage auxiliary pattern 170b can be stacked with the common voltage line 170. The second insulating layer 160 may include an opening 1162 stacked with the common voltage line 170 and the second common voltage auxiliary pattern 170b. The opening 1162 may also be formed in the first insulating layer 120 and the buffer layer 111. The second common voltage auxiliary pattern 170b can be connected to the common voltage line 170 through the opening 1162. Therefore, the second common voltage auxiliary pattern 170b can connect the common voltage line 170 and the first common voltage auxiliary pattern 170a. The first common voltage auxiliary pattern 170a and the second common voltage auxiliary pattern 170b can be used to reduce the resistance of the common voltage line 170. The second common voltage auxiliary pattern 170b can be formed by a rod shape extending in the first direction D1. The first common voltage auxiliary pattern 170a can be repeatedly set in a broken shape for every three pixels PX1, PX2 and PX3.

[0126] The auxiliary common voltage line 170c may extend in the second direction D2. The auxiliary common voltage line 170c may intersect with the common voltage line 170, and at their intersection, the auxiliary common voltage line 170c and the common voltage line 170 may overlap. The second insulating layer 160 may include an opening 1165 overlapping with the auxiliary common voltage line 170c and the common voltage line 170. The opening 1165 may also be formed in the first insulating layer 120 and the buffer layer 111. The auxiliary common voltage line 170c can be connected to the common voltage line 170 through the opening 1165. A common voltage ELVSS may be applied to the auxiliary common voltage line 170c. The auxiliary common voltage line 170c can be used to reduce the resistance of the common voltage line 170.

[0127] The initialization voltage auxiliary pattern 173a can be superimposed on the initialization voltage line 173. The second insulating layer 160 may include an opening 1163 superimposed on the initialization voltage line 173 and the initialization voltage auxiliary pattern 173a. The opening 1163 may also be formed in the first insulating layer 120 and the buffer layer 111. The initialization voltage auxiliary pattern 173a can be connected to the initialization voltage line 173 through the opening 1163. The initialization voltage auxiliary pattern 173a can be used to reduce the resistance of the initialization voltage line 173. The initialization voltage auxiliary pattern 173a can be formed by a rod shape extending in the first direction D1. The initialization voltage auxiliary pattern 173a can be repeatedly set in a broken shape for every three pixels PX1, PX2, and PX3.

[0128] The initialization voltage auxiliary pattern 173a may be stacked with the second electrode 3133 of the initialization transistor T3. The second insulating layer 160 may include an opening 168 stacked with the initialization voltage auxiliary pattern 173a and the second electrode 3133 of the initialization transistor T3. The opening 168 may also be formed in the first insulating layer 120. The initialization voltage auxiliary pattern 173a can be connected to the second electrode 3133 of the initialization transistor T3 through the opening 168.

[0129] The driving voltage auxiliary pattern 172a can be superimposed on the driving voltage line 172. The second insulating layer 160 may include an opening superimposed on the driving voltage line 172 and the driving voltage auxiliary pattern 172a. The opening may also be formed in the first insulating layer 120 and the buffer layer 111. The driving voltage auxiliary pattern 172a can be connected to the driving voltage line 172 through the opening. The driving voltage auxiliary pattern 172a can be used to reduce the resistance of the driving voltage line 172. The driving voltage auxiliary pattern 172a can be formed in a rod shape extending in the first direction D1. The driving voltage auxiliary pattern 172a can be repeated in a broken shape for every three pixels PX1, PX2, and PX3. The driving voltage auxiliary pattern 172a can be superimposed on the first electrode 1131 of the driving transistor T1. The second insulating layer 160 may include an opening 1164 superimposed on the driving voltage auxiliary pattern 172a and the first electrode 1131 of the driving transistor T1. The opening 1164 may also be formed in the first insulating layer 120. The driving voltage auxiliary pattern 172a can be connected to the first electrode 1131 of the driving transistor T1 through the opening 1164.

[0130] The auxiliary driving voltage line 172c may extend in the second direction D2. The auxiliary driving voltage line 172c may intersect with the driving voltage line 172, and at their intersection, the auxiliary driving voltage line 172c and the driving voltage line 172 may overlap. The second insulating layer 160 may include an opening 1166 overlapping with the auxiliary driving voltage line 172c and the driving voltage line 172. The opening 1166 may also be formed in the first insulating layer 120 and the buffer layer 111. The auxiliary driving voltage line 172c can be connected to the driving voltage line 172 through the opening 1166. The driving voltage ELVDD may be applied to the auxiliary driving voltage line 172c. The auxiliary driving voltage line 172c can be used to reduce the resistance of the driving voltage line 172.

[0131] The auxiliary common voltage line 170c and the auxiliary drive voltage line 172c can extend side by side. The auxiliary common voltage line 170c and the auxiliary drive voltage line 172c can be set alternately.

[0132] The third insulating layer 180 may be disposed on the third conductive layer, which includes the first scan line 151, the second scan line 152 and the upper storage electrode 1154.

[0133] At least one of the first, second, and third conductive layers may include at least one metal selected from copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. Each of the first, second, and third conductive layers may be made of a single layer or multiple layers. For example, it may have a multilayer structure including a lower layer and an upper layer, wherein the lower layer includes titanium and the upper layer includes copper.

[0134] At least one of the buffer layer 111, the first insulating layer 120, the second insulating layer 160, and the third insulating layer 180 may include an inorganic insulating material (such as silicon nitride (SiN)). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and / or organic insulating materials (such as polyimide, acryloyl polymers and siloxane polymers).

[0135] A fourth conductive layer, including a first pixel electrode 191a, a second pixel electrode 191b, and a third pixel electrode 191c, may be disposed on the third insulating layer 180.

[0136] The pixel electrodes 191a, 191b, and 191c of each pixel PX1, PX2, and PX3 can be stacked with the upper storage electrode 1154. The third insulating layer 180 may include an opening 181 stacked with the pixel electrodes 191a, 191b, and 191c and the upper storage electrode 1154. Each pixel electrode 191a, 191b, and 191c can be connected to the upper storage electrode 1154 through the opening 181.

[0137] The first pixel electrode 191a of the first pixel PX1 can be stacked with a portion of transistors T1, T2, and T3 of the first pixel PX1. The first pixel electrode 191a can also be stacked with some transistors T1, T2, and T3 of pixels other than the first pixel PX1. For example, the first pixel electrode 191a can be stacked with the switching transistor T2 of the second pixel PX2. The second pixel electrode 191b of the second pixel PX can be stacked with some transistors T1, T2, and T3 of the second pixel PX2. The second pixel electrode 191b can also be stacked with some transistors T1, T2, and T3 of pixels other than the second pixel PX2. For example, the second pixel electrode 191b can be stacked with the driving transistor T1 and the initialization transistor T3 of the third pixel PX3. The third pixel electrode 191c of the third pixel PX3 can be stacked with some transistors T1, T2, and T3 of the third pixel PX3. The third pixel electrode 191c may be stacked with some of the transistors T1, T2, and T3 of the pixels other than the third pixel PX3. At least some of the first pixel electrode 191a, the second pixel electrode 191b, and the third pixel electrode 191c may be stacked with at least some of the first data line 171a, the second data line 171b, and the third data line 171c. For example, the third pixel electrode 191c may be stacked with the first data line 171a, the second data line 171b, and the third data line 171c.

[0138] In this exemplary embodiment, the transistors T1, T2, and T3 of each pixel PX1, PX2, and PX3 may be stacked with pixel electrodes 191a, 191b, and 191c, or they may not be stacked with pixel electrodes 191a, 191b, and 191c. That is, each pixel electrode 191a, 191b, and 191c may be stacked with other pixels.

[0139] The fourth conductive layer may further include a common voltage connection pattern 195. The common voltage connection pattern 195 may be superimposed on the common voltage line 170. The common voltage connection pattern 195 may be superimposed on the first common voltage auxiliary pattern 170a. The common voltage connection pattern 195 may be superimposed on the second common voltage auxiliary pattern 170b. The third insulating layer 180 may include an opening 183 superimposed on the second common voltage auxiliary pattern 170b and the common voltage connection pattern 195. The common voltage connection pattern 195 can be connected to the second common voltage auxiliary pattern 170b through the opening 183. The planar shape of the common voltage connection pattern 195 may be composed of approximately polygonal shapes. For example, the common voltage connection pattern 195 may have a combination of rod shapes protruding from one edge of an octagon to an octagonal planar shape. The octagonal portion of the common voltage connection pattern 195 may be disposed at the intersection of the common voltage line 170 and the auxiliary common voltage line 170c. The rod-shaped portion of the common voltage connection pattern 195 can be superimposed with the common voltage line 170, the first common voltage auxiliary pattern 170a, and the second common voltage auxiliary pattern 170b.

[0140] The common voltage connection pattern 195 can be superimposed on the auxiliary common voltage line 170c. In the above description, the common voltage connection pattern 195 is connected to the second common voltage auxiliary pattern 170b, but is not limited thereto. An opening can be formed in the third insulating layer 180 at the portion where the common voltage connection pattern 195 and the auxiliary common voltage line 170c overlap, and the common voltage connection pattern 195 can be connected to the auxiliary common voltage line 170c through such an opening. That is, the common voltage line 170, the first common voltage auxiliary pattern 170a, the second common voltage auxiliary pattern 170b, the auxiliary common voltage line 170c, and the common voltage connection pattern 195 can be connected by various methods. The common voltage line 170, the first common voltage auxiliary pattern 170a, the second common voltage auxiliary pattern 170b, the auxiliary common voltage line 170c, and the common voltage connection pattern 195 can be directly or indirectly connected to each other, and a common voltage ELVSS can be applied to them.

[0141] A fourth insulating layer 350 may be disposed on the fourth conductive layer. The fourth insulating layer 350 may include an organic insulating material such as a polyacrylic resin or a polyimide resin. The fourth insulating layer 350 may include an opening 351 superimposed on the respective pixel electrodes 191a, 191b, and 191c.

[0142] The emission layer 370 may be disposed on the fourth insulating layer 350 and the pixel electrodes 191a, 191b, and 191c. The emission layer 370 may be disposed within the opening 351 of the fourth insulating layer 350. The emission layer 370 may comprise an organic or inorganic emission material. Although the emission layer 370 is shown as being integrally formed on the substrate 110, it is not limited thereto. The emission layer 370 may also be disposed only within the opening 351 of the fourth insulating layer 350.

[0143] A common electrode 270 can be disposed on the emitter layer 370. The common electrode 270 can be formed on the entire substrate 110. That is, a common electrode 270 can be positioned across multiple pixels PX1, PX2, and PX3. The common electrode 270 can be superimposed on a common voltage connection pattern 195. The emitter layer 370 may include an opening 352 superimposed on the common electrode 270 and the common voltage connection pattern 195. The opening 352 can also be formed in the fourth insulating layer 350. The opening 352 can be formed by a laser drilling process. After the emitter layer 370 is formed, some areas of the emitter layer 370 and the fourth insulating layer 350 can be removed by irradiating the common voltage connection pattern 195 with a laser to form the opening 352.

[0144] The common electrode 270 can be connected to the common voltage connection pattern 195 through the opening 352. The common electrode 270 can be connected to the common voltage line 170 through the common voltage connection pattern 195. The common electrode 270 can be directly / indirectly connected to the common voltage line 170, the first common voltage auxiliary pattern 170a, the second common voltage auxiliary pattern 170b, the auxiliary common voltage line 170c, and the common voltage connection pattern 195. A common voltage ELVSS can be applied to the common electrode 270.

[0145] The common electrode 270 may be stacked with data lines 171a, 171b, and 171c. Parasitic capacitors may be formed at the portions of each data line 171a, 171b, and 171c that are stacked with the common electrode 270. In this exemplary embodiment, the data lines 171a, 171b, and 171c are disposed in a first conductive layer. A first insulating layer 120, a second insulating layer 160, a third insulating layer 180, and a fourth insulating layer 350 may be disposed between the data lines 171a, 171b, and 171c and the common electrode 270. However, in the region that overlaps with the opening 351 of the fourth insulating layer 350, the first insulating layer 120, the second insulating layer 160, and the third insulating layer 180 are disposed between the data lines 171a, 171b, and 171c and the common electrode 270. In contrast, when data lines 171a, 171b, and 171c are disposed in the third conductive layer, the third insulating layer 180 and the fourth insulating layer 350 are disposed between the data lines 171a, 171b, and 171c and the common electrode 270. In this exemplary embodiment, the distance between the data lines 171a, 171b, and 171c and the common electrode 270 is relatively long compared to when the data lines 171a, 171b, and 171c are disposed in the third conductive layer, thereby reducing the capacitance of the parasitic capacitor. Furthermore, the design that minimizes the area of ​​the opening 351 of the fourth insulating layer 350 in the region where the data lines 171a, 171b, and 171c overlap with the common electrode 270 can further reduce the capacitance of the parasitic capacitor.

[0146] At least one of the fourth conductive layer and the common electrode 270 may be made of a transparent metal oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0147] The pixel electrodes 191a, 191b, and 191c of each pixel PX1, PX2, and PX3, together with the emitter layer 370 and the common electrode 270, can form a light-emitting diode (LED). The pixel electrodes 191a, 191b, and 191c can be anodes, and the common electrode 270 can be cathode.

[0148] Next, refer to Figure 11 Describes the amount of capacitance reduction of a parasitic capacitor in a display device according to an exemplary embodiment.

[0149] Figure 11 This is a graph showing the variation in capacitance of parasitic capacitors in a display device. The horizontal axis represents the size of the display device, and the vertical axis represents the capacitance of parasitic capacitors formed by the stacking of data lines and another conductive layer throughout the display device. Figure 11 The variations in the capacitance of the parasitic capacitors in the display device according to an exemplary embodiment and the display device according to a comparative example are illustrated. In the display device according to the exemplary embodiment, data lines are disposed in a first conductive layer, and first scan lines and second scan lines are disposed in a third conductive layer. In the display device according to the comparative example, first scan lines and second scan lines are disposed in a second conductive layer, and data lines are disposed in a third conductive layer. In both the display device according to the exemplary embodiment and the display device according to the comparative example, the common electrode is formed at the same location as the uppermost layer.

[0150] In the display device according to the exemplary embodiment and the display device according to the comparative example, the capacitance of the parasitic capacitor tends to increase as the size of the display device increases. The larger the size of the display device, the larger the area of ​​the data lines stacked with other conductive layers, thereby increasing the capacitance of the parasitic capacitor. When the size of the display device is 65 inches, the capacitance of the parasitic capacitor in the display device according to the comparative example is 420 pF, and the capacitance of the parasitic capacitor in the display device according to the exemplary embodiment is 250 pF. In the display device according to the exemplary embodiment, the capacitance of the parasitic capacitor can be reduced by approximately 170 pF by placing the data lines in the first conductive layer and placing the first scan lines and the second scan lines in the third conductive layer. When the size of the display device is 75 inches, the capacitance of the parasitic capacitor in the display device according to the comparative example is 550 pF, and the capacitance of the parasitic capacitor in the display device according to the exemplary embodiment is 320 pF. Compared to the display device according to the comparative example, the capacitance of the parasitic capacitor in the display device according to the exemplary embodiment can be reduced by approximately 230 pF. It can be confirmed that, according to the exemplary embodiments, the larger the size of the display device, the greater the effect of reducing the capacitance of the parasitic capacitors in the display device. When the size of the display device is 98 inches, the capacitance of the parasitic capacitors in the display device according to the comparative example is 960 pF, while the capacitance of the parasitic capacitors in the display device according to the exemplary embodiments is 570 pF. Compared with the display device according to the comparative example, the capacitance of the parasitic capacitors in the display device according to the exemplary embodiments can be reduced by approximately 390 pF.

[0151] Next, refer to Figure 12 and Figure 13 A display device according to an exemplary embodiment is described.

[0152] according to Figure 12 and Figure 13 The display device of the exemplary embodiment shown herein and according to Figures 1 to 10 The display devices shown in the exemplary embodiments are largely the same, therefore descriptions of identical parts are omitted. In this exemplary embodiment, the connection structure of the data lines and the switching transistors differs from the connection structure of the preceding exemplary embodiments, and this will be described further.

[0153] Figure 12 This is a top plan view showing a portion of a display device according to an exemplary embodiment. Figure 13 It is along Figure 12 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XIII-XIII'.

[0154] like Figure 12 and Figure 13As shown, the first data line 171a, the second data line 171b, and the third data line 171c are disposed on the substrate 110. The first electrode 2131 of the switching transistor T2 of each pixel PX1, PX2, and PX3 can be stacked with each data line 171a, 171b, and 171c. The first connection electrode 178 of each pixel PX1, PX2, and PX3 can be stacked with each data line 171a, 171b, and 171c and the first electrode 2131 of the switching transistor T2.

[0155] In the preceding exemplary embodiments, openings 161 for connecting the first connection electrode 178 to data lines 171a, 171b, and 171c and 162 for connecting the first connection electrode 178 to the first electrode 2131 of the switching transistor T2 were formed separately. In this exemplary embodiment, a single opening 1167 is formed for connecting the first connection electrode 178, data lines 171a, 171b, and 171c, and the first electrode 2131 of the switching transistor T2. Opening 1167 may be stacked with the first connection electrode 178, data lines 171a, 171b, and 171c, and the first electrode 2131 of the switching transistor T2. Opening 1167 may be formed in a buffer layer 111, a first insulating layer 120, and a second insulating layer 160. The upper surfaces of data lines 171a, 171b, and 171c and the side surfaces of the first electrode 2131 of the switching transistor T2 may be exposed by opening 1167. The first connection electrode 178 can be formed to fill the opening 1167. The first connection electrode 178 can be connected to the data lines 171a, 171b and 171c, and can also be connected to the first electrode 2131 of the switching transistor T2. That is, the first connection electrode 178 can connect the data lines 171a, 171b and 171c to the first electrode 2131 of the switching transistor T2.

[0156] In the display device according to this exemplary embodiment, similar to the previous exemplary embodiments, by placing the data lines in the first conductive layer and placing the first scan lines and the second scan lines in the third conductive layer, the capacitance of the parasitic capacitor formed by stacking the data lines with other conductive layers can be reduced.

[0157] Next, refer to Figure 14 and Figure 15 A display device according to an exemplary embodiment is described.

[0158] according to Figure 14 and Figure 15 The display device of the exemplary embodiment shown herein and according to Figures 1 to 10The display devices shown in the exemplary embodiments are largely the same, therefore descriptions of identical parts are omitted. In this exemplary embodiment, the layer in which the auxiliary common voltage line is formed differs from the previous exemplary embodiments, and it is further described below.

[0159] Figure 14 This is a top plan view showing a portion of a display device according to an exemplary embodiment. Figure 15 It is along Figure 14 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XV-XV'.

[0160] like Figure 14 and Figure 15 As shown, a first conductive layer including a first data line 171a, a second data line 171b, a third data line 171c, and a common voltage line 170 is disposed on a substrate 110. The first data line 171a, the second data line 171b, the third data line 171c, and the common voltage line 170 may extend in a first direction D1.

[0161] The first common voltage auxiliary pattern 170a and the second common voltage auxiliary pattern 170b can be configured to be superimposed on the common voltage line 170. The first common voltage auxiliary pattern 170a and the second common voltage auxiliary pattern 170b can be disposed in different layers. For example, the first common voltage auxiliary pattern 170a can be disposed in a second conductive layer, and the second common voltage auxiliary pattern 170b can be disposed in a third conductive layer. The common voltage connection pattern 195 can be superimposed on the common voltage line 170. The common voltage connection pattern 195 can be disposed in a fourth conductive layer. The common voltage line 170, the first common voltage auxiliary pattern 170a, the second common voltage auxiliary pattern 170b, and the common voltage connection pattern 195 can be directly or indirectly connected to each other, and a common voltage ELVSS can be applied to them.

[0162] The auxiliary common voltage line 170c can be configured to intersect with the common voltage line 170. The auxiliary common voltage line 170c can extend in the second direction D2. In the previous exemplary embodiment, the auxiliary common voltage line 170c can be disposed in the third conductive layer, while in this exemplary embodiment, the auxiliary common voltage line 170c can be disposed in the fourth conductive layer. In this exemplary embodiment, the auxiliary drive voltage line 172c can be omitted. In the previous exemplary embodiment, the auxiliary common voltage line 170c and the auxiliary drive voltage line 172c are alternately disposed, while in this exemplary embodiment, the auxiliary drive voltage line 172c is omitted, and only the auxiliary common voltage line 170c can be disposed. The auxiliary common voltage line 170c can be disposed between the first scan line 151 and the second scan line 152. The auxiliary common voltage line 170c can intersect with the data lines 171a, 171b, and 171c, and they overlap each other at their intersection points, thereby creating parasitic capacitors. In this exemplary embodiment, since data lines 171a, 171b, and 171c are disposed in the first conductive layer, while the auxiliary common voltage line 170c is disposed in the fourth conductive layer, the capacitance of the parasitic capacitor can be further reduced compared to the previous exemplary embodiment.

[0163] The auxiliary common voltage line 170c can be connected to the common voltage connection pattern 195 and can be integrally formed with the common voltage connection pattern 195. For example, the common voltage connection pattern 195 can have a shape that protrudes from the auxiliary common voltage line 170c in a plane.

[0164] In the display device according to this exemplary embodiment, similar to the previous exemplary embodiment, the data lines are disposed in the first conductive layer, while the first scan lines and the second scan lines are disposed in the third conductive layer, so that the capacitance of the parasitic capacitor caused by the stacking of the data lines with other conductive layers can be reduced.

[0165] Next, refer to Figure 16 and Figure 17 A display device according to an exemplary embodiment is described. Specifically, a parasitic capacitor between a data line and a common electrode is described.

[0166] Figure 16 This is a top plan view showing some of the constituent elements of a display device according to an exemplary embodiment. Figure 17 It is along Figure 16 A cross-sectional view of the display device according to an exemplary embodiment, taken by lines XVII-XVII'. Figure 16 and Figure 17 The basis was omitted. Figures 1 to 10 The exemplary embodiment shown illustrates a display device with scan lines, drive voltage lines, transistors, etc., and also shows some constituent elements such as data lines, pixel electrodes, emitter layers, common electrodes, etc.

[0167] like Figure 16 and Figure 17 As shown, a first data line 171a, a second data line 171b, and a third data line 171c can be disposed on a substrate 110. The first data line 171a, the second data line 171b, and the third data line 171c can extend along a first direction D1 and are configured to be adjacent along a second direction D2.

[0168] Multiple pixels PX1, PX2, and PX3 can include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 can be a pixel that displays blue, the second pixel PX2 can be a pixel that displays green, and the third pixel PX3 can be a pixel that displays red.

[0169] Each pixel PX1, PX2, and PX3 may include pixel electrodes 191a, 191b, and 191c. A buffer layer 111, a first insulating layer 120, a second insulating layer 160, and a third insulating layer 180 may be disposed between the substrate 110 and the pixel electrodes 191a, 191b, and 191c.

[0170] A fourth insulating layer 350 may be disposed on pixel electrodes 191a, 191b, and 191c. The fourth insulating layer 350 may include an opening 351 superimposed on the pixel electrodes 191a, 191b, and 191c. An emitting layer 370 may be disposed on the pixel electrodes 191a, 191b, and 191c and the fourth insulating layer 350. A common electrode 270 may be located on the emitting layer 370. The pixel electrodes 191a, 191b, and 191c, the emitting layer 370, and the common electrode 270 together can form a light-emitting diode (LED). Light can be emitted in the region corresponding to the opening 351. At the edge of the opening 351, the fourth insulating layer 350 has a tapered shape, so that the light-emitting regions LR, LG, and LB in which light is actually detected can be larger than the area of ​​the opening 351. The light-emitting regions LR, LG, and LB may include a red light-emitting region LR, a green light-emitting region LG, and a blue light-emitting region LB. The red emitting area LR can be an area displaying red light, the green emitting area LG can be an area displaying green light, and the blue emitting area LB can be an area displaying blue light. The emission layer 370 is individually configured for each pixel PX1, PX2, and PX3 to emit red, green, and blue light. Optionally, the emission layer 370 can be formed as a whole to emit blue light, or separate color conversion layers can be configured to emit red, green, and blue light for each pixel PX1, PX2, and PX3.

[0171] In this exemplary embodiment, the first pixel electrode 191a can be stacked with the blue light-emitting region LB, the second pixel electrode 191b can be stacked with the green light-emitting region LG, and the third pixel electrode 191c can be stacked with the red light-emitting region LR.

[0172] In this exemplary embodiment, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the red light-emitting region LR. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the green light-emitting region LG and the blue light-emitting region LB. However, this is merely an example, and the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB can be varied. Furthermore, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the third pixel electrode 191c. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the first pixel electrode 191a and the second pixel electrode 191b. However, this is merely an example, and the arrangement of the first pixel electrode 191a, the second pixel electrode 191b, and the third pixel electrode 191c can also be varied depending on the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB.

[0173] Buffer layer 111, first insulating layer 120, second insulating layer 160, and third insulating layer 180 may be disposed between the first data line 171a, second data line 171b, and third data line 171c and the common electrode 270. Additionally, a fourth insulating layer 350 may be disposed in a portion not overlapping with opening 351 between the first data line 171a, second data line 171b, and third data line 171c and the common electrode 270.

[0174] In the display device according to this exemplary embodiment, compared to the case where data lines 171a, 171b, and 171c are disposed in the third conductive layer, the distance between data lines 171a, 171b, and 171c and the common electrode 270 is relatively long, which allows the capacitance of the parasitic capacitor to be reduced. Furthermore, in the display device according to this exemplary embodiment, since the first data line 171a, the second data line 171b, and the third data line 171c are superimposed on the red light-emitting region LR but not on the green light-emitting region LG and the blue light-emitting region LB, the area occupied by the fourth insulating layer 350 between the first data line 171a, the second data line 171b, and the third data line 171c and the common electrode 270 is widened, thereby further reducing the capacitance of the parasitic capacitor.

[0175] Next, refer to Figure 18 and Figure 19 A display device according to an exemplary embodiment is described.

[0176] according to Figure 18 and Figure 19 The display device of the exemplary embodiment shown herein and according to Figure 16 and Figure 17The display devices shown in the exemplary embodiments are largely the same, therefore descriptions of identical parts are omitted. In this exemplary embodiment, the arrangement of the light-emitting areas differs from the previous exemplary embodiments, and this arrangement is further described below.

[0177] Figure 18 This is a top plan view showing partial constituent elements of a display device according to an exemplary embodiment. Figure 19 It is along Figure 18 A cross-sectional view of a display device according to an exemplary embodiment, taken by line XIX-XIX'. Figure 18 and Figure 19 The basis was omitted. Figures 1 to 10 The exemplary embodiment shown illustrates a display device with scan lines, drive voltage lines, transistors, etc., and also shows some constituent elements such as data lines, pixel electrodes, emitter layers, common electrodes, etc.

[0178] like Figure 18 and Figure 19 As shown, a first data line 171a, a second data line 171b, and a third data line 171c can be disposed on a substrate 110. The first data line 171a, the second data line 171b, and the third data line 171c can extend along a first direction D1 and are configured to be adjacent along a second direction D2.

[0179] Multiple pixels PX1, PX2, and PX3 can include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 can be a green pixel, the second pixel PX2 can be a blue pixel, and the third pixel PX3 can be a red pixel.

[0180] Each pixel PX1, PX2, and PX3 may include pixel electrodes 191a, 191b, and 191c. A buffer layer 111, a first insulating layer 120, a second insulating layer 160, and a third insulating layer 180 may be disposed between the substrate 110 and the pixel electrodes 191a, 191b, and 191c.

[0181] A fourth insulating layer 350 may be disposed on pixel electrodes 191a, 191b, and 191c. The fourth insulating layer 350 may include an opening 351 superimposed on the pixel electrodes 191a, 191b, and 191c. An emitting layer 370 may be disposed on the pixel electrodes 191a, 191b, and 191c and the fourth insulating layer 350. A common electrode 270 may be disposed on the emitting layer 370. The pixel electrodes 191a, 191b, and 191c, the emitting layer 370, and the common electrode 270 together can form a light-emitting diode (LED). Light can be emitted in the region corresponding to the opening 351. At the edge of the opening 351, the fourth insulating layer 350 has a tapered shape, so that the light-emitting regions LR, LG, and LB that are actually visible can be larger than the area of ​​the opening 351. The light-emitting regions LR, LG, and LB may include a red light-emitting region LR, a green light-emitting region LG, and a blue light-emitting region LB. The red emitting area LR can be an area displaying red light, the green emitting area LG can be an area displaying green light, and the blue emitting area LB can be an area displaying blue light. The emission layer 370 is individually configured for each pixel PX1, PX2, and PX3 to emit red, green, and blue light. Optionally, the emission layer 370 can be formed as a whole to emit blue light, and separate color conversion layers can be configured for each pixel PX1, PX2, and PX3 to emit red, green, and blue light.

[0182] In the exemplary embodiment described above, the blue emitting region LB is located at the upper center on the plane, the green emitting region LG is located at the lower left, and the red emitting region LR is located at the lower right. In this exemplary embodiment, the arrangement of the emitting regions LR, LG, and LB on the plane is similar to rotating the previous exemplary embodiment by approximately 90 degrees clockwise. That is, the blue emitting region LB can be located at the right center on the plane, the green emitting region LG can be located at the upper left, and the red emitting region LR can be located at the lower left.

[0183] In this exemplary embodiment, the first pixel electrode 191a can be stacked with the green light-emitting region LG, the second pixel electrode 191b can be stacked with the blue light-emitting region LB, and the third pixel electrode 191c can be stacked with the red light-emitting region LR.

[0184] In this exemplary embodiment, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the blue light-emitting region LB. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the red light-emitting region LR and the green light-emitting region LG. However, this is merely an example, and the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB can be varied. Furthermore, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the second pixel electrode 191b. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the first pixel electrode 191a and the third pixel electrode 191c. However, this is merely an example, and the arrangement of the first pixel electrode 191a, the second pixel electrode 191b, and the third pixel electrode 191c can also be varied depending on the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB.

[0185] Buffer layer 111, first insulating layer 120, second insulating layer 160, and third insulating layer 180 may be disposed between the first data line 171a, second data line 171b, and third data line 171c and the common electrode 270. Additionally, a fourth insulating layer 350 may be disposed in a portion not overlapping with opening 351 between the first data line 171a, second data line 171b, and third data line 171c and the common electrode 270.

[0186] In the display device according to this exemplary embodiment, compared to the case where data lines 171a, 171b, and 171c are disposed in the third conductive layer, the distance between data lines 171a, 171b, and 171c and the common electrode 270 is relatively long, thereby reducing the capacitance of the parasitic capacitor. Furthermore, in the display device according to this exemplary embodiment, since the first data line 171a, the second data line 171b, and the third data line 171c are superimposed on the blue light-emitting region LB but not on the red light-emitting region LR and the green light-emitting region LG, the area where the fourth insulating layer 350 is disposed between the first data line 171a, the second data line 171b, and the third data line 171c and the common electrode 270 is increased, thereby further reducing the capacitance of the parasitic capacitor. The size of the blue light-emitting region LB is relatively smaller than the sizes of the red light-emitting region LR and the green light-emitting region LG. In this exemplary embodiment, the first data line 171a, the second data line 171b, and the third data line 171c are superimposed only on the blue light-emitting region LB. Therefore, compared with the case where the first data line 171a, the second data line 171b, and the third data line 171c are superimposed on the red light-emitting region LR or the green light-emitting region LG, the capacitance of the parasitic capacitor can be further reduced.

[0187] Next, refer to Figure 20 A display device according to an exemplary embodiment is described.

[0188] according to Figure 20 The display device of the exemplary embodiment shown herein and according to Figure 18 and Figure 19 The display device shown in the exemplary embodiments is largely the same, therefore descriptions of identical portions are omitted. In this exemplary embodiment, the arrangement of the light-emitting areas differs from the previous exemplary embodiments, and this arrangement is further described below.

[0189] Figure 20 This is a top plan view showing some of the constituent elements of a display device according to an exemplary embodiment.

[0190] like Figure 20 As shown, the first data line 171a, the second data line 171b, and the third data line 171c can be disposed on the substrate 110. The first data line 171a, the second data line 171b, and the third data line 171c can extend along a first direction D1 and are configured to be adjacent along a second direction D2.

[0191] Multiple pixels PX1, PX2, and PX3 can include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 can be a pixel that displays red, the second pixel PX2 can be a pixel that displays blue, and the third pixel PX3 can be a pixel that displays green.

[0192] In the exemplary embodiment described above, on the plane, the blue emitting region LB is located at the right center, the green emitting region LG is located at the upper left, and the red emitting region LR is located at the lower left. In this exemplary embodiment, the positions of the blue emitting region LB are the same, while the positions of the green emitting region LG and the red emitting region LR can be interchanged. That is, on the plane, the blue emitting region LB can be located at the right center, the green emitting region LG can be located at the lower left, and the red emitting region LR can be located at the upper left.

[0193] In this exemplary embodiment, the first pixel electrode 191a can be stacked with the red light-emitting region LR, the second pixel electrode 191b can be stacked with the blue light-emitting region LB, and the third pixel electrode 191c can be stacked with the green light-emitting region LG.

[0194] In this exemplary embodiment, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the blue light-emitting region LB. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the red light-emitting region LR and the green light-emitting region LG. However, this is merely an example, and the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB can be varied. Furthermore, the first data line 171a, the second data line 171b, and the third data line 171c may be superimposed on the second pixel electrode 191b. The first data line 171a, the second data line 171b, and the third data line 171c may not be superimposed on the first pixel electrode 191a and the third pixel electrode 191c. However, this is merely an example, and the arrangement of the first pixel electrode 191a, the second pixel electrode 191b, and the third pixel electrode 191c can also be varied depending on the arrangement of the red light-emitting region LR, the green light-emitting region LG, and the blue light-emitting region LB.

[0195] In the display device according to this exemplary embodiment, compared to the case where data lines 171a, 171b, and 171c are disposed in the third conductive layer, the distance between data lines 171a, 171b, and 171c and the common electrode 270 is relatively long, thereby reducing the capacitance of the parasitic capacitor. Furthermore, in the display device according to this exemplary embodiment, since the first data line 171a, the second data line 171b, and the third data line 171c are superimposed on the blue light-emitting region LB but not on the red light-emitting region LR and the green light-emitting region LG, the area where the fourth insulating layer 350 is disposed between the first data line 171a, the second data line 171b, and the third data line 171c and the common electrode 270 is increased, thereby further reducing the capacitance of the parasitic capacitor. The size of the blue light-emitting region LB is relatively smaller than the sizes of the red light-emitting region LR and the green light-emitting region LG. In this exemplary embodiment, the first data line 171a, the second data line 171b, and the third data line 171c are superimposed only on the blue light-emitting region LB. Therefore, compared with the case where the first data line 171a, the second data line 171b, and the third data line 171c are superimposed on the red light-emitting region LR or the green light-emitting region LG, the capacitance of the parasitic capacitor can be further reduced.

[0196] Next, refer to Figure 21 A cross-sectional structure of the display device according to an exemplary embodiment is further described below. (Refer to...) Figures 1 to 10 Describe them together. Previously, in Figures 1 to 10 The section explains that the common electrode is positioned on the top layer. Another layer can be further positioned on top of the common electrode, which will be described below.

[0197] Figure 21This is a cross-sectional view of some constituent elements of a display device according to an exemplary embodiment. Figure 21 In, and according to Figures 1 to 10 Compared to the display device of the exemplary embodiment shown, scan lines, drive voltage lines, transistors, etc., are omitted, and some constituent elements such as pixel electrodes, emitter layers, and common electrodes are shown. Additionally, Figure 21 Another layer is also shown, positioned above the common electrode.

[0198] like Figure 21 As shown, the display device according to an exemplary embodiment may include a plurality of pixels PX1, PX2, and PX3. Pixel electrodes 191a, 191b, and 191c may be disposed on the substrate 110 for each pixel PX1, PX2, and PX3. The plurality of transistors and insulating layers disposed between the substrate 110 and the pixel electrodes 191a, 191b, and 191c are omitted, but for example, as shown... Figures 1 to 10 The location is shown in the diagram.

[0199] A fourth insulating layer 350 may be disposed on pixel electrodes 191a, 191b, and 191c, and the fourth insulating layer 350 may include an opening 351. An emitting layer 370 may be disposed on pixel electrodes 191a, 191b, and 191c and the fourth insulating layer 350, and a common electrode 270 may be disposed on the emitting layer 370. The emitting layer 370 may include a light-emitting material that emits a first color of light, which may be blue light.

[0200] An encapsulation layer 380, comprising multiple insulating layers 381, 382, ​​and 383, may be disposed on the common electrode 270. Insulating layers 381 and 383 may comprise inorganic insulating materials, and insulating layer 382 disposed between insulating layers 381 and 383 may comprise organic insulating materials.

[0201] A filler layer 390, including filler material, can be disposed on the encapsulation layer 380. A cover layer 400, including insulating material, multiple color conversion layers 430a and 430b, and a transmissive layer 430c, can be disposed on the filler layer 390.

[0202] The transmissive layer 430c allows incident light to pass through. Specifically, the transmissive layer 430c can transmit a first color of light, which may be blue light. The transmissive layer 430c may comprise a polymer material that transmits the first color of light. The region where the transmissive layer 430c is disposed may correspond to the light-emitting region emitting blue light, and the transmissive layer 430c allows incident first color light to pass through without including individual semiconductor nanocrystals.

[0203] Color conversion layers 430a and 430b may include different semiconductor nanocrystals. For example, first-color light incident on color conversion layer 430a may be converted into second-color light and emitted by the semiconductor nanocrystals included in color conversion layer 430a. First-color light incident on color conversion layer 430b may be converted into third-color light and emitted by the semiconductor nanocrystals included in color conversion layer 430b.

[0204] Semiconductor nanocrystals may include at least one of phosphor materials and quantum dot materials that convert incident first color light into second color light or third color light.

[0205] The nucleus of a quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof.

[0206] Group II-VI compounds can be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof. Ternary compounds are selected from the group consisting of AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, C... The group consisting of dZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof, and the quaternary compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof.

[0207] III-V group compounds can be selected from the group consisting of binary, ternary and quaternary compounds. Binary compounds are selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof. Ternary compounds are selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb and mixtures thereof. Quaternary compounds are selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0208] Group IV-VI compounds can be selected from the group consisting of binary, ternary, and quaternary compounds. Binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof. Ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof. Quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements can be selected from the group consisting of Si, Ge, and mixtures thereof. Group IV compounds can be binary compounds selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0209] Binary, ternary, or quaternary compounds can exist in particles at a uniform concentration, or they can exist in the same particle where the concentration distribution can be partially divided into different states. Furthermore, they can have a core / shell structure in which one quantum dot surrounds another. The interface between the core and shell can have a concentration gradient in which the concentration of the element present in the shell decreases towards the center.

[0210] In some exemplary embodiments, the quantum dot may have a core-shell structure comprising a core comprising the aforementioned nanocrystals, and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and / or as a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. The interface between the core and shell may have a concentration gradient in which the concentration of elements present in the shell decreases toward the center. Examples of shells for quantum dots include metal oxides or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0211] For example, metal oxides or non-metal oxides may be exemplified as binary compounds (such as SiO2, Al2O3, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO) or ternary compounds (such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4), but the invention is not limited thereto.

[0212] Furthermore, semiconductor compounds may be exemplified as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, or AlSb, but the present invention is not limited thereto.

[0213] Quantum dots can have a full width at half maximum (FWHM) of about 45 nm or less, preferably about 40 nm or less, more preferably about 30 nm or less, and within this range, color purity or color reproducibility can be improved. Furthermore, since light emitted through quantum dots is emitted in all directions, a wide viewing angle can be improved.

[0214] In addition, the shape of quantum dots is not specifically limited to the types commonly used in this field, but more specifically, it can be spherical nanoparticles, pyramidal nanoparticles, multi-armed nanoparticles, cubic nanoparticles, nanotubes, nanowires, nanofibers, and nanoplate particles, etc.

[0215] Quantum dots can control the color of emitted light based on their particle size; therefore, quantum dots can have a variety of emission colors such as blue, red, and green.

[0216] An insulating layer 440 may be disposed on multiple color conversion layers 430a and 430b and a transmission layer 430c, and multiple color filters 450a, 450b and 450c and a light blocking member 460 may be disposed on the insulating layer 440.

[0217] Color filter 450a can display the second color of light, color filter 450b can display the third color of light, and color filter 450c can display the first color of light.

[0218] The light-blocking component 460 can be disposed between adjacent color filters 450a, 450b and 450c.

[0219] The substrate 210 can be disposed on multiple color filters 450a, 450b and 450c and light blocking member 460. That is, multiple color conversion layers 430a and 430b, a transmission layer 430c and multiple color filters 450a, 450b and 450c can be disposed between the substrate 110 and the substrate 210.

[0220] According to another exemplary embodiment, instead of including a plurality of color conversion layers 430a and 430b and a transmission layer 430c, the emission layer 370 may include quantum dots.

[0221] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising: Base; The first data line, the second data line, and the third data line extend on the substrate in a first direction and are configured to be adjacent to each other along a second direction that intersects the first direction; A semiconductor layer is disposed on the first data line, the second data line, and the third data line; A first insulating layer is disposed on the semiconductor layer; The first lower storage electrode, the second lower storage electrode, and the third lower storage electrode are disposed on the first insulating layer and are arranged to be adjacent to each other along the first direction; A second insulating layer is disposed on the first lower storage electrode, the second lower storage electrode, and the third lower storage electrode; The first scan line extends in the second direction on the second insulating layer; The first pixel is connected to the first scan line and the first data line; The second pixel is connected to the first scan line and the second data line; as well as The third pixel is connected to the first scan line and the third data line.

2. The display device according to claim 1, further comprising: A first auxiliary scanning pattern is superimposed on the first scanning line and connected to the first scanning line. The first auxiliary scanning pattern is disposed on the same layer as the first lower storage electrode and is not superimposed on the first data line, the second data line and the third data line.

3. The display device according to claim 1, further comprising: The first upper storage electrode is stacked with the first lower storage electrode; The second upper storage electrode is stacked with the second lower storage electrode; as well as The third upper storage electrode is stacked with the third lower storage electrode. The first upper storage electrode, the second upper storage electrode, and the third upper storage electrode are arranged sequentially along the first direction and are disposed on the same layer as the first scan line.

4. The display device according to claim 3, further comprising: A first light-blocking layer is stacked with the first lower storage electrode; The second light-blocking layer is stacked with the second lower storage electrode; as well as The third light-blocking layer is stacked with the third lower storage electrode. The first light-blocking layer, the second light-blocking layer, and the third light-blocking layer are arranged sequentially along the first direction and are disposed on the same layer as the first data line, the second data line, and the third data line.

5. The display device according to claim 3, further comprising: The driving voltage line and the initialization voltage line extend in the first direction. The first pixel includes a first driving transistor, a first switching transistor, and a first initialization transistor. The first driving transistor is connected between the driving voltage line and the first upper storage electrode, the first switching transistor is connected between the first lower storage electrode and the first data line, and the first initialization transistor is connected between the initialization voltage line and the first upper storage electrode. The second pixel includes a second driving transistor, a second switching transistor, and a second initialization transistor. The second driving transistor is connected between the driving voltage line and the second upper storage electrode, the second switching transistor is connected between the second lower storage electrode and the second data line, and the second initialization transistor is connected between the initialization voltage line and the second upper storage electrode. The third pixel includes a third driving transistor, a third switching transistor, and a third initialization transistor. The third driving transistor is connected between the driving voltage line and the third upper storage electrode. The third switching transistor is connected between the third lower storage electrode and the third data line. The third initialization transistor is connected between the initialization voltage line and the third upper storage electrode.

6. The display device according to claim 5, wherein, The first driving transistor, the second driving transistor, and the third driving transistor are arranged sequentially along the first direction. The first switching transistor, the second switching transistor, and the third switching transistor are arranged sequentially along the first direction and connected to the first scan line. The first initialization transistor, the second initialization transistor, and the third initialization transistor are arranged sequentially along the first direction.

7. The display device according to claim 5, further comprising: The second scan line extends in the second direction. The second scan line is disposed on the same layer as the first scan line and is connected to the first initialization transistor, the second initialization transistor and the third initialization transistor.

8. The display device according to claim 7, further comprising: A second auxiliary scanning pattern is superimposed on the second scanning line and connected to the second scanning line. The second auxiliary scanning pattern is disposed on the same layer as the first lower storage electrode and is not superimposed on the first data line, the second data line and the third data line.

9. The display device according to claim 5, further comprising: A third insulating layer is disposed on the first scan line. The first pixel further includes a first pixel electrode disposed on the third insulating layer and connected to the first driving transistor, and The first pixel electrode is stacked with the second pixel or the third pixel.

10. The display device according to claim 9, further comprising: A common voltage line extends in the first direction and is disposed on the same layer as the first data line; A common voltage connection pattern is connected to the common voltage line and is disposed on the same layer as the first pixel electrode; An emission layer is disposed on the first pixel electrode; as well as A common electrode is disposed on the emitter layer and connected to the common voltage connection pattern.

11. The display device according to claim 10, further comprising: An auxiliary common voltage line extends in the second direction, is disposed on the same layer as the first scan line, and is connected to the common voltage line.

12. The display device according to claim 11, further comprising: An auxiliary driving voltage line extends in the second direction, is disposed on the same layer as the first scan line, and is connected to the driving voltage line.

13. The display device according to claim 10, further comprising: An auxiliary common voltage line extends from the common voltage connection pattern and is disposed on the same layer as the first pixel electrode.

14. The display device according to claim 9, wherein, The second pixel also includes a second pixel electrode connected to the second driving transistor. The third pixel also includes a third pixel electrode connected to the third driving transistor, and The data line is superimposed on one of the first pixel electrode, the second pixel electrode, and the third pixel electrode, but not on the remaining pixel electrodes.

15. The display device according to claim 5, further comprising: Connect the electrodes to connect the first data line to the first switching transistor. The connecting electrode and the first scan line are disposed on the same layer.

16. The display device according to claim 15, wherein, The second insulating layer includes a single opening stacked with the connection electrode, the first data line, and the first switching transistor. The connection electrode is connected to the first data line and the first switching transistor through the opening, and The connection electrode contacts the side surface of the first switching transistor in the opening.

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