Display device and repairing method thereof

Abstract

A display device includes a substrate; a scan line disposed on the substrate; a storage line parallel to the scan line; a data line intersecting the scan line and the storage line; a first transistor and a second transistor connected to the scan line and the data line; a first pixel electrode disposed on the first transistor and including a first stem portion parallel to the data line, a first contact portion connected to the first transistor, and a first branch portion connecting the first contact portion and the first stem portion; a second pixel electrode disposed on the second transistor, spaced apart from the first pixel electrode in a planar view, and with the scan line provided between the second pixel electrode and the first pixel electrode, the second pixel electrode including a second stem portion parallel to the data line, a second contact portion connected to the second transistor, and a second branch portion connecting the second contact portion and the second stem portion; and a first pattern disposed between the substrate and the second pixel electrode and overlapping the second branch portion.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. In more detail, the present application relates to a liquid crystal display device and a repairing method of a liquid crystal display device. BACKGROUND

[0002] Display devices are increasing in importance as multimedia is developed. Accordingly, various types of display devices such as liquid crystal display (LCD), organic light emitting display (OLED), etc. are being used.

[0003] Among the display devices, the liquid crystal display device is one of the most widely used flat panel display devices at present. The liquid crystal display device can include two display panels each forming an electric field generating electrode and a liquid crystal layer interposed between the two display panels. A voltage is applied to the electric field generating electrode to generate an electric field in the liquid crystal layer, and thereby the orientation of liquid crystal molecules of the liquid crystal layer is determined, and the polarization of incident light is controlled, so that the liquid crystal display device can display an image.

[0004] In the process of manufacturing the liquid crystal display device, a defective pixel which can emit light in a black picture can be generated. Accordingly, a pixel electrode of the defective pixel can be set to a floating state so that the defective pixel cannot be recognized. However, in the process of cutting off the pixel electrode, an alignment layer can be damaged, and light leakage can be generated through the damaged alignment layer. SUMMARY

[0005] An object of the present application is to provide a display device and a repairing method of a display device which prevent light leakage due to a damaged alignment layer.

[0006] However, the objects of the present application are not limited to the above-described objects, and various extensions can be made within the scope of the idea and the field of the present application.

[0007] To achieve the aforementioned object of the present application, display devices according to various embodiments can include a substrate; a scan line disposed on the substrate; a storage line parallel to the scan line; a data line crossing the scan line and the storage line; a first transistor and a second transistor connected to the scan line and the data line; a first pixel electrode disposed on the first transistor and including a first trunk portion parallel to the data line, a first contact portion connected to the first transistor, and a first branch portion connecting the first contact portion and the first trunk portion; a second pixel electrode disposed on the second transistor, spaced apart from the first pixel electrode in a planar direction, and having the scan line disposed therebetween, the second pixel electrode including a second trunk portion parallel to the data line, a second contact portion connected to the second transistor, and a second branch portion connecting the second contact portion and the second trunk portion; and a first pattern disposed between the substrate and the second pixel electrode and overlapping the second branch portion.

[0008] In an embodiment, the first pattern can extend from the storage line.

[0009] In an embodiment, the first pattern can be symmetrical with the second trunk portion as a reference in a planar direction.

[0010] In an embodiment, the display device can further include a second pattern disposed between the substrate and the first pixel electrode and overlapping the first branch portion.

[0011] In an embodiment, the storage line can include a first extension portion and a second extension portion extending in parallel to the data line and spaced apart from each other, the first trunk portion being disposed between the first extension portion and the second extension portion, and the second pattern can extend from the first extension portion.

[0012] In an embodiment, the display device can further include a third pattern extending from the second extension portion and configured to be symmetrical with the second pattern with the first trunk portion as a reference in a planar direction.

[0013] In an embodiment, the display device can further include a third transistor connected to the scan line and the storage line.

[0014] In an embodiment, the display device can further include an alignment layer disposed on the first pixel electrode and the second pixel electrode.

[0015] In an embodiment, the display device can further include a common electrode disposed on the alignment layer, and a liquid crystal layer disposed between the alignment layer and the common electrode.

[0016] To achieve the aforementioned object of the present application, display devices according to various embodiments can include a substrate; a scan line disposed on the substrate; a storage line parallel to the scan line; a data line crossing the scan line and the storage line; a transistor including a gate electrode connected to the scan line, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode; a pixel electrode disposed on the transistor and including a trunk portion parallel to the data line, a contact portion connected to the drain electrode, and a branch portion connecting the contact portion and the trunk portion; and a first pattern disposed between the substrate and the pixel electrode and overlapping the branch portion.

[0017] In an embodiment, the first pattern can extend from the storage line.

[0018] In an embodiment, the first pattern can be symmetrical with the trunk portion as a reference on a plane.

[0019] In an embodiment, the storage line can include a first extension portion and a second extension portion extending in parallel to the data line and spaced apart from each other, the trunk portion being provided between the first extension portion and the second extension portion, and the first pattern can extend from the first extension portion.

[0020] In an embodiment, the display device can further include a second pattern extending from the second extension portion and configured to be symmetrical with the first pattern with the trunk portion as a reference on a plane.

[0021] In an embodiment, the display device can further include an alignment layer disposed on the pixel electrode.

[0022] To achieve the aforementioned object of the present application, there is provided a repairing method of a display device, the display device can include a substrate, a scan line disposed on the substrate, a storage line parallel to the scan line, a data line crossing the scan line and the storage line, a first transistor and a second transistor connected to the scan line and the data line, a first pixel electrode disposed on the first transistor and including a first stem portion parallel to the data line, a first contact portion connected to the first transistor, and a first branch portion connecting the first contact portion and the first stem portion, a second pixel electrode disposed on the second transistor, spaced apart from the first pixel electrode in a planar surface, and having the scan line disposed between the second pixel electrode and the first pixel electrode, the second pixel electrode including a second stem portion parallel to the data line, a second contact portion connected to the second transistor, and a second branch portion connecting the second contact portion and the second stem portion, and a first pattern disposed between the substrate and the second pixel electrode and overlapping the second branch portion, the repairing method of the display device can include a step of cutting the second branch portion to block a connection of the second pixel electrode to the second transistor.

[0023] In an embodiment, it can be that the second branch portion is cut using a laser.

[0024] In an embodiment, it can be that the display device further includes a second pattern disposed between the substrate and the first pixel electrode and overlapping the first branch portion.

[0025] In an embodiment, the repairing method of the display device can further include a step of cutting the first branch portion to block a connection of the first pixel electrode to the first transistor.

[0026] In an embodiment, it can be that the first branch portion is cut using a laser.

[0027] (EFFECT OF INVENTION)

[0028] Embodiments of the present application relate to a display device that prevents light leakage through a damaged portion of an alignment layer by including a first pattern disposed between a substrate and a pixel electrode and overlapping a branch portion connecting a stem portion and a contact portion of the pixel electrode.

[0029] However, the effects of the present application are not limited to the aforementioned effects, and various extensions can be made without departing from the spirit and scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is an exploded perspective view illustrating a display device according to an embodiment of the present application.

[0031] Figure 2 is a block diagram of a display panel of a display device. Figure 1

[0032] Figure 3 is an equivalent circuit diagram of a pixel of a display panel of Figure 2

[0033] Figure 4 is a configuration diagram of a pixel of a display panel of Figure 2

[0034] Figure 5 is a diagram of a gate pattern included in a pixel of Figure 4

[0035] Figure 6 is a diagram of a data pattern included in a pixel of Figure 4

[0036] Figure 7 is a diagram of a transparent conductive pattern included in a pixel of Figure 4

[0037] Figure 8 is a cross-sectional view taken along the line I-I' of Figure 4

[0038] Figure 9 is a diagram showing a repair method of a display device to which an embodiment of the present application relates.

[0039] Explanation of symbols:

[0040] 210: first substrate; 280: first alignment layer; 400: liquid crystal layer; CE: common electrode; DL: data line; PE1: first pixel electrode; PE1a: first stem portion; PE1b: first contact portion; PE1c: first branch portion; PE2: second pixel electrode; PE2a: second stem portion; PE2b: second contact portion; PE2c: second branch portion; PT1: first pattern; PT2: second pattern; PT3: third pattern; RL: storage line; SL: scan line; TR1: first transistor; TR2: second transistor; TR3: third transistor. DETAILED DESCRIPTION

[0041] Hereinafter, display devices and repair methods of display devices to which embodiments of the present application relate will be described in more detail with reference to the accompanying drawings. The same or similar components are denoted by the same or similar symbols throughout the drawings.

[0042] Figure 1 is an exploded perspective view showing a display device to which an embodiment of the present application relates.

[0043] Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings.​​​​​​​Figure 1 The display device can include the display panel 100 and a backlight unit BLU. The display panel 100 can include a first display panel 200, a second display panel 300, and a liquid crystal layer 400 disposed between the first display panel 200 and the second display panel 300.

[0044] The backlight unit BLU can provide light LT to the display panel 100. The light LT provided by the backlight unit BLU can be white light or light of a specific color. The backlight unit BLU can include a light emitting diode for generating the light LT.

[0045] The light LT provided by the backlight unit BLU can be incident to a lower surface of the display panel 100. In order to have high light efficiency, the backlight unit BLU can include various optical sheets such as a prism sheet, a diffusion sheet, a reflection sheet, a brightness improvement film, etc.

[0046] Figure 2 is a block diagram of the display panel 100 of the display device of Figure 1 .

[0047] Referring to Figure 2 , the display panel 100 can include a display portion 110, a scan driver 120, a data driver 130, and a timing controller 140.

[0048] The display portion 110 can display an image. A plurality of pixels PX can be disposed in the display portion 110. The plurality of pixels PX can be arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1.

[0049] Each of the pixels PX can be electrically connected to one of a plurality of scan lines SL and one of a plurality of data lines DL. Here, the plurality of scan lines SL can extend in the first direction DR1. In addition, the plurality of data lines DL can extend in the second direction DR2. For example, as shown in Figure 2 , the first direction DR1 can be a row direction, and the second direction DR2 can be a column direction.

[0050] The scan driver 120 can generate a scan signal SS based on a first control signal CONT1 received from the timing controller 140. The scan driver 120 can provide the scan signal SS to the pixels PX disposed in the display portion 110 through the scan lines SL. In an embodiment, the scan driver 120 can include a plurality of transistors. In other embodiments, the scan driver 120 can also be an integrated circuit.

[0051] The data driving part 130 can receive the second control signal CONT2 and the provision of the image data DATA from the timing control part 140. The data driving part 130 can generate the data signal DS based on the second control signal CONT2 and the image data DATA. The data driving part 130 can provide the data signal DS to the pixel PX disposed in the display part 110 through the data line DL. In an embodiment, the data driving part 130 can include a shift register, a latch, a digital-analog converter, etc.

[0052] The timing control part 140 can receive the provision of the image signal RGB and the control signal CS from the outside. The timing control part 140 can process the image signal RGB and the control signal CS into an operation condition suitable for the display part 110, thereby generating the image data DATA, the first control signal CONT1, and the second control signal CONT2.

[0053] The image signal RGB includes grayscale data provided to the display part 110. In addition, the control signal CS can include a horizontal synchronization signal, a vertical synchronization signal, a main clock signal, etc. The horizontal synchronization signal can indicate a time required to display one pixel row of the display part 110. The vertical synchronization signal can indicate a time required to display one frame of an image. The main clock signal can be a signal that becomes a reference for the timing control part 140 to generate each signal in synchronization with the scan driving part 120 and the data driving part 130.

[0054] Figure 3 is an equivalent circuit diagram of the pixel PX of the display panel 100. Figure 2

[0055] Referring to Figure 3 , the pixel PX can be connected with the scan line SL, the data line DL, and the storage line RL. The pixel PX can receive the provision of the scan signal SS from the scan line SL, can receive the provision of the data signal DS from the data line DL, and can receive the provision of the storage voltage Vst from the storage line RL.

[0056] The pixel PX can include the first transistor TR1, the second transistor TR2, the third transistor TR3, the first liquid crystal capacitor Clc1, the second liquid crystal capacitor Clc2, the first storage capacitor Cst1, and the second storage capacitor Cst2.

[0057] ​The first transistor TR1 can include a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode can be connected with the scan line SL. The first source electrode can be connected with the data line DL, and the first drain electrode can be connected with the first node N1. The first transistor TR1 can perform a switching operation based on a scan signal SS received from the scan line SL, and provide a data signal DS received from the data line DL to the first node N1.

[0058] The second transistor TR2 can include a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode can be connected with the scan line SL. The second source electrode can be connected with the data line DL, and the second drain electrode can be connected with the second node N2. The second transistor TR2 can perform a switching operation based on a scan signal SS received from the scan line SL, and provide a data signal DS received from the data line DL to the second node N2.

[0059] The third transistor TR3 can include a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode can be connected with the scan line SL. The third source electrode can be connected with the storage line RL, and the third drain electrode can be connected with the second node N2. The third transistor TR3 can perform a switching operation based on a scan signal SS received from the scan line SL, and provide a storage voltage Vst received from the storage line RL to the second node N2.

[0060] The first liquid crystal capacitor Clc1 can be formed between the first node N1 and a common electrode CE (refer to FIG. 1) that provides a common voltage Vcom. Figure 8 The second liquid crystal capacitor Clc2 can be formed between the second node N2 and the common electrode CE that provides the common voltage Vcom.

[0061] The first storage capacitor Cst1 can be formed between the first node N1 and a storage line RL that provides a storage voltage Vst. The second storage capacitor Cst2 can be formed between the second node N2 and the storage line RL that provides the storage voltage Vst.

[0062] If a gate conduction voltage is applied to the scan line SL, the first transistor TR1, the second transistor TR2, and the third transistor TR3 are turned on. Consequently, the data signal DS applied to the data line DL is applied to the first node N1 and the second node N2 through the turned-on first transistor TR1 and the second transistor TR2, respectively. In this case, the data signals DS applied to the first node N1 and the second node N2 are identical, and the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 can be charged to a voltage corresponding to the difference between the common voltage Vcom applied to the common electrode CE and the data signal DS. Simultaneously, through the turned-on third transistor TR3, the voltage of the second node N2 increases or decreases according to the storage voltage Vst applied from the storage line RL, thereby making the voltage charging the second liquid crystal capacitor Clc2 different from the voltage charging the first liquid crystal capacitor Clc1.

[0063] Because the voltages of the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 are different from each other, the tilt angles of the liquid crystal molecules in the first sub-pixel SPX1 formed by the first liquid crystal capacitor Clc1 and the second sub-pixel SPX2 formed by the second liquid crystal capacitor Clc2 become different from each other. Therefore, the brightness of the first sub-pixel SPX1 and the brightness of the second sub-pixel SPX2 can also become different from each other. Thus, by appropriately adjusting the voltages of the first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2, the image viewed from the side and the image viewed from the front can be made as close as possible to each other, thereby improving side recognition.

[0064] Figure 4 It means Figure 2 The configuration diagram of the display panel with 100 pixels (PX). Figure 5 It means Figure 4 A diagram of the gate pattern included in the pixel PX. Figure 6 It means Figure 4 The image contains a data pattern of pixels PX. Figure 7 It means Figure 4 The image shows the transparent conductive pattern included in the pixel PX. Figure 8 It is along Figure 4 A sectional view taken along line I-I'.

[0065] Reference Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The display panel 100 may include a first display panel 200, a second display panel 300, and a liquid crystal layer 400.

[0066] The first display panel 200 and the second display panel 300 can be configured to face each other. The liquid crystal layer 400 can be interposed between the first display panel 200 and the second display panel 300. The liquid crystal layer 400 can include a plurality of liquid crystal molecules 410. In an embodiment, the first display panel 200 and the second display panel 300 can be bonded by a sealing member.

[0067] The first display panel 200 can include a first substrate 210, a gate pattern GP, a gate insulating layer 220, a data pattern DP, a first passivation layer 250, a color filter CF, an organic insulating layer 260, a second passivation layer 270, a transparent conductive pattern TP, and a first alignment layer 280.

[0068] In an embodiment, the first substrate 210 can be a transparent insulating substrate. The transparent insulating substrate can include glass, quartz, a light-transmissive plastic, or the like. In other embodiments, the first substrate 210 can also be a structure in which a flexible substrate or a plurality of films are laminated.

[0069] The gate pattern GP can be disposed on the first substrate 210. The gate pattern GP can include a scan line SL and a storage line RL.

[0070] The scan line SL can extend substantially in the first direction DR1. The scan line SL can include a first gate electrode GE1, a second gate electrode GE2, and a third gate electrode GE3.

[0071] The storage line RL can be substantially parallel to the scan line SL. The storage line RL can be disposed on the same layer as the scan line SL. The storage line RL can be disposed to surround at least a portion of each of a right side portion of the first pixel electrode PE1 and a left side portion of the second pixel electrode PE2. Thus, the storage line RL can include a first extension EP1 surrounding the right side portions of the first pixel electrode PE1 and the second pixel electrode PE2, and a second extension EP2 surrounding the left side portions of the first pixel electrode PE1 and the second pixel electrode PE2. The first extension EP1 and the second extension EP2 can be spaced apart from each other, and the first trunk portion PE1a of the first pixel electrode PE1 and the second trunk portion PE2a of the second pixel electrode PE2 can be disposed therebetween.

[0072] The storage line RL can be disposed to overlap at least a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2. Thus, the storage line RL can include a third extension EP3 overlapping at least a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2. The overlapping third extension EP3 and the first pixel electrode PE1 can form a first storage capacitor Cst1, and the overlapping third extension EP3 and the second pixel electrode PE2 can form a second storage capacitor Cst2.

[0073] The gate pattern GP can be formed of a single layer film selected from among aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), a double layer film selected from among two of them, or a triple layer film selected from among three of them. The scan line SL and the storage line RL included in the gate pattern GP can be formed substantially simultaneously by the same mask process as each other.

[0074] The gate insulating layer 220 can be provided on the gate pattern GP. In an embodiment, the gate insulating layer 220 can be formed of silicon nitride, silicon oxide, or the like. The gate insulating layer 220 can also have a multi-layer film structure including at least two insulating layers having different physical properties.

[0075] The data pattern DP can be provided on the gate insulating layer 220. The data pattern DP can include a data line DL, a first source electrode SE1, a first drain electrode DE1, a second source electrode SE2, a second drain electrode DE2, a third source electrode SE3, a third drain electrode DE3, and a semiconductor layer 230. In the semiconductor layer 230, a first channel region CH1 of a first transistor TR1 can be formed between the first source electrode SE1 and the first drain electrode DE1, a second channel region CH2 of a second transistor TR2 can be formed between the second source electrode SE2 and the second drain electrode DE2, and a third channel region CH3 of a third transistor TR3 can be formed between the third source electrode SE3 and the third drain electrode DE3.

[0076] The semiconductor layer 230 can be provided on the gate insulating layer 220. In an embodiment, the semiconductor layer 230 can be formed of amorphous silicon, polycrystal silicon, or the like. In other embodiments, the semiconductor layer 230 can also be formed of an oxide semiconductor. In the case where the semiconductor layer 230 is formed of the oxide semiconductor, the semiconductor layer 230 can be formed of at least one selected from among oxide semiconductors including IGZO, ZnO, ZnO2, CdO, SrO, SrO2, CaO, CaO2, MgO, MgO2, InO, In2O2, GaO, Ga2O, Ga2O3, SnO, SnO2, GeO, GeO2, PbO, Pb2O3, Pb3O4, TiO, TiO2, Ti2O3, and Ti3O5.

[0077] In an embodiment, the data pattern DP can further include a resistive contact layer 240. The resistive contact layer 240 can be provided on the semiconductor layer 230. The resistive contact layer 240 can be formed of an n-type impurity such as phosphorus doped at a high concentration in an n-type semiconductor such as amorphous silicon, polycrystal silicon, or the like. +Hydrogenated amorphous silicon or the like is formed, or can be formed from a silicide. However, in the case where the semiconductor layer 230 is formed of an oxide semiconductor, the resistive contact layer 240 can be omitted. Hereinafter, a case where the data pattern DP includes the resistive contact layer 240 is described in this specification.

[0078] The data line DL, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, the third source electrode SE3, and the third drain electrode DE3 can be provided over the gate insulating layer 220 and the resistive contact layer 240. The data line DL can extend substantially in the second direction DR2, and can cross the scan line SL and the storage line RL.

[0079] The first source electrode SE1 can protrude from the data line DL with at least a part thereof overlapping with the first gate electrode GE1. The first drain electrode DE1 can overlap with the first gate electrode GE1 with at least a part thereof, and be spaced apart from the first source electrode SE1.

[0080] In Figure 4 and Figure 6 a case where the first source electrode SE1 has a "U"-shaped planar shape and the first drain electrode DE1 is surrounded by the first source electrode SE1 is shown, but the present application is not limited thereto. The first gate electrode GE1, the first source electrode SE1, the first drain electrode DE1, and the first channel region CH1 can form the first transistor TR1.

[0081] The second source electrode SE2 can protrude from the data line DL with at least a part thereof overlapping with the second gate electrode GE2. The second drain electrode DE2 can overlap with the second gate electrode GE2 with at least a part thereof, and be spaced apart from the second source electrode SE2. The second gate electrode GE2, the second source electrode SE2, the second drain electrode DE2, and the second channel region CH2 can form the second transistor TR2.

[0082] The third source electrode SE3 can be electrically connected to the storage line RL through the connection pattern CP, and can overlap with the third gate electrode GE3 with at least a part thereof. The third drain electrode DE3 can overlap with the third gate electrode GE3 with at least a part thereof, and be spaced apart from the third source electrode SE3. The third gate electrode GE3, the third source electrode SE3, the third drain electrode DE3, and the third channel region CH3 can form the third transistor TR3.

[0083] The data pattern DP can be formed of a single layer film selected from among aluminum (Al), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), and tungsten (W), a double layer film selected from among two of them, or a triple layer film selected from among three of them. The data line DL, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, the second drain electrode DE2, the third source electrode SE3, the third drain electrode DE3, the semiconductor layer 230, and the resistive contact layer 240 included in the data pattern DP can be formed substantially simultaneously by the same mask process as each other.

[0084] The first passivation layer 250 can be provided on the data pattern DP. In an embodiment, the first passivation layer 250 can be formed of silicon nitride, silicon oxide, or the like inorganic insulator. The first passivation layer 250 can prevent the pigments of the organic insulating layer 260 from flowing into the semiconductor layer 230.

[0085] The color filter CF can be provided on the first passivation layer 250. Light that has passed through the color filter CF can display one of the primary colors such as red, green, and blue. However, the display color of light that has passed through the color filter CF is not limited to the primary colors, and can display any one of cyan, magenta, yellow, and white.

[0086] In an embodiment, the color filter CF can be formed of a substance that displays a different color in each of the pixels adjacent in the first direction DR1, and formed of a substance that displays the same color in each of the pixels adjacent in the second direction DR2. However, the present application is not limited thereto, and in other embodiments, the color filter CF can be formed of a substance that displays a different color in each of the adjacent pixels regardless of the direction. In Figure 8 The case in which the color filter CF is provided to the first display panel 200 is shown in FIG. 1, but the color filter CF can be provided to the second display panel 300 differently therefrom.

[0087] The organic insulating layer 260 can be provided on the first passivation layer 250 and the color filter CF. The organic insulating layer 260 can include an organic substance that has excellent planarization properties and has photosensitivity. The organic insulating layer 260 can be omitted.

[0088] The second passivation layer 270 can be provided on the organic insulating layer 260. In an embodiment, the second passivation layer 270 can be formed of silicon nitride, silicon oxide, or the like inorganic insulator. The second passivation layer 270 can be omitted.

[0089] The first contact hole CNT1, the second contact hole CNT2, and the third contact hole CNT3 can be formed in the first passivation layer 250, the color filter CF, the organic insulating layer 260, and the second passivation layer 270. The first contact hole CNT1 can overlap at least a portion of the first drain electrode DE1. The second contact hole CNT2 can overlap at least a portion of the second drain electrode DE2. The third contact hole CNT3 can overlap at least a portion of the third extension part EP3 of the storage line RL and at least a portion of the third source electrode SE3.

[0090] The transparent conductive pattern TP can be disposed on the second passivation layer 270. The transparent conductive pattern TP can include a transparent conductive substance. In an embodiment, the transparent conductive substance can include polycrystalline, single-crystal, or amorphous ITO (indium tin oxide).

[0091] The transparent conductive pattern TP can include the first pixel electrode PE1, the second pixel electrode PE2, and the connection pattern CP. The first pixel electrode PE1, the second pixel electrode PE2, and the connection pattern CP can be disposed in the same layer as each other and can be physically and electrically insulated from each other.

[0092] The first pixel electrode PE1 can be in direct contact with the first drain electrode DE1 exposed through the first contact hole CNT1. In addition, the first pixel electrode PE1 can overlap the common electrode CE. Thereby, the first pixel electrode PE1 and the common electrode CE, which overlap each other, can form the first liquid crystal capacitor Clc1.

[0093] The first pixel electrode PE1 can include a first trunk part PE1a extending in the second direction DR2 substantially in parallel with the data line DL, a first contact part PE1b connected with the first drain electrode DE1, and a first branch part PE1c connecting the first contact part PE1b and the first trunk part PE1a.

[0094] The first contact part PE1b can be defined as an area overlapping the first contact hole CNT1. Accordingly, the first contact part PE1b of the first pixel electrode PE1 can be directly connected with the first drain electrode DE1 exposed through the first contact hole CNT1.

[0095] The first trunk part PE1a, the first contact part PE1b, and the first branch part PE1c of the first pixel electrode PE1 can be electrically connected. Thereby, the first trunk part PE1a, the first contact part PE1b, and the first branch part PE1c can have the same electric potential.

[0096] The second pixel electrode PE2 can be in direct contact with the second drain electrode DE2 exposed through the second contact hole CNT2. Also, the second pixel electrode PE2 can overlap the common electrode CE. Thereby, the second pixel electrode PE2 and the common electrode CE, which overlap each other, can form a second liquid crystal capacitor Clc2.

[0097] The second pixel electrode PE2 can be spaced apart from the first pixel electrode PE1 on a plane, between which the scan line SL can be disposed. In other words, the scan line SL can be located between the first pixel electrode PE1 and the second pixel electrode PE2 on a plane.

[0098] The second pixel electrode PE2 can include a second trunk portion PE2a extending in a second direction DR2 substantially in parallel with the data line DL, a second contact portion PE2b connected with the second drain electrode DE2, and a second branch portion PE2c connecting the second contact portion PE2b and the second trunk portion PE2a.

[0099] The second contact portion PE2b can be defined as an area overlapping the second contact hole CNT2. Accordingly, the second contact portion PE2b of the second pixel electrode PE2 can be directly connected with the second drain electrode DE2 exposed through the second contact hole CNT2.

[0100] The second trunk portion PE2a, the second contact portion PE2b, and the second branch portion PE2c of the second pixel electrode PE2 can be electrically connected. Thereby, the second trunk portion PE2a, the second contact portion PE2b, and the second branch portion PE2c can have the same electric potential.

[0101] The connection pattern CP can be in direct contact with the third extension portion EP3 of the storage line RL and the third source electrode SE3 exposed through the third contact hole CNT3. Thereby, the third source electrode SE3 can be electrically connected with the third extension portion EP3 of the storage line RL through the connection pattern CP.

[0102] The first alignment layer 280 can be disposed on the transparent conductive pattern TP. The first alignment layer 280 can guide the initial alignment of the liquid crystal molecules 410 within the liquid crystal layer 400.

[0103] The first display panel 200 can include a first pattern PT1, a second pattern PT2, and a third pattern PT3.

[0104] The first pattern PT1 can be disposed between the first substrate 210 and the second pixel electrode PE2, and overlap the second branch portion PE2c of the second pixel electrode PE2. The first pattern PT1 can prevent a light leakage through the first alignment layer 280 even if the first alignment layer 280 is damaged in a process of cutting the second branch portion PE2c of the second pixel electrode PE2 in order to repair the pixel PX.

[0105] In an embodiment, the first pattern PT1 can extend from the storage line RL. For example, the first pattern PT1 can extend from the storage line RL in the second direction DR2.

[0106] In an embodiment, the first pattern PT1 can be symmetrical in the plane with reference to the second stem portion PE2a of the second pixel electrode PE2. In other words, a first portion of the first pattern PT1 located on the right side of the second stem portion PE2a in the plane and a second portion of the first pattern PT1 located on the left side of the second stem portion PE2a in the plane can be symmetrical with reference to the second stem portion PE2a. In this case, a length, a width, a shape, or an area of the first portion of the first pattern PT1 can be substantially the same as a length, a width, a shape, or an area of the second portion of the first pattern PT1, respectively.

[0107] The second pattern PT2 can be disposed between the first substrate 210 and the first pixel electrode PE1, and can overlap the first branch portion PE1c of the first pixel electrode PE1. The second pattern PT2 can prevent a case in which light leakage occurs through the first alignment layer 280 even if the first alignment layer 280 is damaged in a process of cutting the first branch portion PE1c of the first pixel electrode PE1 in order to repair the pixel PX.

[0108] In an embodiment, the second pattern PT2 can extend from the first extension portion EP1 of the storage line RL. For example, the second pattern PT2 can extend from the first extension portion EP1 of the storage line RL in the first direction DR1.

[0109] The third pattern PT3 can be disposed between the first substrate 210 and the first pixel electrode PE1, and can extend from the second extension portion EP2 of the storage line RL. For example, the third pattern PT3 can extend from the second extension portion EP2 of the storage line RL in the first direction DR1.

[0110] In an embodiment, the second pattern PT2 and the third pattern PT3 can be disposed to be symmetrical to each other in the plane with reference to the first stem portion PE1a of the first pixel electrode PE1. In this case, a length, a width, a shape, or an area of the second pattern PT2 can be substantially the same as a length, a width, a shape, or an area of the third pattern PT3, respectively, and a distance from the first stem portion PE1a to the second pattern PT2 in the plane can be substantially the same as a distance from the first stem portion PE1a to the third pattern PT3 in the plane.

[0111] The second display panel 300 can include a second substrate 310, a black matrix BM, a planarization layer 320, a common electrode CE, and a second alignment layer 330.

[0112] The second substrate 310 can be configured to face the first substrate 210. The second substrate 310 can be a transparent insulating substrate. In one embodiment, the second substrate 310 can be formed of the same material as the first substrate 210.

[0113] A black matrix BM can be disposed on the second substrate 310. The black matrix BM can be disposed in an inactive region along the first direction DR1. The inactive region is the boundary between adjacent pixels in the second direction DR2, and is the region where the first pixel electrode PE1 and the second pixel electrode PE2 are not disposed. The black matrix BM can be configured to extend in the first direction DR1 and overlap with the scan line SL.

[0114] The black matrix BM can block light from passing through the ineffective area. In one embodiment, the black matrix BM can be formed from photosensitive components, organic materials, metallic substances, etc. For example, the photosensitive components may include adhesive resins, polymerizable monomers, polymerizable oligomers, pigments, dispersants, etc. Additionally, the metallic substances may include chromium (Cr), etc.

[0115] A black matrix BM extending in the second direction DR2 may not be configured between adjacent pixels in the first direction DR1. The spacing between adjacent pixels in the first direction DR1 can be adjusted so that the liquid crystal orientation can be adjusted even without the black matrix BM, preventing light from passing between adjacent pixels in the first direction DR1.

[0116] The planarization layer 320 can be disposed on the black matrix BM. The planarization layer 320 can provide a flat surface to the common electrode CE. In one embodiment, the planarization layer 320 can be formed of an organic or inorganic material.

[0117] A common electrode CE can be formed on the planarization layer 320. At least a portion of the common electrode CE can overlap with the first pixel electrode PE1, and at least another portion of the common electrode CE can overlap with the second pixel electrode PE2. In one embodiment, the common electrode CE can be formed of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum (Al), silver (Ag), chromium (Cr), or their alloys.

[0118] A second alignment layer 330 may be disposed on the common electrode CE. The second alignment layer 330 may guide the initial alignment of the liquid crystal molecules 410 within the liquid crystal layer 400. In one embodiment, the second alignment layer 330 may be formed of the same material as the first alignment layer 280.

[0119] The liquid crystal layer 400 can include a plurality of liquid crystal molecules 410. In an embodiment, the liquid crystal molecules 410 can have negative dielectric anisotropy and be vertically aligned in an initial alignment state. The liquid crystal molecules 410 can also have a predetermined pre-tilt angle in the initial alignment state. The initial alignment of the liquid crystal molecules 410 can be guided by the first alignment layer 280 and the second alignment layer 330. If an electric field is formed between the first display panel 200 and the second display panel 300, the liquid crystal molecules 410 tilt or rotate in a certain direction, and thus the polarization state of light passing through the liquid crystal layer 400 can be changed.

[0120] Figure 9 FIG. 1 is a diagram illustrating a display device according to an embodiment of the present application.

[0121] In a case where a defective pixel is generated, the pixel in which a defect is generated is repaired, and thus the pixel in which a defect is generated can be maintained in a black state. Specifically, a data signal applied to a pixel electrode of the pixel in which a defect is generated is blocked, and thus the pixel in which a defect is generated can not be recognized.

[0122] Referring to Figure 4 , Figure 8 and Figure 9 , in a repair method of a display device according to an embodiment, the second branch part PE2c of the second pixel electrode PE2 can be cut along the first cutting line CL1 to block the connection of the second pixel electrode PE2 and the second transistor TR2. As the second branch part PE2c is cut, the second main part PE2a and the second contact part PE2b of the second pixel electrode PE2 are disconnected, and thus a data signal is not applied to the second pixel electrode PE2, and thus the second pixel electrode PE2 can be in a floating state. Thus, the liquid crystal molecules 410 between the second pixel electrode PE2 and the common electrode CE are maintained in an initial alignment state, and thus a defective pixel can not be recognized.

[0123] In an embodiment, the second branch part PE2c can be cut using a laser. In a case where the second branch part PE2c is cut using the laser, the first alignment layer 280 disposed on the second pixel electrode PE2 can be damaged, and thus light can be leaked through a damaged part of the first alignment layer 280. However, the display device according to the embodiments of the present application includes the first pattern PT1 overlapping the second branch part PE2c, and thus the first pattern PT1 can block light incident from the backlight unit BLU (see FIG. 1) to the first alignment layer 280, and thus a case where light is leaked through the damaged part of the first alignment layer 280 can be prevented. Figure 1

[0124] ​In the repair method of the display device according to an embodiment, the first branch part PE1c of the first pixel electrode PE1 can be cut along the second cutting line CL2 to block the connection of the first pixel electrode PE1 and the first transistor TR1. As the first branch part PE1c is cut, the first trunk part PE1a and the first contact part PE1b of the first pixel electrode PE1 are disconnected, and no data signal is applied to the first pixel electrode PE1, so that the first pixel electrode PE1 can be in a floating state. Thus, the liquid crystal molecules 410 between the first pixel electrode PE1 and the common electrode CE can maintain the initial alignment state, so that a defective pixel is not identified.

[0125] In an embodiment, the first branch part PE1c can be cut by a laser. In the case where the first branch part PE1c is cut by the laser, the first alignment layer 280 disposed on the first pixel electrode PE1 can be damaged, so that light leakage can occur through the damaged part of the first alignment layer 280. However, the display device according to the embodiments of the present application includes the second pattern PT2 overlapping the first branch part PE1c, so that the second pattern PT2 can block light incident from the backlight unit BLU to the first alignment layer 280, thereby preventing the light leakage through the damaged part of the first alignment layer 280.

[0126] (Industrial Applicability)

[0127] The display device according to exemplary embodiments of the present application can be applied to a display device included in a computer, a notebook computer, a portable phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, etc.

[0128] The display device and the repair method of the display device according to exemplary embodiments of the present application have been described above with reference to the accompanying drawings, but the embodiments described above are exemplary, and those skilled in the art can make modifications and changes within the scope of the technical idea of the present application recited in the claims.

Claims

1. A display device comprising: a substrate; a scan line provided over the substrate; a storage line parallel to the scan line; a data line intersecting the scan line and the storage line; a first transistor and a second transistor connected to the scan line and the data line; a first pixel electrode provided over the first transistor and including a first stem portion parallel to the data line, a first contact portion connected to the first transistor, and a first branch portion extending from the first stem portion to the first contact portion to connect the first contact portion and the first stem portion; a second pixel electrode provided over the second transistor, spaced apart from the first pixel electrode in a planar view, and provided with the scan line and the storage line between the second pixel electrode and the first pixel electrode, the second pixel electrode including a second stem portion parallel to the data line, a second contact portion connected to the second transistor, and a second branch portion extending from the second stem portion to the second contact portion to connect the second contact portion and the second stem portion; and a first pattern provided between the substrate and the second pixel electrode, the first pattern extending from the storage line in a direction away from the first pixel electrode to overlap with the second branch portion.

2. The display device according to claim 1, wherein the first pattern is symmetrical with the second stem portion as a reference in a planar view.

3. The display device according to claim 1, further comprising: a second pattern provided between the substrate and the first pixel electrode, and overlapping with the first branch portion.

4. The display device according to claim 3, wherein the storage line includes a first extension portion and a second extension portion extending in parallel to the data line and spaced apart from each other, the first stem portion being provided between the first extension portion and the second extension portion, the second pattern extends from the first extension portion.

5. The display device according to claim 4, further comprising: a third pattern extending from the second extension portion, and provided to be symmetrical with the second pattern with the first stem portion as a reference in a planar view.

6. The display device according to claim 1, further comprising: a third transistor connected to the scan line and the storage line.

7. The display device according to claim 1, further comprising: an alignment layer provided over the first pixel electrode and the second pixel electrode.

8. The display device according to claim 7, further comprising: a common electrode provided over the alignment layer; and a liquid crystal layer provided between the alignment layer and the common electrode.

9. A display device comprising: a substrate; a scan line provided over the substrate and extending longitudinally in a first direction; a storage line extending longitudinally in the first direction to be parallel to the scan line; a data line extending longitudinally in a second direction perpendicular to the first direction to intersect the scan line and the storage line; a transistor including a gate electrode connected to the scan line, a source electrode connected to the data line, and a drain electrode spaced apart from the source electrode. ​ ​ a pixel electrode provided over the transistor and including a stem portion parallel to the data line, a contact portion connected to the drain electrode, and a branch portion extending from the stem portion to the contact portion to connect the contact portion and the stem portion; and a first pattern provided between the substrate and the pixel electrode and overlapping with the branch portion, the first pattern extending longitudinally from an extension portion of the storage line extending in the second direction in the first direction.

10. The display device according to claim 9, wherein the first pattern is symmetrical with the stem portion as a reference in a plane.

11. The display device according to claim 9, wherein the storage line includes a first extension portion and a second extension portion extending parallel to the data line and spaced apart from each other, the stem portion being provided between the first extension portion and the second extension portion, the first pattern extends from the first extension portion.

12. The display device according to claim 11, further comprising: a second pattern extending from the second extension portion and provided to be symmetrical with the first pattern with the stem portion as a reference in a plane.

13. The display device according to claim 9, further comprising: an alignment layer provided over the pixel electrode.

14. A repair method of a display device, the display device being the display device according to any one of claims 1 to 2 and 6 to 8, the repair method of the display device comprising: a step of cutting the second branch portion to block connection of the second pixel electrode and the second transistor.

15. The repair method of the display device according to claim 14, wherein the second branch portion is cut with a laser.

16. The repair method of the display device according to claim 14, wherein the display device further comprises a second pattern provided between the substrate and the first pixel electrode and overlapping with the first branch portion.

17. The repair method of the display device according to claim 16, further comprising: a step of cutting the first branch portion to block connection of the first pixel electrode and the first transistor.

18. The repair method of the display device according to claim 17, wherein the first branch portion is cut with a laser.

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