A method and apparatus for FM0 decoding with interference rejection capability
By using a combination of four FIFOs and an accumulator, continuous segmented accumulation and decoding of signals was achieved, solving the communication failure problem caused by high-frequency interference and improving the anti-interference capability and efficiency of the communication system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING YUNXINGYU TECH SERVICE CO LTD
- Filing Date
- 2021-12-10
- Publication Date
- 2026-06-23
Smart Images
Figure CN114421969B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to an FM0 decoding method and apparatus with anti-interference capability. Background Technology
[0002] In real-world communication systems, high-frequency interference is frequently encountered. This interference can cause communication failures in decoding methods that rely on transition time. This is because decoding methods that rely on transition time use only a small number of sampling points to determine the encoded value. If these key points are interfered with, communication will fail. Communication failure will trigger the system's retransmission mechanism, thereby reducing communication efficiency. When there is a lot of interference, it will seriously affect system performance. Summary of the Invention
[0003] To address the problem that high-frequency interference frequently occurs in real-world communication systems, causing communication failures in decoding methods that rely on transition times, the present invention aims to provide an FM0 decoding method and apparatus with anti-interference capabilities.
[0004] To achieve the above objectives, the present invention adopts the following technical solution: an FM0 decoding method with anti-interference capability, comprising the following steps:
[0005] S1 consists of four one-bit wide FIFOs, namely FIFO0, FIFO1, FIFO2, and FIFO3. The input signal is sampled by a clock signal and stored in the FIFO. The FIFO stores two FM0 encoded bits of time sampled data.
[0006] S2, 4 accumulators, record the accumulated value of the sampled values in the corresponding FIFO;
[0007] S3, the four accumulated values are judged as high or low respectively by F0, F1, F2, and F3;
[0008] S4, after being converted to absolute value, the accumulator performs summation to obtain the total value;
[0009] S5 uses the change in total value to find the peak value and uses it to correct the sampling time;
[0010] S6 uses whether the high and low values and the total value are greater than the threshold to determine whether the fm0 encoding is valid, and the fm0 output data is valid.
[0011] Preferably, in step S1, each clock cycle inputs one bit of data into the FIFO chain, and the FIFO outputs one bit of data. The total number of data bits L in the FIFO, the FM0 encoding bit time T, and the clock time C have the following relationship:
[0012] L = 2T / C
[0013] The FIFO stores sampled data for the timing of two FM0 encoded bits, which includes one analysis bit, consisting of the first half and the second half of the analysis bit.
[0014] Preferably, in S2, the four accumulators are I0, I1, I2, and I3, and the number of 1s in the corresponding FIFO is recorded. The specific method is as follows: initially, the FIFO and the accumulator are all 0, and then 1s are intercepted at the FIFO inlet and outlet. If 1 is entered into the FIFO, the accumulator is incremented by 1, and if 1 is exited from the FIFO, the accumulator is decremented by 1.
[0015] Preferably, in S3, half of the maximum value of the accumulator is the dividing line, with the higher value being 1 and the lower value being 0. If F1 equals F2, it means that the output of FM0 is 1, otherwise it is 0.
[0016] Preferably, in S4, the absolute value is a custom combinational logic that returns the distance between the accumulator value and the accumulator's midpoint. When the fm0 code shifts forward in the FIFO, the output value of the adder, after being converted into an analog quantity, will present a triangular wave. The peak of the triangular wave is aligned with the midpoint and edge point of the fm0 code.
[0017] Preferably, in step S5, to find the peak point of the triangular wave, a climbing state machine and an extreme value register are set up. In the climbing state, the adder output should be greater than the extreme value register value. If it is greater, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than, the counter is incremented by 1. If the number of times exceeds the limit, the climb state is entered and a calibration signal is output. Similarly, in the climbing state, the adder output should be less than the extreme value register value. If it is less than, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than, the counter is incremented by 1. If the number of times exceeds the limit, the climb state is entered, and so on.
[0018] Preferably, in step S6, the validity of the counter's overflow signal and the validity of the fm0 signal together determine the validity of the fm0 output data.
[0019] An FM0 decoding device with anti-interference capability consists of four one-bit wide FIFOs (FIFO0, FIFO1, FIFO2, and FIFO3) connected in series, four independent accumulators (I0, I1, I2, and I3), a logic judgment module, and an output module. The FM0 signal transmission direction is sequentially: FIFO, accumulator, logic judgment module, and output module.
[0020] Compared with existing technologies, the beneficial effects achieved by this invention are as follows: Other information of the FM0 encoding of this invention is derived from the accumulated value of the segmented FIFO, that is, the sum of 1s in the FIFO. This invention is very practical and can be extended to the decoding of various code types, which has strong practical significance. The FM0 decoding method of this invention does not depend on a certain sample value, but performs continuous segmented accumulation on the sample value sequence, and then performs decoding judgment based on the segmented accumulated value. Since the integration method is adopted, the decoded value is determined by the values of multiple consecutive sample points. Regardless of the quantity and location of interference, as long as the signal-to-noise ratio is sufficient, it can be decoded correctly, thus possessing anti-interference capability. The continuous segmentation is formed by connecting multiple FIFO segments end to end to form a long FIFO. In each sampling period, the latest sample point signal 1 or 0 enters the long FIFO, while the oldest sample point signal is squeezed out of the FIFO. The number of segments is related to the code type characteristics of FM0 encoding. This invention uses 4 segments, with the middle two segments corresponding to a complete FM0 encoding bit, referred to as the analysis bit. The first segment corresponds to the first half of the analysis bit, and the second segment corresponds to the second half of the analysis bit. Attached Figure Description
[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0022] Figure 1 This is a schematic diagram of the device structure of the present invention;
[0023] Figure 2 This is a schematic diagram of the fm0 data output of the present invention;
[0024] Figure 3 This is a schematic diagram of the adder of the present invention;
[0025] Figure 4 This is a schematic diagram of the effective structure of the fm0 signal of the present invention;
[0026] Figure 5 This is a schematic diagram of the climbing state machine of the present invention;
[0027] Figure 6 This is a schematic diagram illustrating the validity of fm0 data in this invention. Detailed Implementation
[0028] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
[0029] Please see Figures 1 to 6It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed in this invention. Furthermore, the terms such as "upper," "lower," "left," "right," "middle," and "one" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.
[0030] Example 1: An FM0 decoding method with anti-interference capability, comprising the following steps:
[0031] S1 consists of four one-bit wide FIFOs, namely FIFO0, FIFO1, FIFO2, and FIFO3. The input signal is sampled by a clock signal and stored in the FIFO. The FIFO stores two FM0 encoded bits of time sampled data.
[0032] S2, 4 accumulators, record the accumulated value of the sampled values in the corresponding FIFO;
[0033] S3, the four accumulated values are judged as high or low respectively by F0, F1, F2, and F3;
[0034] S4, after being converted to absolute value, the accumulator performs summation to obtain the total value;
[0035] S5 uses the change in total value to find the peak value and uses it to correct the sampling time;
[0036] S6 uses whether the high and low values and the total value are greater than the threshold to determine whether the fm0 encoding is valid, and the fm0 output data is valid.
[0037] In S1, each clock cycle inputs one bit of data into the FIFO chain, and the FIFO outputs one bit of data. The total number of data bits L in the FIFO, the FM0 encoding bit time T, and the clock time C have the following relationship:
[0038] L = 2T / C
[0039] The FIFO stores sampled data for the timing of two FM0 encoded bits, which includes one analysis bit, consisting of the first half and the second half of the analysis bit.
[0040] In S2, the four accumulators are I0, I1, I2, and I3, and they record the number of 1s in the corresponding FIFO. The specific method is as follows: initially, the FIFO and the accumulators are all 0. Then, 1s are intercepted at the FIFO inlet and outlet. If 1 is entered into the FIFO, the accumulator is incremented by 1. If 1 is exited from the FIFO, the accumulator is decremented by 1.
[0041] In S3, half of the maximum value of the accumulator is the dividing line; the higher value is 1, and the lower value is 0. If F1 equals F2, it means that the output of FM0 is 1; otherwise, it is 0.
[0042] In S4, the absolute value is a custom combinational logic that returns the distance between the accumulator's value and the accumulator's midpoint. When the fm0 code shifts forward in the FIFO, the adder's output value, after being converted into an analog quantity, will present a triangular wave. The peak of the triangular wave is aligned with the midpoint and edge of the fm0 code.
[0043] In step S5, to find the peak point of the triangular wave, a climbing state machine and an extreme value register are set up. In the climbing state, the adder output should be greater than the extreme value register value. If it is greater, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than the value, the counter is incremented by 1. If the number of attempts exceeds the limit, the climb state is entered and a calibration signal is output. Similarly, in the climbing state, the adder output should be less than the extreme value register value. If it is less than the value, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than the value, the counter is incremented by 1. If the number of attempts exceeds the limit, the climb state is entered, and so on.
[0044] In S6, the validity of the counter's overflow signal and the validity of the fm0 signal together determine the validity of the fm0 output data.
[0045] Example 2: An FM0 decoding device with anti-interference capability consists of four one-bit wide FIFOs, namely FIFO0, FIFO1, FIFO2, and FIFO3 connected in series, four independent accumulators I0, I1, I2, and I3, a logic judgment module, and an output module. The FM0 signal transmission direction is FIFO, accumulator, logic judgment module, and output module in sequence.
[0046] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. An FM0 decoding method with anti-interference capability, characterized in that, It includes the following steps: S1 consists of four one-bit wide FIFOs, namely FIFO0, FIFO1, FIFO2, and FIFO3. The input signal is sampled by a clock signal and stored in the FIFO. The FIFO stores two FM0 encoded bits of time sampled data. S2, 4 accumulators, record the accumulated value of the sampled values in the corresponding FIFO; S3, the four accumulated values are judged as high or low respectively by F0, F1, F2, and F3; S4, after being converted to absolute value, the accumulator performs summation to obtain the total value; S5 uses the change in total value to find the peak value and uses it to correct the sampling time; S6 uses whether the high and low values and the total value are greater than the threshold to determine whether the fm0 encoding is valid, and the fm0 output data is valid.
2. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In S1, each clock cycle inputs one bit of data into the FIFO chain, and the FIFO outputs one bit of data. The total number of data bits L in the FIFO, the FM0 encoding bit time T, and the clock time C have the following relationship: L = 2T / C The FIFO stores sampled data for the timing of two FM0 encoded bits, which includes one analysis bit, consisting of the first half and the second half of the analysis bit.
3. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In S2, the four accumulators are I0, I1, I2, and I3, and they record the number of 1s in the corresponding FIFO. The specific method is as follows: initially, the FIFO and the accumulators are all 0. Then, 1s are intercepted at the FIFO inlet and outlet. If 1 is entered into the FIFO, the accumulator is incremented by 1. If 1 is exited from the FIFO, the accumulator is decremented by 1.
4. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In S3, half of the maximum value of the accumulator is the dividing line; the higher value is 1, and the lower value is 0. If F1 equals F2, it means that the output of FM0 is 1; otherwise, it is 0.
5. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In S4, the absolute value is a custom combinational logic that returns the distance between the accumulator's value and the accumulator's midpoint. When the fm0 code shifts forward in the FIFO, the adder's output value, after being converted into an analog quantity, will present a triangular wave. The peak of the triangular wave is aligned with the midpoint and edge of the fm0 code.
6. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In step S5, to find the peak point of the triangular wave, a climbing state machine and an extreme value register are set up. In the climbing state, the adder output should be greater than the extreme value register value. If it is greater, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than the value, the counter is incremented by 1. If the number of attempts exceeds the limit, the climb state is entered and a calibration signal is output. Similarly, in the climbing state, the adder output should be less than the extreme value register value. If it is less than the value, the extreme value register value is refreshed by the new value and the counter is cleared to 0. If it is less than the value, the counter is incremented by 1. If the number of attempts exceeds the limit, the climb state is entered, and so on.
7. The FM0 decoding method with anti-interference capability according to claim 1, characterized in that: In S6, the validity of the counter's overflow signal and the validity of the fm0 signal together determine the validity of the fm0 output data.
8. An FM0 decoding device with anti-interference capability, characterized in that: It consists of four one-bit wide FIFOs (FIFO0, FIFO1, FIFO2, and FIFO3) connected in series, four independent accumulators (I0, I1, I2, and I3), a logic judgment module, and an output module. The transmission direction of the fm0 signal is sequentially FIFO, accumulator, logic judgment module, and output module.