FPGA-based timing synchronization method, device and PG equipment

Abstract

The invention discloses a timing synchronization method, device and PG equipment based on FPGA, which comprises a triggering step: obtaining a timing synchronization signal and a synchronization control signal according to the first valid frame header of a frame header signal of an image data stream; a data writing step: writing a valid data signal of the image data stream; and a video outputting step: taking a valid data strobe DE signal in the timing synchronization signal as a read signal to read a valid data signal, and outputting a timing synchronization signal, wherein both the read valid data signal and the output timing synchronization signal are delayed by a preset number of clock cycles relative to the synchronization control signal, so as to output a video signal synchronized with the valid data signal and the timing synchronization signal, thereby realizing effective synchronization of the valid data signal and the timing synchronization signal, and in the case of out-of-step, resynchronization can be achieved when the first valid frame header of the frame header of the next frame arrives, thereby effectively avoiding the problem of image distortion displayed in a display module to be tested due to out-of-step, thereby affecting the detection.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a timing synchronization method and device based on FPGA and a PG device. Background Art

[0002] With the development of display technology, display modules are increasingly used. Pattern generators (PG) are usually used in the production test of display modules. They need to send specific images to the display module to be tested for display, so as to detect whether the display module to be tested has defects such as bad pixels.

[0003] The PG device needs to continuously read the image data stream from the memory and synchronize the image data stream with specific timing synchronization signals (such as valid data selection signal DE, line synchronization signal HSYNC, field synchronization signal VSYNC, etc.) to generate video data, and then transmit it to the line test display module, and the display module to be tested will correctly display the picture.

[0004] In the prior art, the image data stream and the timing synchronization signal are prone to desynchronization. Once desynchronization occurs, the image displayed in the display module to be tested will be distorted, thereby affecting the detection. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a FPGA-based timing synchronization method, device and PG device, aiming to solve the problem in the prior art that the image displayed in the display module to be tested is distorted due to the loss of synchronization between the image data stream and the timing synchronization signal, thereby affecting the detection.

[0006] In order to achieve the above object, the first aspect of the present invention provides a timing synchronization method based on FPGA, comprising:

[0007] Triggering step: obtaining a timing synchronization signal and a synchronization control signal according to the first valid frame header of the frame header signal of the image data stream;

[0008] Data writing step: writing valid data signals of image data stream;

[0009] Video output step: use the valid data selection DE signal in the timing synchronization signal as the read signal to read the valid data signal, and output the timing synchronization signal. The read valid data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal to output a video signal synchronized with the valid data signal and the timing synchronization signal.

[0010] Optionally, the triggering step comprises:

[0011] Sending a frame header signal to a timing synchronization control module;

[0012] Triggering the timing synchronization control module to output a synchronization control signal according to the first valid frame header of the frame header signal, and triggering the timing synchronization control module to output a timing synchronization signal delayed by a first number of clock cycles relative to the synchronization control signal;

[0013] Video output steps include:

[0014] Delaying the timing synchronization signal by a second number of clock cycles as a new timing synchronization signal;

[0015] Delaying the DE signal of the new timing synchronization signal as a read signal by a third number of clock cycles to read out a valid data signal;

[0016] The new timing synchronization signal is delayed by a third number of clock cycles and output as the final output timing synchronization signal; wherein the preset number is the sum of the first number, the second number and the third number.

[0017] Optionally, the first quantity is 1, the second quantity is 1, and the third quantity is 2.

[0018] Optionally, the synchronization control signal is delayed by a fourth number of clock cycles relative to the first valid frame header.

[0019] Optionally, the writing step further includes: writing a frame header signal of the image data stream;

[0020] The video output step further includes: reading a frame header signal using the DE signal as a read signal;

[0021] The method further includes:

[0022] Judgment step: judge whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid. If both are valid, it is in a synchronous state. If at least one is invalid, it is in an out-of-step state and enters the trigger step again.

[0023] Optionally, the method further comprises:

[0024] Preliminary judgment step: obtaining a data valid signal and a frame header signal of the image data stream; when it is detected that both the frame header signal and the data valid signal are valid signals, the control state machine enters a synchronization state from an initial idle state, and enters a triggering step and a data writing step;

[0025] In the judgment step, if all are valid, the control state machine remains in the synchronization state; if at least one is invalid, the control state machine jumps to the out-of-step state and enters the triggering step again.

[0026] A second aspect of the present invention provides a timing synchronization device based on FPGA, comprising:

[0027] A trigger module, used for obtaining a timing synchronization signal and a synchronization control signal according to a first valid frame header of a frame header signal of an image data stream;

[0028] A writing module, used for writing valid data signals of an image data stream;

[0029] The video output module is used to read the valid data signal using the valid data selection DE signal in the timing synchronization signal as the read signal, and output the timing synchronization signal. The read valid data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal to output a video signal synchronized with the valid data signal and the timing synchronization signal.

[0030] Optionally, the trigger module is further used to send a frame header signal to the timing synchronization control module, trigger the timing synchronization control module to output a synchronization control signal according to the first valid frame header of the frame header signal, and trigger the timing synchronization control module to output a timing synchronization signal that is delayed by a first number of clock cycles relative to the synchronization control signal;

[0031] The video output module is also used to delay the timing synchronization signal by a second number of clock cycles as a new timing synchronization signal; delay the DE signal of the new timing synchronization signal by a third number of clock cycles as a read signal to read out a valid data signal; delay the new timing synchronization signal by a third number of clock cycles as a final output timing synchronization signal and output it; wherein the preset number is the sum of the first number, the second number and the third number.

[0032] Optionally, the first quantity is 1, the second quantity is 1, and the third quantity is 2.

[0033] Optionally, the writing module is further used to write a frame header signal of the image data stream;

[0034] The video output module is also used to read the frame header signal using the DE signal as a read signal;

[0035] The device also includes:

[0036] The judgment module is used to judge whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid. If both are valid, they are in a synchronized state. If at least one is invalid, it is in an out-of-step state and controls the trigger module, the writing module and the video output module to work again.

[0037] Optionally, the device further comprises:

[0038] The preliminary judgment module is used to obtain the data valid signal and the frame header signal of the image data stream; when it is detected that the current frame header signal and the data valid signal are both valid signals, the control state machine enters the synchronization state from the initial idle state, and controls the timing synchronization control module, the trigger module and the writing module to work again;

[0039] The judgment module is also used to control the state machine to remain in the synchronous state if all are valid, and to control the state machine to jump to the out-of-step state if at least one is invalid, and to control the timing synchronization control module, the trigger module and the writing module to work again.

[0040] A third aspect of the present invention provides a PG device, comprising: the above-mentioned FPGA-based timing synchronization device.

[0041] Through the above technical solution, effective synchronization of valid data signals and timing synchronization signals is achieved, and in the case of loss of step, resynchronization can be achieved when the first valid frame header of the next frame arrives, effectively avoiding the problem of image distortion displayed in the display module to be tested due to loss of step, thereby affecting the detection.

[0042] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0044] Figure 1 A schematic diagram of an application environment of a timing synchronization method based on FPGA according to an embodiment of the present invention is shown schematically;

[0045] Figure 2 A schematic diagram of a flow chart of a timing synchronization method based on FPGA according to an embodiment of the present invention is shown;

[0046] Figure 3 A block diagram of a timing synchronization system based on FPGA according to an embodiment of the present invention is schematically shown;

[0047] Figure 4 A timing diagram of a timing synchronization method based on FPGA according to an embodiment of the present invention is schematically shown;

[0048] Figure 5 A schematic diagram of a flow chart of a timing synchronization method based on FPGA according to another embodiment of the present invention is shown;

[0049] Figure 6 The structure block diagram of a timing synchronization device based on FPGA according to an embodiment of the present invention is schematically shown. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific implementation methods described herein are only used to illustrate and explain the embodiments of the present invention, and are not used to limit the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0051] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0052] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0053] The FPGA-based timing synchronization method provided by the present invention can be applied to Figure 1 In the application environment shown. Among them, the PG device communicates with the host computer device and the display module to be tested through the network respectively. The host computer can be but is not limited to devices such as smart phones or tablet computers. The user generates a test file package through the host computer, and sends the test file package to the PG device through the host computer. The host computer also sends an execution instruction to the PG device. After receiving the execution instruction, the PG device decompresses the received test file package to obtain image data, reads the image data to obtain an image data stream, and synchronizes the image data stream with the timing synchronization signal to obtain a video signal, and then sends the video signal to the display module to be tested for display. Of course, in actual applications, the present invention is not limited to the above Figure 1 In the application environment, the present invention focuses on how to synchronize the image data stream with the timing synchronization signal to output the video signal for the image module to be tested. How to obtain the image data stream can adopt any existing or future method.

[0054] Figure 2The flowchart of the timing synchronization method based on FPGA according to an embodiment of the present invention is schematically shown. Figure 2 As shown, in one embodiment of the present invention, a timing synchronization method based on FPGA is provided. The embodiment of the present invention mainly applies this method to the above Figure 1 Taking the PG device in as an example, the method may include the following steps:

[0055] S10: Triggering step: obtaining a timing synchronization signal and a synchronization control signal according to the first valid frame header of the frame header signal of the image data stream.

[0056] Specifically, a frame header signal can be sent to the timing synchronization control module, and the timing synchronization control module can be triggered to output a synchronization control signal according to the first valid frame header of the frame header signal, and the timing synchronization control module can be triggered to output a timing synchronization signal that is delayed by a first number of clock cycles relative to the synchronization control signal. The timing synchronization control module can use an existing IP core or a self-developed IP core.

[0057] Figure 3 A block diagram of a timing synchronization device based on FPGA according to an embodiment of the present invention is schematically shown. Figure 3 As shown, the application environment includes a Data Source module, a Video Timing Controller module (i.e., a timing synchronization control module, hereinafter referred to as a VTC module) and an Axi Stream to Video module (an FPGA-based timing synchronization device). The Data Source module is used to output an image data stream (i.e., the source of the image data stream). The Video Timing Controller module can generate and output timing synchronization signals, such as a valid data selection DE signal, a line synchronization Hsync signal and a field synchronization Vsync signal. The Axi Stream to Video module is used to synchronize the image data stream with the timing synchronization signal.

[0058] The Data Source module can be a PPC convert module based on a Field Programmable Gate Array (FPGA). The width of its output effective data bus is determined by the number of data channels (lane number) of the display module to be tested. If the number of lanes is 8, the effective bit width of its output data bus is 8 pixel data, that is, 8 pixel data are output in each clock cycle. Its interface signal is AXI Stream, and the AXI Stream interface signals include tuser, tdada, tvalid and tready, among which the tready signal is the feedback signal output by the Axi Stream to Video module to the DataSource module. When this signal is high and valid, it means that it can receive data; otherwise, it cannot receive data, and the Data Source module should suspend data transmission at this time.

[0059] The image data stream output by the Data Source module includes a valid data signal axis_tdata, a frame header signal axis_tuser and a data valid signal axis_tvalid. In this embodiment, the frame header signal axis_tuser is used as a Frame Sync In signal input of the VideoTiming Controller module.

[0060] After receiving the frame header signal axis_tuser, the Video Timing Controller module generates and outputs a synchronization control signal Frame Sync Out and a timing synchronization signal (including a DE signal, an Hsync signal, and a Vsync signal) according to the first valid frame header of the frame header signal. The synchronization control signal is delayed by a fourth number of clock cycles relative to the first valid frame header, and the timing synchronization signal is delayed by a first number of clock cycles relative to the synchronization control signal.

[0061] Figure 4 A timing diagram of a timing synchronization method based on FPGA according to an embodiment of the present invention is schematically shown, and reference is made to Figure 2 , Figure 3 and Figure 4, taking the fourth number being 2 and the first number being 1 as an example, the Video Timing Controller module delays the first valid frame header by 2 clock cycles, and then outputs a high-valid synchronization control signal to the Axi Stream toVideo module; starting from the first clock cycle after the synchronization control signal is valid, the Video Timing Controller module outputs a DE signal, an Hsync signal, and a Vsync signal that meet pre-configured parameters (such as the width, height, horizontal or vertical front shoulder, and back shoulder of the image), and the DE signal, the Hsync signal, and the Vsync signal are all one clock cycle later than the synchronization control signal; thereafter, the Video Timing Controller module continuously outputs the synchronization control signal, the DE signal, the Hsync signal, and the Vsync signal according to a frame cycle.

[0062] The timing relationship among the DE signal, Hsync signal and Vsync signal is well known in the art and will not be described in detail here. Only the delay variation of the DE signal will be described below. Similarly, the Hsync signal and the Vsync signal will also be delayed accordingly.

[0063] The Axi Stream to Video module synchronously outputs a valid data signal and a timing synchronization signal according to the synchronization control signal and the timing synchronization signal to obtain and output a video signal Video Data.

[0064] S20: Data writing step: writing valid data signals of the image data stream.

[0065] In a specific implementation, the valid data signal of the image data stream is written into the FIFO of the Axi Stream to Video module. When writing the valid data signal, the frame header signal of the image data stream can also be written into the Axi Stream to Video module FIFO. In addition, the valid data signal refers to the data on the tdata signal when the data valid signal axis_tvalid is valid.

[0066] S30: Video output step: Use the valid data selection DE signal in the timing synchronization signal as a read signal to read the valid data signal, and output the timing synchronization signal. The read valid data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal to output a video signal synchronized with the valid data signal and the timing synchronization signal.

[0067] In a specific implementation, taking into account that the read data may be delayed relative to the read signal, the timing synchronization signal may be delayed by a second number of clock cycles as a new timing synchronization signal; the DE signal of the new timing synchronization signal may be delayed by a third number of clock cycles as a read signal to read out a valid data signal; the new timing synchronization signal may be delayed by a third number of clock cycles as a final output timing synchronization signal and output; wherein the preset number is the sum of the first number, the second number, and the third number.

[0068] Refer to Figure 2 , Figure 3 and Figure 4 , taking the second number being 1 and the third number being 2 as an example, assuming that the read data is delayed by 2 clock cycles relative to the read signal, the Axi Stream to Video module can first delay the DE signal, Hsync signal, and Vsync signal output by the VTC by 1 clock cycle, and then read the valid data signal in the cache according to the delayed DE signal (read signal), and finally output the DE signal, Hsync signal, and Vsync signal that are delayed by another 2 cycles relative to the read signal and the valid data signal after reading, to obtain a video signal synchronized with the valid data signal and the timing synchronization signal.

[0069] It should be noted that the first number, the second number and the third number can be set according to actual conditions. Considering the stability of timing control and the transmission rate, in one example, the value of the first number is 1, the value of the second number is 1, and the value of the third number is 2.

[0070] When the first number is 1, the second number is 1, and the third number is 2, the read valid data signal and the output timing synchronization signal are both delayed by 4 clock cycles relative to the synchronization control signal.

[0071] This embodiment includes a triggering step: obtaining a timing synchronization signal and a synchronization control signal according to the first valid frame header of the frame header signal of the image data stream; a data writing step: writing the valid data signal of the image data stream; a video output step: using the valid data selection DE signal in the timing synchronization signal as a read signal to read the valid data signal, and outputting the timing synchronization signal, the read valid data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal, so as to output a video signal synchronized with the valid data signal and the timing synchronization signal, thereby achieving effective synchronization of the valid data signal and the timing synchronization signal, not only with good timing control stability, but also with high transmission rate; and in the case of out-of-step, resynchronization can be performed when the first valid frame header of the frame header of the next frame arrives, thereby effectively avoiding the problem of image distortion displayed in the display module to be tested due to out-of-step, thereby affecting the detection.

[0072] Figure 5The flowchart of the timing synchronization method based on FPGA according to another embodiment of the present invention is schematically shown. Figure 5 As shown, in another embodiment of the present invention, a timing synchronization method based on FPGA is provided, which may also include:

[0073] S40: writing step: writing a frame header signal of the image data stream;

[0074] S50: Video output step: using the DE signal as a read signal to read the frame header signal;

[0075] S60: Judgment step: judge whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid. If both are valid, they are in a synchronized state. If at least one is invalid, they are in an out-of-step state and enter the trigger step again.

[0076] Refer to Figure 3 , Figure 4 and Figure 5 When the Axi Stream to Video module detects that the Frame Sync Out signal output by the Video TimingController module is valid after a delay signal of a preset number of clock cycles, it can detect whether the frame header signal read from the FIFO is also valid. If both are valid, it can be determined that the valid data signal is synchronized with the timing synchronization signal, that is, it is in a synchronized state. If at least one is invalid, it is in a state of out-of-step, and returns to the triggering step. Steps S40, 50 and S60 can be used to automatically determine whether there is an out-of-step state, and automatically trigger resynchronization in the out-of-step state, thereby improving the efficiency of resynchronization, improving the rapid response after out-of-step, and greatly improving the smoothness of the picture.

[0077] Furthermore, the timing synchronization method also includes: a preliminary judgment step: obtaining a data valid signal and a frame header signal of the image data stream; when it is detected that the frame header signal and the data valid signal are both valid signals, the control state machine enters a synchronization state from an initial idle state, and enters a triggering step and a data writing step; in the judgment step, if both are valid, the control state machine remains in a synchronization state, and if at least one is invalid, the control state machine jumps to an out-of-step state, and enters the triggering step again.

[0078] It should be understood that at the initial power-on, the control machine is in an idle (i.e., IDLE) state. When the data valid signal axis_tvalid and the frame header signal axis_tuser are both valid signals, the control state machine enters the synchronization (i.e., SYNC) state from the idle state. When the control machine is in the state of just entering the synchronization state, it enters the triggering step to trigger the Video TimingController module to output the timing synchronization signal and the synchronization control signal; when the control machine is in the SYNC state, the frame header signal and the valid data signal of the image data stream are written into the FIFO of the Data Source module.

[0079] During the execution of the triggering step, the data writing step and the video output step, the Axi Stream to Video module continuously determines whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid. If both are valid, the control state machine remains in the synchronization state. If at least one is invalid, the control state machine jumps to the out-of-step state and enters the triggering step again.

[0080] This embodiment uses a state machine to continuously determine whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid, and determines whether they are in a synchronous state, which effectively ensures the accuracy of timing control while reducing development difficulty.

[0081] Figure 2 and Figure 5 FIG. 1 is a flow chart of a timing synchronization method based on FPGA in one embodiment. It should be understood that although Figure 2 and Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 and Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0082] In one embodiment, Figure 6As shown, a timing synchronization device based on FPGA is provided, which may include a trigger module 10, used to obtain a timing synchronization signal and a synchronization control signal according to the first valid frame header of the frame header signal of the image data stream; a writing module 20, used to write the valid data signal of the image data stream; a video output module 30, used to read the valid data signal by using the valid data selection DE signal in the timing synchronization signal as a read signal, and output the timing synchronization signal, the read valid data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal, so as to output a video signal synchronized with the valid data signal and the timing synchronization signal.

[0083] Furthermore, the trigger module 10 is also used to send a frame header signal to the timing synchronization control module, trigger the timing synchronization control module to output a synchronization control signal according to the first valid frame header of the frame header signal, and trigger the timing synchronization control module to output a timing synchronization signal that is delayed by a first number of clock cycles relative to the synchronization control signal; the video output module 30 is also used to delay the timing synchronization signal by a second number of clock cycles as a new timing synchronization signal; delay the DE signal of the new timing synchronization signal by a third number of clock cycles as a read signal to read out a valid data signal; delay the new timing synchronization signal by a third number of clock cycles as a final output timing synchronization signal and output it; wherein the preset number is the sum of the first number, the second number and the third number.

[0084] Further, the first number is 1, the second number is 1, and the third number is 2.

[0085] Furthermore, the writing module 20 is also used to write the frame header signal of the image data stream; the video output module 30 is also used to read the frame header signal using the DE signal as the read signal; the device also includes: a judgment module (not shown in the figure), which is used to judge whether the synchronization control signal delayed by a preset number of clock cycles and the read frame header signal are both valid, if both are valid, it is in a synchronous state, if at least one is invalid, it is in an out-of-step state, and controls the trigger module, the writing module and the video output module to work again.

[0086] Furthermore, the device also includes: a preliminary judgment module (not shown), which is used to obtain the data valid signal and frame header signal of the image data stream; when it is detected that the current frame header signal and the data valid signal are both valid signals, the control state machine enters the synchronization state from the initial idle state, and controls the timing synchronization control module, the trigger module and the writing module to work again; the judgment module is also used to control the state machine to remain in the synchronization state if all are valid, and if at least one is invalid, the control state machine jumps to the out-of-step state, and controls the timing synchronization control module, the trigger module and the writing module to work again.

[0087] An embodiment of the present invention further provides a PG device, including: the above-mentioned FPGA-based timing synchronization device.

[0088] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0089] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A timing synchronization method based on FPGA, characterized in that: include: Triggering step: obtaining a timing synchronization signal and a synchronization control signal according to the first valid frame header of the frame header signal of the image data stream; Data writing step: writing a valid data signal of the image data stream; Video output step: using the effective data strobe DE signal in the timing synchronization signal as a read signal to read the effective data signal, and outputting the timing synchronization signal, wherein the read effective data signal and the output timing synchronization signal are both delayed by a preset number of clock cycles relative to the synchronization control signal, so as to output a video signal synchronized with the effective data signal and the timing synchronization signal; The data writing step further includes: writing a frame header signal of the image data stream; The video output step further includes: reading the frame header signal using the DE signal as a read signal; The timing synchronization method further includes: Judgment step: judge whether the synchronization control signal delayed by the preset number of clock cycles and the read frame header signal are both valid. If both are valid, it is in a synchronization state; if at least one is invalid, it is in an out-of-step state and enters the trigger step again.

2. The timing synchronization method according to claim 1, characterized in that: The triggering step comprises: Sending the frame header signal to a timing synchronization control module; Triggering the timing synchronization control module to output the synchronization control signal according to a first valid frame header of the frame header signal, and triggering the timing synchronization control module to output the timing synchronization signal delayed by a first number of clock cycles relative to the synchronization control signal; The video output step comprises: Delaying the timing synchronization signal by a second number of clock cycles as a new timing synchronization signal; Delaying the DE signal of the new timing synchronization signal as a read signal by a third number of clock cycles to read out the valid data signal; The new timing synchronization signal is delayed by the third number of clock cycles and output as the final output timing synchronization signal; wherein the preset number is the sum of the first number, the second number and the third number.

3. The timing synchronization method according to claim 2, characterized in that: The first number is 1, the second number is 1, and the third number is 2.

4. The timing synchronization method according to claim 2, characterized in that: Also includes: The synchronization control signal is delayed by a fourth number of clock cycles relative to the first valid frame header.

5. The timing synchronization method according to claim 1, characterized in that: Also includes: Preliminary judgment step: obtaining a data valid signal and a frame header signal of the image data stream; When it is detected that both the frame header signal and the data valid signal are valid signals, the control state machine enters the synchronization state from the initial idle state, and enters the triggering step and the data writing step; In the judging step, if all are valid, the state machine is controlled to remain in the synchronous state; if at least one is invalid, the state machine is controlled to jump to the out-of-sync state and enter the triggering step again.

6. A timing synchronization device based on FPGA, characterized in that: include: A trigger module, used for obtaining a timing synchronization signal and a synchronization control signal according to a first valid frame header of a frame header signal of an image data stream; A writing module, used for writing a valid data signal of the image data stream; A video output module, used for reading the valid data signal by using the valid data strobe DE signal in the timing synchronization signal as a read signal, and outputting the timing synchronization signal, wherein both the read valid data signal and the output timing synchronization signal are delayed by a preset number of clock cycles relative to the synchronization control signal, so as to output a video signal synchronized with the valid data signal and the timing synchronization signal; The writing module is further used to write a frame header signal of the image data stream; The video output module is further used to read the frame header signal using the DE signal as a read signal; The timing synchronization device also includes: A judgment module is used to judge whether the synchronization control signal delayed by the preset number of clock cycles and the read frame header signal are both valid. If both are valid, they are in a synchronized state; if at least one is invalid, it is in an out-of-step state, and the trigger module, the writing module and the video output module are controlled to work again.

7. The timing synchronization device according to claim 6, characterized in that: The trigger module is further configured to send the frame header signal to the timing synchronization control module, trigger the timing synchronization control module to output the synchronization control signal according to the first valid frame header of the frame header signal, and trigger the timing synchronization control module to output the timing synchronization signal delayed by a first number of clock cycles relative to the synchronization control signal; The video output module is also used to delay the timing synchronization signal by a second number of clock cycles as a new timing synchronization signal; delay the DE signal of the new timing synchronization signal by a third number of clock cycles as a read signal to read out the valid data signal; delay the new timing synchronization signal by the third number of clock cycles as a final output timing synchronization signal and output it; wherein the preset number is the sum of the first number, the second number and the third number.

8. The timing synchronization device according to claim 7, characterized in that: The first number is 1, the second number is 1, and the third number is 2.

9. The timing synchronization device according to claim 7, characterized in that: Also includes: A preliminary judgment module, used for obtaining a data valid signal and a frame header signal of the image data stream; When it is detected that the current frame header signal and the data valid signal are both valid signals, the state machine is controlled to enter the synchronization state from the initial idle state, and the trigger module and the writing module are controlled to work again; The judgment module is also used to control the state machine to remain in the synchronization state if both are valid, and to control the state machine to jump to the out-of-step state if at least one is invalid, and to control the trigger module and the write module to work again.

10. A PG device, characterized in that: include: A timing synchronization device based on FPGA according to any one of claims 6 to 9.

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