Storage element and method of manufacturing the same

Abstract

The present invention discloses a storage element and a manufacturing method thereof, wherein the storage element comprises: a substrate, a stacked structure, a polysilicon layer, a vertical channel structure and a charge storage structure. The stacked structure is arranged on the substrate. The stacked structure comprises a plurality of dielectric layers and a plurality of conductor layers stacked alternately. The polysilicon layer is arranged between the substrate and the stacked structure. The vertical channel structure penetrates the stacked structure and the polysilicon layer. The charge storage structure is at least arranged between the vertical channel structure and the plurality of conductor layers.

Description

Technical Field

[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a storage element and a manufacturing method thereof. Background Art

[0002] Non-volatile memory (eg, flash memory) has become a widely used memory in personal computers and other electronic devices because it has the advantage that the stored data will not disappear after power failure.

[0003] The three-dimensional flash memory commonly used in the industry at present includes NOR flash memory and NAND flash memory. In addition, another three-dimensional flash memory is AND flash memory, which can be applied to multi-dimensional flash memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional flash memory has gradually become the current trend. Summary of the invention

[0004] The present invention provides a storage element comprising: a substrate, a stacked structure, a polysilicon layer, a vertical channel structure and a charge storage structure. The stacked structure is arranged on the substrate. The stacked structure comprises a plurality of dielectric layers and a plurality of conductor layers stacked alternately. The polysilicon layer is arranged between the substrate and the stacked structure. The vertical channel structure penetrates the stacked structure and the polysilicon layer. The charge storage structure is at least arranged between the vertical channel structure and the plurality of conductor layers.

[0005] In an embodiment of the present invention, the polysilicon layer includes doped polysilicon material, and the doped polysilicon material is P-type doped polysilicon material.

[0006] In one embodiment of the present invention, the vertical channel structure includes: two source / drain columns, which penetrate the stacked structure and the polysilicon layer and partially extend into the substrate; an insulating column, which is arranged between the two source / drain columns to separate the two source / drain columns; and a channel layer, which surrounds the two source / drain columns.

[0007] In one embodiment of the present invention, one of the two source / drain pillars mentioned above includes: a first part, buried in the substrate; and a second part, configured on the first part, wherein the cross-sectional area of ​​the first part is smaller than the cross-sectional area of ​​the second part, and the first part and the second part have the same doped polysilicon material, and the doped polysilicon material is N-type doped polysilicon material.

[0008] In one embodiment of the present invention, the channel layer protrudes downward from the bottom surface of the polysilicon layer, and the distance between the bottom surface of the channel layer and the bottom surface of the polysilicon layer is less than

[0009] In one embodiment of the present invention, the charge storage structure surrounds each conductor layer in the stacked structure, the channel layer protrudes upward from the top surface of the top conductor layer, and the distance between the top surface of the channel layer and the top surface of the corresponding charge storage structure surrounding the top conductor layer is less than

[0010] In one embodiment of the present invention, the charge storage structure is disposed between the channel layer and the stacked structure, the channel layer protrudes upward from the top surface of the topmost conductor layer, and the distance between the top surface of the channel layer and the top surface of the topmost conductor layer is less than

[0011] In one embodiment of the present invention, the above-mentioned channel layer includes: a main body portion, which is arranged between the two source / drain columns and the stacked structure, and between the two source / drain columns and the polysilicon layer; and an extension portion, which is connected to the bottom surface of the main body portion and partially extends into the two source / drain columns.

[0012] In an embodiment of the present invention, the above-mentioned memory element further includes a gate dielectric layer disposed between the polysilicon layer and the channel layer.

[0013] In one embodiment of the present invention, the material of the plurality of conductor layers in the stacked structure is different from the material of the polysilicon layer.

[0014] The present invention provides a method for manufacturing a storage element, comprising: forming an etch stop layer on a substrate; forming a stacked structure on the etch stop layer, wherein the stacked structure includes a plurality of dielectric layers and a plurality of conductor layers stacked alternately; and forming a vertical channel structure penetrating the stacked structure and the etch stop layer.

[0015] In an embodiment of the present invention, the etch stop layer comprises a doped polysilicon material, and the doped polysilicon material is a P-type doped polysilicon material.

[0016] In one embodiment of the present invention, before forming the etch stop layer on the substrate, the method further includes forming two polysilicon layers in the substrate.

[0017] In one embodiment of the present invention, the vertical channel structure includes: two source / drain columns, which penetrate the stacked structure and the etch stop layer and partially extend into the substrate; an insulating column, which is arranged between the two source / drain columns to separate the two source / drain columns; and a channel layer, which surrounds the two source / drain columns.

[0018] In one embodiment of the present invention, one of the two source / drain pillars mentioned above includes: a first part, buried in the substrate; and a second part, configured on the first part, wherein the cross-sectional area of ​​the first part is smaller than the cross-sectional area of ​​the second part, and the first part and the second part have the same doped polysilicon material, and the doped polysilicon material is N-type doped polysilicon material.

[0019] In one embodiment of the present invention, the channel layer protrudes upward from the top surface of the topmost conductor layer, and the distance between the top surface of the channel layer and the top surface of the topmost conductor layer is less than

[0020] In one embodiment of the present invention, the channel layer protrudes downward from the bottom surface of the etch stop layer, and the distance between the bottom surface of the channel layer and the bottom surface of the etch stop layer is less than

[0021] In one embodiment of the present invention, the material of the plurality of conductor layers in the stacked structure is different from the material of the etch stop layer.

[0022] In one embodiment of the present invention, the method further comprises forming a charge storage layer between the stacked structure and the channel layer.

[0023] In one embodiment of the present invention, before forming the plurality of conductive layers, the method further comprises forming a charge storage layer to surround the plurality of conductive layers.

[0024] Based on the above, in this embodiment, a P-type polysilicon layer is formed between the substrate and the stacked structure, so that the P-type polysilicon layer is used as an etch stop layer for subsequent vertical channel holes, thereby avoiding over-etching. In addition, in this embodiment, two N-type polysilicon layers are formed in the substrate, so that the two N-type polysilicon layers are used as etch stop layers for subsequent source / drain holes, thereby avoiding over-etching.

[0025] In addition, in this embodiment, the channel layer protrudes upward from the top surface of the charge storage layer to a depth smaller than and protrude the channel layer downward from the bottom surface of the P-type polysilicon layer to a distance less than distance to effectively reduce unnecessary parasitic leakage current, thereby increasing the operating margin of the storage element. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1R It is a cross-sectional schematic diagram of a manufacturing process of a memory element according to a first embodiment of the present invention.

[0027] Figures 2A to 2R Along the Figures 1A to 1R Schematic diagram of the plane of AA tangent line.

[0028] Figure 3 is a cross-sectional schematic diagram of a memory element according to an alternative embodiment of the present invention.

[0029] Figure 4 and Figure 5 They are Figure 1R Magnified view of the area.

[0030] Figure 6 is a cross-sectional schematic diagram of a storage element according to a second embodiment of the present invention.

[0031] Figure 7 and Figure 8 They are Figure 6 Magnified view of the area.

[0032]

Explanation of symbols

[0033] 1, 2: Storage components

[0034] 10, 12, 16, 18, 20, 22, 24: Open

[0035] 14: Depression

[0036] 30: Slit

[0037] 32: Gap

[0038] 100: Substrate

[0039] 102, 104: Polysilicon layer

[0040] 106: Covering layer

[0041] 108: Polysilicon layer

[0042] 108bt, 132bt: bottom surface

[0043] 108s, 108s′, 112s, 114s, 124s, 128s, 128s′: side wall

[0044] 110, 210: laminated structure

[0045] 110t, 112t, 114t, 132t, 132t′, 133t, 154t: top surface

[0046] 112: Dielectric layer

[0047] 112tm: top dielectric layer

[0048] 114: Sacrificial Layer

[0049] 114tm: top sacrificial layer

[0050] 120, 220: Charge storage layer

[0051] 124, 128: Oxide layer

[0052] 124t, 128t: Thickness

[0053] 130: Vertical channel structure

[0054] 132: Channel layer

[0055] 132a: Channel Materials

[0056] 133: Gap wall

[0057] 133a: Spacer material

[0058] 134: Insulation column

[0059] 135: Dielectric Materials

[0060] 136: First source / drain column

[0061] 138: Second source / drain column

[0062] 142, 144: Polysilicon materials

[0063] 154: Conductor layer

[0064] 154tm: top conductor layer

[0065] 160: Storage unit

[0066] 170: Transistor

[0067] D1, D2, D3, D4, D5: distance

[0068] EP: Extension

[0069] MP: Main body DETAILED DESCRIPTION

[0070] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the accompanying drawings are exaggerated for clarity. The same or similar element numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0071] Figures 1A to 1R FIG. 1 is a cross-sectional schematic diagram of a manufacturing process of a storage element 1 according to a first embodiment of the present invention. Figures 2A to 2R Along the Figures 1A to 1R The following embodiments are described by taking the three-dimensional flash memory as an AND gate (AND) flash memory as an example, but the present invention is not limited thereto.

[0072] Please refer to Figure 1A and Figure 2A First, a substrate 100 is provided. In one embodiment, the substrate 100 includes a dielectric substrate. The dielectric substrate may be a dielectric layer formed on a silicon substrate, such as a silicon oxide layer.

[0073] Next, polysilicon layers 102 and 104 are formed in the substrate 100. In one embodiment, the method for forming the polysilicon layers 102 and 104 may include: forming an opening in the substrate 100; forming a polysilicon material in the opening; and performing a planarization process on the polysilicon material. In one embodiment, the polysilicon layers 102 and 104 may have the same material, such as doped polysilicon material. For example, the polysilicon layers 102 and 104 may be N-type doped (N+) polysilicon layers.

[0074] Afterwards, a cap layer 106 and a polysilicon layer 108 are sequentially formed on the substrate 100. In one embodiment, the material of the cap layer 106 includes a dielectric material, such as silicon oxide. In one embodiment, the material of the polysilicon layer 108 includes a doped polysilicon material. For example, the polysilicon layer 108 may be a P-type doped (P+) polysilicon layer. In an alternative embodiment, the polysilicon layer 108 includes a high work function material, such as a material having a work function higher than 4 eV. In other embodiments, the polysilicon layer 108 may be a material having a work function higher than 4.5 eV. In other embodiments, the polysilicon layer 108 and the polysilicon layers 102 and 104 may have different conductivity types.

[0075] Then, a stacked structure 110 is formed on the polysilicon layer 108, so that the cap layer 106 and the polysilicon layer 108 are disposed between the substrate 100 and the stacked structure 110. Specifically, the stacked structure 110 includes a plurality of dielectric layers 112 and a plurality of sacrificial layers 114 that are alternately stacked. In one embodiment, the dielectric layer 112 and the sacrificial layer 114 may be different dielectric materials. For example, the dielectric layer 112 may be a silicon oxide layer; and the sacrificial layer 114 may be a silicon nitride layer. In one embodiment, the number of the dielectric layer 112 and the sacrificial layer 114 may be 8 layers, 16 layers, 32 layers, 64 layers, or more layers.

[0076] Please refer to Figure 1B and Figure 2B , an opening 10 (also referred to as a first opening) is formed in the stacked structure 110. Figure 1B As shown, the opening 10 penetrates the stacked structure 110 and exposes the polysilicon layer 108. In this embodiment, the polysilicon layer 108 can be regarded as an etch stop layer for forming the opening 10 to avoid over-etching. In this case, the opening 10 can be regarded as a vertical channel opening. In one embodiment, the planar Figure 2BFrom the perspective of FIG. 1 , the opening 10 has a circular profile, but the present invention is not limited thereto. In other embodiments, the opening 10 may have a profile of other shapes, such as an ellipse, a rectangle, a polygon, or a combination thereof.

[0077] Please refer to Figure 1C and Figure 2C , the opening 10 is extended downward to form an opening 12 (also referred to as a second opening) penetrating the polysilicon layer 108. In this embodiment, the cap layer 106 can be regarded as an etch stop layer for forming the opening 12 to avoid over-etching. Figure 1C As shown, the opening 12 may also partially extend into the cap layer 106. In one embodiment, the opening 12 is spatially connected to the opening 10, and the width of the opening 12 is less than or equal to the width of the opening 10. That is, the sidewall 108s of the polysilicon layer 108 may protrude from the sidewall 112s of the dielectric layer 112.

[0078] Please refer to Figure 1D and Figure 2D , a dry etching process is performed on the polysilicon layer 108 to laterally etch the polysilicon layer 108 so that the sidewall 108s′ of the polysilicon layer 108 is recessed inwardly from the sidewall 112s of the dielectric layer 112. In this case, Figure 1D As shown, the recess 14 can be formed between the cap layer 106, the stacked structure 110 and the polysilicon layer 108. In one embodiment, the above-mentioned dry etching process includes a chemical dry etching (CDE) process. The above-mentioned chemical dry etching process includes using an etching gas with high etching selectivity to the polysilicon layer 108. That is, in the above-mentioned dry etching process, the polysilicon layer 108 exposed in the opening 12 is removed, but the cap layer 106, the dielectric layer 112 and the sacrificial layer 114 are not removed or only a small amount is removed. To a certain extent, the above-mentioned dry etching process can avoid the protrusion of the polysilicon layer 108 and can form a smoother profile to facilitate the subsequent deposition process.

[0079] Please refer to Figure 1E and Figure 2E, an oxidation treatment is performed to form an oxide layer 124 (also referred to as a first oxide layer) on the sidewalls 114s of the sacrificial layer 114 exposed in the opening 10, and an oxide layer 128 (also referred to as a second oxide layer) is formed on the sidewalls 108s′ of the polysilicon layer 108 exposed in the opening 12. In one embodiment, the oxide layer 124 and the oxide layer 128 have different materials. For example, the oxide layer 124 may be a silicon oxynitride layer, and the oxide layer 128 may be a silicon oxide layer. In one embodiment, the oxidation treatment includes thermal oxidation, wet oxidation, or a combination thereof. It is worth noting that since the oxidation rate of the polysilicon layer 108 is faster than the oxidation rate of the sacrificial layer 114, the thickness 128t of the oxide layer 128 may be greater than the thickness 124t of the oxide layer 124. Figure 1E As shown, the oxide layer 128 can fill the recess 14, so that the sidewall 128s of the oxide layer 128, the sidewall 112s of the dielectric layer 112, and the sidewall 124s of the oxide layer 124 are substantially coplanar. In other words, the width of the opening 12 can be substantially equal to the width of the opening 10, and the combination of the openings 10 and 12 is referred to as a composite opening 20 in the following paragraphs. However, the present invention is not limited thereto, and in other embodiments, the sidewall 128s of the oxide layer 128, the sidewall 112s of the dielectric layer 112, and the sidewall 124s of the oxide layer 124 may also have a slight difference in height.

[0080] In an alternative embodiment, the above-mentioned dry etching process may be omitted. That is, the polysilicon layer 108 is not etched back laterally. In this case, after the oxidation process, the sidewall 128s′ of the oxide layer 128 may protrude beyond the sidewall 112s of the dielectric layer 112 and the sidewall 124s of the oxide layer 124, as shown in FIG. Figure 3 In this embodiment, the oxide layer 128 may extend to the vertical channel structure 130 (eg, Fig.1O )middle.

[0081] Please refer to Figure 1F and Figure 2F , a channel material 132a is formed on the substrate 100. Specifically, Figure 1F As shown, the channel material 132a conformally covers the top surface of the stacked structure 110 and the surface of the composite opening 20. In one embodiment, the channel material 132a includes undoped polysilicon material or intrinsic polysilicon material, which can be formed by chemical vapor deposition (CVD).

[0082] Please refer to Figure 1G and Figure 2G , a spacer material 133a is formed on the channel material 132a. In one embodiment, the spacer material 133a includes a low temperature oxide (LTO), and the formation method thereof may be a low temperature oxide deposition method.

[0083] Please refer to Figure 1H and Figure 2H , a first anisotropic etching process is performed to remove the spacer material 133a on the top surface of the stacked structure 110 and the bottom surface of the composite opening 20, thereby forming a spacer 133 on the sidewall of the composite opening 20. In one embodiment, the first anisotropic etching process includes a reactive ion etching (RIE) process.

[0084] Please refer to Fig. 1I and Fig.2I , a second anisotropic etching process is performed to remove the channel material 132a on the top surface of the stacked structure 110 and the bottom surface of the composite opening 20, thereby forming a channel layer 132. Specifically, as Fig. 1I As shown, the channel layer 132 is also formed in the form of a spacer between the stacked structure 110 and the spacer 133, and between the polysilicon layer 108 and the spacer 133. In one embodiment, the top surface 132t of the channel layer 132 may be coplanar with the top surface 110t of the stacked structure 110, and the top surface 132t of the channel layer 132 may be lower than the top surface 133t of the spacer 133. In one embodiment, the second anisotropic etching process includes a reactive ion etching (RIE) process.

[0085] Please refer to Figure 1J and Figure 2J , using the spacer 133 as a mask, an over-etching process is performed on the channel layer 132, thereby adjusting the height of the channel layer 132. In one embodiment, the top surface 132t′ of the channel layer 132 can be lowered to be lower than the top surface 110t of the stacked structure 110. For example, the top surface 132t′ of the channel layer 132 can be between the top surface 112t of the topmost dielectric layer 112tm and the top surface 114t of the topmost sacrificial layer 114tm. In this embodiment, the distance D1 between the top surface 132t′ of the channel layer 132 and the top surface 114t of the topmost sacrificial layer 114tm is less than In one embodiment, the distance D1 may be between to In an alternative embodiment, the distance D1 may be between to In some embodiments, the over-etching process includes using an etching gas having a high etching selectivity to the channel layer 132. That is, in the over-etching process, most of the channel layer 132 is removed, but the cap layer 106, the dielectric layer 112 and the spacer 133 are not removed or only a small amount is removed.

[0086] Please refer to Figure 1K and Figure 2KAfter adjusting the height of the channel layer 132, the spacers 133 are removed to expose the channel layer 132. In one embodiment, the method of removing the spacers 133 may include wet etching, dry etching or a combination thereof.

[0087] Please refer to Figure 1K to Figure 1L and Figure 2K to Figure 2L , a dielectric material 135 is formed in the composite opening 20, and an insulating column 134 is formed in the dielectric material 135. Specifically, the dielectric material 135 is formed in the composite opening 20 by chemical vapor deposition. It is worth noting that the dielectric material 135 does not fill the composite opening 20, but retains the central portion of the composite opening 20. Afterwards, an insulating column 134 is formed in the composite opening 20 to fill the central portion of the composite opening 20. In one embodiment, the insulating column 134 and the dielectric material 135 may have different dielectric materials. For example, the insulating column 134 may be silicon nitride, and the dielectric material 135 may be silicon oxide. In other embodiments, the composite opening 20 may be filled with the dielectric material 135 first, and then a central opening is formed in the dielectric material 135, and the central opening is filled with the insulating column 134. In this embodiment, the insulating column 134 may penetrate the dielectric material 135 and the cap layer 106 to contact the substrate 100 between the polysilicon layers 102 and 104.

[0088] Please refer to Figure 1M and Figure 2M , two openings 16 and 18 (also referred to as third openings) are formed in the dielectric material 135. Specifically, the opening 16 penetrates the dielectric material 135 and the cap layer 106 to expose the polysilicon layer 102 in the substrate 100; and the opening 18 penetrates the dielectric material 135 and the cap layer 106 to expose the polysilicon layer 104 in the substrate 100. In this case, the openings 16 and 18 can be regarded as source / drain openings. In one embodiment, the planar Figure 2M From the perspective of the embodiment, the openings 16 and 18 have a circular profile, but the present invention is not limited thereto. In other embodiments, the openings 16 and 18 may have profiles of other shapes, such as an ellipse, a rectangle, a polygon, or a combination thereof. In the present embodiment, the openings 16 and 18 are respectively formed on opposite sides of the insulating column 134 and are not in contact with the insulating column 134 and the channel layer 132, but the present invention is not limited thereto. In other embodiments, the openings 16 and 18 may be in contact with the insulating column 134 and / or the channel layer 132. The openings 16 and 18 may be used to define the location of the source / drain of the storage element of the present embodiment. In the present embodiment, the layout for forming the openings 16 and 18 is the same as the layout for forming the polysilicon layers 102 and 104. That is, the above two processes may be applied to the same mask to reduce manufacturing costs.

[0089] Please refer to Figure 1N and Figure 2N, widening the cross-sectional area of ​​the openings 16, 18 so that the widened openings 22, 24 are respectively in contact with the insulating pillars 134 and / or the channel layer 132. In one embodiment, the method of widening the openings 16, 18 is, for example, performing an isotropic etching process on the openings 16, 18. In detail, when performing the isotropic etching process, the insulating pillars 134 (for example, silicon nitride), the channel layer 132 (for example, polysilicon) and the polysilicon layers 102, 104 are used as etching stop layers to remove the dielectric material 135 (for example, silicon oxide) around the openings 16, 18. In this case, the widened openings 22, 24 can be in contact with the insulating pillars 134 and / or the channel layer 132, such as Figure 2N However, the present invention is not limited thereto. In other embodiments, Figure 1N As shown, one side of the widened openings 22 , 24 may contact the channel layer 132 , while the other side of the widened openings 22 , 24 does not contact the insulating pillar 134 .

[0090] Please refer to Fig.1O and Fig.2O , polysilicon materials 142 and 144 are respectively filled into the widened openings 22 and 24 to contact the polysilicon layers 102 and 104, thereby forming the first source / drain column 136 and the second source / drain column 138 of the storage element of this embodiment. In this embodiment, the polysilicon materials 142 and 144 have the same material as the polysilicon layers 102 and 104, for example, N-type doped (N+) polysilicon material. In this case, the first source / drain column 136 may include the polysilicon layer 102 buried in the substrate 100 (also referred to as the first part) and the polysilicon material 142 (also referred to as the second part) disposed on the polysilicon layer 102. In addition, the second source / drain column 138 may also include the polysilicon layer 104 buried in the substrate 100 and the polysilicon material 144 disposed on the polysilicon layer 104. As Fig.2O As shown, the cross-sectional area of ​​the polysilicon layers 102 and 104 (indicated by the dotted lines) is smaller than the cross-sectional area of ​​the polysilicon materials 142 and 144, and the polysilicon layers 102 and 104 are located within the polysilicon materials 142 and 144. After the source / drain pillars 136 and 138 are formed, the vertical channel structure 130 of the present invention is completed. Fig.1OAs shown, the vertical channel structure 130 penetrates the stacked structure 110, the polysilicon layer 108, and the cap layer 106 to contact the substrate 100. Specifically, the vertical channel structure 130 may include a channel layer 132, an insulating column 134, a dielectric material 135, a first source / drain column 136, and a second source / drain column 138. The first source / drain column 136 and the second source / drain column 138 penetrate the dielectric material 135 and partially extend into the substrate 100. The insulating column 134 is disposed between the first source / drain column 136 and the second source / drain column 138 to separate the first source / drain column 136 from the second source / drain column 138. In addition, as shown in the planar Fig.2O As shown, the channel layer 132 laterally surrounds the insulating pillar 134 , the dielectric material 135 , the first source / drain pillar 136 , and the second source / drain pillar 138 .

[0091] After forming the vertical channel structure 130, a gate replacement process may be performed to replace the sacrificial layer 114 in the stacked structure 110 with the conductor layer 154, such as Figure 1P to Figure 1R and Figure 2P to Figure 2R shown.

[0092] First, please refer to Figure 1P and Figure 2P A slit 30 is formed in the stacked structure 110 next to the vertical channel structure 130. The slit 30 penetrates the stacked structure 110, the polysilicon layer 108, and the cap layer 106 to expose a portion of the substrate 100. Figure 1P The bottom surface of the slit 30 is shown to be lower than the bottom surface of the cap layer 106, but the present invention is not limited thereto. In other embodiments, as long as the bottom surface of the slit 30 is equal to or lower than the bottom surface of the bottom sacrificial layer 114bm, it is within the scope of protection of the present invention.

[0093] Next, please refer to Figure 1Q and Figure 2Q , an etching process is performed to remove the sacrificial layer 114 to form a plurality of gaps 34 between the dielectric layers 112. The gaps 34 laterally expose the oxide layer 124. That is, the gaps 34 are defined by the dielectric layer 112 and the oxide layer 124. It is worth noting that the oxide layer 124 can be regarded as an etching stop layer of the above-mentioned etching process to avoid excessive etching and thus damaging the channel layer 132. In one embodiment, the etching process can be a wet etching process. For example, when the sacrificial layer 114 is silicon nitride, the etching process can be using an etching solution containing phosphoric acid, and pouring the etching solution into the slit 30 to remove the sacrificial layer 114. Since the etching solution has a high etching selectivity for the sacrificial layer 114, the sacrificial layer 114 can be completely removed, while the dielectric layer 112, the polysilicon layer 108 and the cap layer 106 are not removed or only a small amount is removed.

[0094] Please refer to Figure 1R and Figure 2R , a charge storage layer 120 and a conductor layer 154 are sequentially formed in the gap 34, thereby completing the storage element 1 of the present invention. Specifically, as Figure 1R As shown, the charge storage layer 120 conformally covers the gap 34 to surround the conductor layer 154. In one embodiment, the charge storage layer 120 can be a composite layer of oxide / nitride / oxide (ONO), a composite layer of oxide / nitride / oxide / nitride / oxide (ONONO), a composite layer of silicon / oxide / nitride / oxide / silicon (SONOS), or other suitable materials. In one embodiment, the material of the conductor layer 154 is, for example, polysilicon, amorphous silicon, tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSi x ) or cobalt silicide (CoSi x ). In addition, after forming the charge storage layer 120 and before forming the conductor layer 154, a buffer layer and a barrier layer may be sequentially formed between the charge storage layer 120 and the conductor layer 154. The material of the buffer layer is, for example, a high dielectric constant material having a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or a combination thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0095] In this embodiment, the memory element 1 has a plurality of memory cells 160. Specifically, Figure 1R As shown, in the memory element 1, there are four memory cells 160 stacked one on top of another. However, the present invention is not limited thereto. In other embodiments, the number of memory cells 160 can be adjusted according to the number of conductor layers 154 in the stacked structure 210. Figure 1R and Figure 2R Only a single vertical channel structure 130 is shown, but the present invention is not limited thereto. In an alternative embodiment, the memory element 1 may include a plurality of vertical channel structures 130, and the vertical channel structures 130 may be arranged in an array in a top view.

[0096] In order to operate the memory element 1, after manufacturing the memory element 1, conductive lines are formed above the memory element 1 to be electrically connected to the memory element 1. In the present embodiment, some conductive lines formed above and electrically connected to the first source / drain pillars 136 as sources serve as source lines, and other conductive lines formed above and electrically connected to the second source / drain pillars 138 as drains serve as bit lines, and these source lines and bit lines are arranged in parallel with each other without contacting each other.

[0097] Next, the operation of the memory cell 160 in the memory element 1 will be described.

[0098] For the memory element 1, each memory cell 160 can be operated individually. An operating voltage can be applied to the first source / drain column 136, the second source / drain column 138 and the corresponding conductor layer 154 (which can be regarded as a gate or a word line) of the memory cell 160 to perform a write (program) operation, a read operation or an erase operation. When a write voltage is applied to the first source / drain column 136 and the second source / drain column 138, since the first source / drain column 136 and the second source / drain column 138 are connected to the channel layer 132, electrons can be transmitted along the first electrical path E1 and the second electrical path E2 (for example, a double-sided electrical path) and stored in the entire charge storage structure.

[0099] It is worth noting that the storage element 1 further includes a transistor 170 disposed between the stacked structure 210 and the substrate 100. In this embodiment, the transistor 170 may be, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET). Figure 1R As shown, the transistor 170 may include a polysilicon layer 108 used as a gate, an oxide layer 128 used as a gate dielectric layer, a first source / drain pillar 136 used as a source, and a second source / drain pillar 138 used as a drain. When performing a read operation on the upper memory cell 160, 0V or grounding may be applied to the polysilicon layer 108 to turn off unnecessary parasitic leakage current, thereby improving the performance of the memory element 1.

[0100] Figure 4 Plotted as Figure 1R is an enlarged view of area 140, and Figure 5 Plotted as Figure 1R An enlarged view of area 150.

[0101] Please refer to Figure 4 , the top surface 132t′ of the channel layer 132 may be between the top surface 112t of the topmost dielectric layer 112tm and the top surface 120t of the charge storage layer 120. In this embodiment, the distance D2 between the top surface 132t′ of the channel layer 132 and the top surface 120t of the charge storage layer 120 is less than In one embodiment, the distance D2 may be between to In an alternative embodiment, the distance D2 may be between to It is worth noting that when the distance D2 of the channel layer 132 protruding from the top surface 120t of the charge storage layer 120 is greater than When the top conductor layer 154tm is operated, unnecessary parasitic leakage current will be generated, thereby affecting the performance of the storage element 1. Therefore, the present invention controls the distance D2 of the channel layer 132 protruding from the top surface 120t of the charge storage layer 120 to be less than The unnecessary parasitic leakage current is effectively reduced, thereby increasing the operation window of the storage element 1 .

[0102] Please refer to Figure 5 , the bottom surface 132bt of the channel layer 132 may protrude downward from the bottom surface 108bt of the polysilicon layer 108. In this embodiment, the distance D3 between the bottom surface 132bt of the channel layer 132 and the bottom surface 108bt of the polysilicon layer 108 is less than In one embodiment, the distance D3 may be between to In an alternative embodiment, the distance D3 may be between to It is worth noting that when the distance D3 of the channel layer 132 protruding from the bottom surface 108bt of the polysilicon layer 108 is greater than When the channel layer 132 is extended beyond the bottom surface 108bt of the polysilicon layer 108, unnecessary parasitic leakage current will be generated during the read operation, thereby affecting the performance of the storage element 1. Therefore, the present invention controls the distance D3 of the channel layer 132 protruding from the bottom surface 108bt of the polysilicon layer 108 to be less than 200A, so as to effectively reduce the unnecessary parasitic leakage current, thereby increasing the operation margin of the storage element 1.

[0103] In one embodiment, if Figure 5 As shown, the channel layer 132 may include a main body MP and an extension EP. The main body MP is disposed between the source / drain column 138 (or 136) and the stacked structure 210, and between the source / drain column 138 (or 136) and the polysilicon layer 108. The extension EP is connected to the bottom surface of the main body MP and extends laterally into the source / drain column 138 (or 136). In some embodiments, the thickness of the extension EP is substantially equal to the distance D3, that is, the thickness of the extension EP may be less than

[0104] The storage element 1 of the first embodiment described above uses an oxide / nitride / oxide last (ONO last) process to form the charge storage layer 120. However, the present invention is not limited thereto, and the storage element 2 of the second embodiment may also use an ONO first (ONO first) process to form the charge storage layer 220. Please refer to the following paragraphs for detailed description.

[0105] Figure 6 is a cross-sectional schematic diagram of a storage element 2 according to a second embodiment of the present invention. Figure 7 Plotted as Figure 6 An enlarged view of area 270, and Figure 8 Plotted as Figure 6 An enlarged view of area 280.

[0106] Please refer to Figure 6 , the storage element 2 of the second embodiment is similar to the storage element 1 of the first embodiment, and the same or similar components are represented by the same or similar component numbers, which will not be repeated here. The main difference between the above two is that the charge storage layer 220 of the storage element 2 is configured between the channel layer 132 and the stacked structure 210. Specifically, the method for forming the charge storage layer 220 may include: before the channel material is formed, forming a charge storage material to conformally cover the top surface of the stacked structure 110 and the surface of the composite opening 20; and performing an anisotropic etching process to remove the charge storage material on the top surface of the stacked structure 110 and the bottom surface of the composite opening 20, thereby forming the charge storage layer 220 on the sidewalls of the composite opening 20. In other words, the charge storage layer 220 is formed on the sidewalls of the composite opening 20 in the form of a spacer. After the charge storage layer 220 is formed, Figure 1F to Figure 1K The channel layer 132 is formed by the steps of Figure 1L to Figure 1R The vertical channel structure 130 and the conductor layer 154 are formed by the steps of Figure 6 As shown, the channel layer 132 and the charge storage layer 220 may extend continuously in a direction perpendicular to the top surface of the substrate 100 .

[0107] In addition, during the gate replacement process, since the charge storage layer 220 has been formed between the channel layer 132 and the stacked structure 110, the conductive layer 154 is filled into the gap 34 between the dielectric layers 112 (eg, Figure 1Q ), the conductor layer 154 may directly contact the adjacent dielectric layer 112 and the corresponding oxide layer 124. In an alternative embodiment where the oxide layer 124 is not formed, the conductor layer 154 may directly contact the charge storage layer 220.

[0108] It is worth noting that Figure 7 As shown, the channel layer 132 and the charge storage layer 220 of the storage element 2 protrude upward from the top surface 154t of the topmost conductive layer 154tm, and the distance D4 between the top surface 132t′ of the channel layer 132 and the top surface 154t of the topmost conductive layer 154tm is less than In one embodiment, the distance D4 may be between to In an alternative embodiment, the distance D4 may be between to It is worth mentioning that when the distance D4 of the channel layer 132 protruding from the top surface 154t of the topmost conductor layer 154tm is greater than When the top conductor layer 154tm is operated, unnecessary parasitic leakage current will be generated, thereby affecting the performance of the storage element 2. Therefore, the present invention controls the distance D4 of the channel layer 132 protruding from the top surface 154t of the top conductor layer 154tm to be less than This effectively reduces unnecessary parasitic leakage current, thereby increasing the operating margin of the storage element 2 .

[0109] In addition, please refer to Figure 8 , the channel layer 132 and the charge storage layer 220 protrude downward from the bottom surface 108bt of the polysilicon layer 108, and the distance D5 between the bottom surface 132bt of the channel layer 132 and the bottom surface 108bt of the polysilicon layer 108 is less than In one embodiment, the distance D5 may be between to In an alternative embodiment, the distance D5 may be between to It is worth noting that when the distance D5 of the channel layer 132 protruding from the bottom surface 108bt of the polysilicon layer 108 is greater than When the channel layer 132 protrudes from the bottom surface 108bt of the polysilicon layer 108, unnecessary parasitic leakage current will be generated during the reading operation, thereby affecting the performance of the storage element 2. Therefore, the present invention controls the distance D5 of the channel layer 132 protruding from the bottom surface 108bt of the polysilicon layer 108 to be less than This effectively reduces unnecessary parasitic leakage current, thereby increasing the operating margin of the storage element 2 .

[0110] In summary, in this embodiment, a P-type polysilicon layer is formed between the substrate and the stacked structure, so that the P-type polysilicon layer is used as an etching stop layer for subsequent vertical channel openings, thereby avoiding over-etching. In addition, in this embodiment, two N-type polysilicon layers are formed in the substrate, so that the two N-type polysilicon layers are used as etching stop layers for subsequent source / drain openings, thereby avoiding over-etching.

[0111] In addition, in this embodiment, the channel layer protrudes upward from the top surface of the charge storage layer to a depth smaller than and protrude the channel layer downward from the bottom surface of the P-type polysilicon layer to a distance less than distance to effectively reduce unnecessary parasitic leakage current, thereby increasing the operating margin of the storage element.

[0112] So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings.

[0113] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage element, wherein: include: substrate; A stacked structure, disposed on the substrate, wherein the stacked structure comprises a plurality of dielectric layers and a plurality of conductor layers stacked alternately; A polysilicon layer, disposed between the substrate and the stacked structure; A vertical channel structure, penetrating the stacked structure and the polysilicon layer; a charge storage structure, disposed at least between the vertical channel structure and the plurality of conductor layers; as well as A transistor, disposed between the substrate and the stacked structure, the transistor comprising the polysilicon layer; Wherein, the vertical channel structure comprises: Two source / drain posts, penetrating the stacked structure and the polysilicon layer, and partially extending into the substrate; An insulating column, disposed between the two source / drain columns to separate the two source / drain columns; a channel layer surrounding the two source / drain pillars; and A dielectric material separates the insulating column and the channel layer.

2. The memory element according to claim 1, wherein: The polysilicon layer includes doped polysilicon material, and the doped polysilicon material is a P-type doped polysilicon material.

3. The memory element according to claim 1, wherein: One of the two source / drain posts comprises: A first portion embedded in the substrate; and The second part is arranged on the first part, wherein the cross-sectional area of ​​the first part is smaller than the cross-sectional area of ​​the second part, and the first part and the second part have the same doped polysilicon material, and the doped polysilicon material is N-type doped polysilicon material.

4. The memory element according to claim 1, wherein: The channel layer protrudes downward from the bottom surface of the polysilicon layer, and the distance between the bottom surface of the channel layer and the bottom surface of the polysilicon layer is less than 200Å.

5. The memory element according to claim 1, wherein The charge storage structure surrounds each conductor layer in the stacked structure, the channel layer protrudes upward from the top surface of the topmost conductor layer, and the distance between the top surface of the channel layer and the top surface of the corresponding charge storage structure surrounding the topmost conductor layer is less than 200Å.

6. The memory element according to claim 1, wherein: The charge storage structure extends continuously between the channel layer and the stacked structure, the channel layer protrudes upward from the top surface of the topmost conductor layer, and the distance between the top surface of the channel layer and the top surface of the topmost conductor layer is less than 200Å.

7. The memory element according to claim 1, wherein: The channel layer comprises: a main body portion, disposed between the two source / drain columns and the stacked structure, and disposed between the two source / drain columns and the polysilicon layer; and The extension portion is connected to the bottom surface of the main body portion and partially extends into the two source / drain columns.

8. The memory element according to claim 1, wherein The invention also includes a gate dielectric layer configured between the polysilicon layer and the channel layer.

9. The memory element according to claim 1, wherein: The material of the plurality of conductor layers in the stacked structure is different from the material of the polysilicon layer.

10. A method for manufacturing a memory element, wherein: include: forming an etch stop layer on the substrate; forming a stacked structure on the etch stop layer, wherein the stacked structure comprises a plurality of dielectric layers and a plurality of conductor layers stacked alternately; as well as A vertical channel structure is formed that penetrates the stacked structure and the etch stop layer, wherein the vertical channel structure comprises two source / drain columns, an insulating column, a channel layer, and a dielectric material; the two source / drain columns penetrate the stacked structure and the etch stop layer and partially extend into the substrate; the insulating column is disposed between the two source / drain columns to separate the two source / drain columns; and the channel layer surrounds the two source / drain columns; The dielectric material separates the insulating pillar and the channel layer; Wherein, the method further comprises: A transistor is formed between the stacked structure and the substrate, wherein the transistor includes the etch stop layer.

11. The method for manufacturing a memory element according to claim 10, wherein: The etch stop layer includes doped polysilicon material, and the doped polysilicon material is a P-type doped polysilicon material.

12. The method for manufacturing a memory element according to claim 10, wherein: Before forming the etch stop layer on the substrate, the method further includes forming two polysilicon layers in the substrate.

13. The method for manufacturing a memory element according to claim 12, wherein: One of the two source / drain posts comprises: A first portion embedded in the substrate; and The second part is arranged on the first part, wherein the cross-sectional area of ​​the first part is smaller than the cross-sectional area of ​​the second part, and the first part and the second part have the same doped polysilicon material, and the doped polysilicon material is N-type doped polysilicon material.

14. The method for manufacturing a memory element according to claim 12, wherein: The channel layer protrudes upward from a top surface of the topmost conductor layer, and a distance between the top surface of the channel layer and the top surface of the topmost conductor layer is less than 200Å.

15. The method for manufacturing a memory element according to claim 12, wherein: The channel layer protrudes downward from the bottom surface of the etch stop layer, and the distance between the bottom surface of the channel layer and the bottom surface of the etch stop layer is less than 200Å.

16. The method for manufacturing a memory element according to claim 12, wherein: The material of the plurality of conductor layers in the stacked structure is different from the material of the etch stop layer.

17. The method for manufacturing a memory element according to claim 12, wherein: The method also includes forming a charge storage layer between the stacked structure and the channel layer. 18 . The method for manufacturing a memory element according to claim 10 , wherein before forming the plurality of conductor layers, the method further comprises forming a charge storage layer to surround the plurality of conductor layers.

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