Method of forming a wrap-around gate input / output by selective epitaxial regrowth

Abstract

Electronic devices and forming methods having fin structures with surrounding gate non-I / O devices and I / O devices are described. A plurality of dummy gates are etched to expose a fin including alternating layers of a first material and a second material. The layers of the second material are removed to create openings, and the remaining layers of the first material are epitaxially grown to form fin structures.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to semiconductor devices, and more particularly to horizontally surrounding gate device structures and methods and apparatus for forming horizontally surrounding gate device structures. Background Technology

[0002] Transistors are critical components in most integrated circuits. Since the drive current and therefore speed of a transistor are proportional to its gate width, faster transistors typically require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and "fin-field-effect transistors" (finFETs) have been developed to resolve this conflict between maximizing drive current and minimizing size. FinFETs are characterized by significantly increasing transistor size through fin-shaped channel regions without substantially increasing the transistor's footprint, and are currently used in many integrated circuits. However, finFETs also have their own drawbacks.

[0003] As the feature size of transistor devices continues to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, fin field-effect transistor (FFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure comprises multiple lattice-matched channels suspended in a stacked manner and connected by source / drain regions. The hGAA structure is believed to provide good electrostatic control and will be widely used in complementary metal-oxide-semiconductor (CMOS) wafer fabrication.

[0004] Logic gate performance is related to the material properties used, as well as the thickness and area of ​​the structural layers. However, challenges arise when some gate characteristics are tuned to accommodate device scaling. Furthermore, the space between the pillars of a horizontal gate-all-around (hGAA) device limits the thickness of the gate dielectric material for the I / O transistors.

[0005] In the natural process of fabricating hGAA structures, the I / O devices require high drive current. It has been found that having a Si / SiGe sequence as in conventional processes is detrimental to I / O performance, especially in the case of NMOS devices. The GAA structure is also unsuitable for I / O devices. Therefore, there is a need to improve the method for forming horizontally wrapped gate devices to enable the formation of fin-like structures. Summary of the Invention

[0006] One or more embodiments of this disclosure pertain to a method of forming a semiconductor device. A plurality of dummy gates are etched from a substrate surface onto a plurality of fins. The plurality of fins extend along a first direction, while the dummy gates extend along a second direction intersecting the first direction. Etching the plurality of dummy gates exposes portions of the plurality of fins, such that several portions of the fins on the substrate surface are covered by the dummy gates, and several portions of the fins are exposed. The fins comprise alternating layers of a first material and a second material. Gate oxide is removed through trenches formed by etching the dummy gates. Second material layers are etched from the plurality of fins through the trenches, resulting in alternating first material layers and openings. First material is epitaxially grown through the trenches to merge the first material layers into first material junctions.

[0007] Additional embodiments of the disclosure are directed to semiconductor devices including non-I / O gate regions, I / O gate regions, source-drain non-I / O regions, pFET regions, and nFET regions.

[0008] Further embodiments of this disclosure pertain to a semiconductor device comprising a non-I / O gate region and non-I / O gate contacts having a gate-all-around structure. The gate-all-around structure includes a plurality of spaced nanosheets. The device includes an I / O gate region comprising a finFET and an I / O contact; a source-drain non-I / O region comprising a source contact and a drain contact; and a pFET region comprising an epitaxially grown first material and a pFET contact. The epitaxially grown first material has a length, a width, and a height. The width has a plurality of spaced protrusions aligned with the spaced nanosheets. The device further includes an nFET region comprising an epitaxially grown second material and an nFET contact. Attached Figure Description

[0009] To gain a more detailed understanding of the features of this disclosure described above, a more specific description of the disclosure can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be considered as limiting its scope, as other equivalent embodiments are permissible.

[0010] Figures 1 to 11F The manufacturing stages of an electronic device according to one or more embodiments of this disclosure are shown;

[0011] Figures 12A to 12F An electronic device according to one or more embodiments of the disclosed content is shown; and

[0012] Figure 13 Showing Figure 12E An expanded view of region XII shown.

[0013] For ease of understanding, the same reference numerals are used where possible to denote common elements in all figures. The figures are not drawn to scale and have been simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further reiteration. Detailed Implementation

[0014] Before describing several exemplary embodiments of this disclosure, it is to be understood that this disclosure is not limited to the details of the construction or process steps listed in the following description. This disclosure can be implemented in various ways or in other embodiments.

[0015] As used in this specification and the appended claims, the term "substrate" refers to a surface on which a process is performed, or a portion thereof. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may also refer only to a portion of a substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0016] As used herein, “substrate” refers to any substrate or material surface formed on a substrate over which a film treatment is performed during a manufacturing process. For example, substrate surfaces that can be treated include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials (such as metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any film treatment steps disclosed in this disclosure may also be performed on a substrate layer formed on the substrate, as detailed below, and the term “substrate surface” is intended to include such a substrate layer as indicated in the context. Thus, for example, when a film / layer or a portion of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017] In this specification and the appended claims, the terms "precursor", "reactant", "reactive gas", etc., are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0018] As used herein, the term "gate all around (GAA)" refers to an electronic device (e.g., a transistor) in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires or nanoplates, strip channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal strips, such that the GAA transistor is a stacked horizontal gate all around (hGAA) transistor.

[0019] One or more embodiments of this disclosure pertain to a method for forming conventional fin-like structures for I / O devices in logic. Some embodiments advantageously retain the non-I / O devices as nanosheets / nanoplates in post-finFET technology. Some embodiments of this disclosure advantageously provide an additional process to the conventional hGAA process flow, where a SiGe plate is removed for GAA work function metal deposition after the gate oxide layer is etched. In some embodiments, ODL (or SOH) deposition follows SiGe removal, after which the non-I / O regions are masked. In the exposed I / O regions, the ODL is stripped, and silicon is epitaxially regrowth between and on the nanoplates until they are clipped. Once the silicon has been sufficiently grown, an etch-back process (e.g., using HCl) is performed to recess the sidewalls of the nanoplates and make the sidewalls vertical, resulting in a fin-like structure made of crystalline silicon in the I / O device. In some embodiments, the hard mask and ODL are removed from the non-I / O devices, and work function metal is deposited as GAA on the outer surface of the regrowth fins on the non-I / O sides and the I / O devices.

[0020] One or more embodiments of the disclosed content are described with reference to the accompanying drawings. Figure 1 An electronic device 100 according to one or more embodiments of the disclosure is illustrated. The electronic device 100 includes a plurality of fins 110 on a substrate surface 102. Each figure illustrates an embodiment having three fins 110 separated by grooves 111; however, those skilled in the art will recognize that there may be more or fewer than three fins 110. The fins 110 have a length extending along a first direction 191 (also referred to as the X direction), a width extending along a second direction 192 (also referred to as the Y direction), and a height extending along a third direction 193 (also referred to as the Z direction). The term "horizontal" is used to refer to the plane formed by the first direction 191 and the second direction 192 (also referred to as the XY plane). The term "vertical" is used to refer to the third direction 193. The terms "horizontal" and "vertical" are used to describe relative directionality and should not be interpreted as any particular relationship relative to gravity. In some embodiments, the number of fins 110 is a multiple of three.

[0021] The fin 110 comprises alternating layers of a first material 112 and a second material 114. In some embodiments, the first material 112 and the second material 114 are different materials. In some embodiments, the first material 112 comprises at least one III-V material, and the second material 114 comprises at least one III-V material, thus the first material 112 and the second material 114 comprise different materials. In some embodiments, the first material 112 comprises silicon (Si). In some embodiments, the second material 114 comprises silicon germanium (SiGe). The first material 112 and the second material 114 can be of any suitable thickness and can be deposited by any suitable technique known to those skilled in the art. The layer of the first material 112 and the second material 114 is also referred to as a nanosheet.

[0022] Fins 110 are formed on a substrate 101 comprising a variety of materials. Those skilled in the art will recognize that the materials described herein are merely representative of possible materials and should not be limited to these materials. In the illustrated embodiment, two fins 110 are formed on p-type doped silicon 117, and one fin 110 is formed on n-type doped silicon 118. Between the p-type doped silicon 117 and the n-type doped silicon 118 is a shallow trench isolation (STI) oxide 119.

[0023] Gate oxide 120 is formed on surface 102 of substrate 101, covering a plurality of fins 110. Gate oxide 120 can be any suitable material deposited by any suitable technique known to those skilled in the art. In some embodiments, gate oxide 120 is deposited as a conformal layer by atomic layer deposition (ALD) process. In some embodiments, gate oxide 120 is a thermally grown oxide. In one or more embodiments, gate oxide comprises silicon oxide.

[0024] Figure 2 Showing Figure 1The implementation describes the patterning of multiple dummy gates 200 and the removal of exposed gate oxide 120. The dummy gates 200 extend along a second direction 192, intersecting the first direction 191 at an angle. In some implementations, the angle is in the range of 30° to 150°, or 45° to 135°, or 60° to 120°, or 75° to 105°, or 80° to 100°. In some implementations, the angle formed by the intersection of the first direction 191 and the second direction 192 is 90°. Multiple dummy gates 200 are formed on multiple fins 110 such that portions 210 of the fins 110 are covered by the dummy gates 200, while portions 220 of the fins 110 are exposed in the gaps 215 between the dummy gates 200. In some implementations, the dummy gates 200 are deposited, masked, patterned, and etched using any suitable technique. In some embodiments, etching the dummy gate 200 forms a trench 215, exposing a portion 220 of the fin 110 having gate oxide 120. In the illustrated embodiment, the dummy gate 200 shows a dummy gate material 202 topped with a hard mask 204. The dummy gate material 202 can be any suitable material known to those skilled in the art. In some embodiments, the dummy gate material 202 comprises amorphous silicon. The hard mask 204 can be any suitable material deposited by any suitable technique and patterned by any suitable technique (e.g., photolithography). In some embodiments, the hard mask comprises silicon nitride.

[0025] In some implementations, such as Figure 2 As shown, the gate oxide 120 is etched from the top of the fin 110 exposed in the trench 215. The gate oxide 120 can be etched by any suitable technique known to those skilled in the art. In some embodiments, an anisotropic etching process is used to etch the gate oxide 120. In some embodiments, a reactive ion etching (RIE) process is used to etch the gate oxide 120.

[0026] Figure 3 Diagram and Figure 2 In a similar implementation, the first material 112 and the second material 114, which are not beneath the dummy gate 200, are etched and the inner spacer 116 is formed. The exposed first material 112 and the second material 114 (the portion of the plate or nanosheet not beneath the dummy gate) are etched using any suitable technique known to those skilled in the art. In some embodiments, the first material 112 and the second material 114 are etched using an anisotropic etching process. In some embodiments, the first material 112 and the second material 114 are etched simultaneously with the gate oxide 120. In some embodiments, the first material 112 and the second material 114 are etched separately from the gate oxide 120.

[0027] The second material 114 is recessed into the trench below the dummy gate 200 by a recess distance 215. The recess distance can be any suitable distance. In some embodiments, the recess distance is in the range of 1 to 10 nm, or in the range of 2 to 8 nm, or in the range of 3 to 7 nm, or in the range of 4 to 5 nm. The second material 114 can be recessed by any suitable technique known to those skilled in the art.

[0028] In some embodiments, the inner spacer 116 is deposited as a conformal film covering the exposed portions of the recessed second material 114, the first material 112, the dummy gate 200, and the STI oxide 119 by atomic layer deposition. Following conformal deposition, the inner spacer 116 is cleaned from the top, bottom, and sidewalls of the dummy gate 200 using an anisotropic etching process (e.g., RIE), leaving the inner spacer 116 within the recessed region left by the recessed second material 114. In some embodiments, the inner spacer 116 is removed from the top and bottom surfaces and remains as a sidewall spacer 302 on the sidewalls of the dummy gate (e.g., ...). Figure 4 (As shown). The sidewall spacers 302 may be formed of the same material as the inner spacers 116 or of different materials.

[0029] Figure 4 The diagram illustrates the relationship with Figure 3 In a similar implementation, after depositing, masking, and patterning the sidewall spacers 302 and the hard mask 300, the second material 114 exposed through the hard mask 300 is epitaxially grown to form the pFET of the source-drain non-I / O region. The hard mask 300 is formed on the substrate and patterned to create openings 301 in the source-drain non-I / O region of the electronic device. Fins 110 accessible through the openings in some embodiments are etched between dummy gates 200 to remove the first material 112 from the fins 110. After etching, the second material 114 is epitaxially grown to form the pFET 320 of the source-drain non-I / O region 310.

[0030] The illustrated implementation shows a process in which the pFET is formed before the nFET. However, those skilled in the art will recognize that the nFET can be formed before the pFET and will understand that the figures have been rearranged to accommodate such an implementation.

[0031] In some embodiments, the sidewall spacer 302 is deposited separately from the inner spacer 116 as a conformal film and etched away from the horizontal surface, such that the sidewalls of the dummy gate 200 are covered with the sidewall spacer 302. In some embodiments, the sidewall spacer 302 prevents direct contact between the hard mask 300 and the dummy gate material 202. The sidewall spacer 302 can be deposited and / or etched by any suitable technique known to those skilled in the art. The sidewall spacer 302 can be any suitable material known to those skilled in the art. In some embodiments, the sidewall spacer 302 comprises a low-k dielectric. The hard mask 300 can be any suitable hard mask deposited by any suitable technique known to those skilled in the art.

[0032] Figure 5 The illustration shows the process after removing hard mask 300, forming a new hard mask 400, masking, and patterning hard mask 400. Figure 4 The implementation proceeds as follows: Next, an nFET 420 is epitaxially grown in the nFET region 410. The hard mask 300 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the hard mask 300 is removed by an etching process. A second hard mask 400 is formed and patterned by any suitable technique known to those skilled in the art to create an opening 401 on the nFET region 410. In some embodiments, the nFET is formed prior to the pFET. Those skilled in the art will recognize and understand how to form the nFET and then the pFET without requiring inappropriate experimentation.

[0033] Figure 6 The illustration shows the formation of an optional gate-cut pillar 502 (in Figure 6 (See in the middle) after Figure 5 The implementation method involves removing hard mask 204 and hard mask 400 using any suitable technique known to those skilled in the art. An oxide layer 500 is deposited to fill the space between the dummy gates 200. The oxide layer 500 is deposited using any suitable technique known to those skilled in the art, including but not limited to flowable chemical vapor deposition (FCVD). In some implementations, the oxide layer 500 is silicon oxide deposited via a blanket deposition process, followed by a suitable planarization process (e.g., chemical mechanical planarization) to expose the top 208 of the dummy gates 200 through the oxide layer 500.

[0034] In some embodiments, a pad 510 is deposited on the exposed surface prior to the deposition of the oxide layer 500, after the removal of hard masks 204 and 400. The pad 510 is also referred to as a contact etch-stop layer (CESL). In some embodiments, the pad 510 comprises silicon nitride. In some embodiments, the pad 510 is deposited as a conformal layer by atomic layer deposition. In some embodiments, forming the gate cleavage pillar 502 includes depositing and patterning a hard mask 520 to form an opening 525 to expose the top 501 of the amorphous silicon layer 500, the top 303 of the sidewall spacers 302, and the top 512 of the pad 510. The gate cleavage pillar 502 can be any suitable material, including but not limited to nitrides. In some embodiments, the formation of the gate cleavage pillar 502 is omitted, and therefore no gate cleavage pillar is present in the electronic device. Figure 7 The illustration shows the process after several processes have been performed to remove the dummy gate material 202 (e.g., an amorphous silicon gate). Figure 6 In the embodiment of forming the gate diced pillar 502, the hard mask 520 is removed to expose the top 303 of the sidewall spacer 302, the top 512 of the pad 510, and the top 501 of the oxide layer 500.

[0035] The dummy gate 200 (optionally including dummy gate material 202) is removed, resulting in the formation of trench 600. The dummy gate 200 and dummy gate material 202 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the oxide layer 500 is removed by reactive ion etching (RIE). The dummy gate material 202 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the dummy gate 200 is removed by removing the hard mask 204 in a process selectively removing the oxide layer 500 and the dummy gate material 202, followed by removing the dummy gate material 202 in a process selectively removing the oxide layer 500. In some embodiments, removing the dummy gate material 202 may remove less than 50% of the oxide layer 500.

[0036] The second material 114 layers (nanosheets) are removed through trench 600. As shown, these layers are masked to open I / O areas while protecting non-I / O areas to allow for I / O area fabrication. Layers of the second material 114 are etched through trench 600 from multiple fins 110, forming alternating layers of the first material 112 and openings 610 defined by inner spacers 116 on both sides along a first direction 191. The second material 114 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the second material 114 is selectively etched relative to the first material 112. Removing the second material 114 may allow filling the gaps between the nanosheets. In some embodiments, removing the second material 114 may allow the formation of a pure silicon device. In some embodiments, the first material comprises crystalline silicon (Si) and the second material comprises silicon germanium (SiGe), and an etching process selective for crystalline silicon is used to remove SiGe.

[0037] Figures 7 to 1 Each figure in Figure 1 illustrates the electronic device according to a similar pattern to the six-view diagram. View A of each figure presents an isometric view of the electronic device according to one or more embodiments of this disclosure. Views B through F illustrate the electronic device shown in View A along... Figure 7 The lines shown in Figure A represent slices of the electronics in Figure A. In each figure, view "B" illustrates a slice of the electronics in view "A," with the non-I / O gate shown. In each figure, view "C" illustrates a slice of the electronics in view "A," with the I / O gate shown. In each figure, view "D" illustrates a slice of the electronics in view "A," with the source-drain non-I / O shown. In each figure, view "E" illustrates a slice of the electronics in view "A," with the pFET shown. In each figure, view "F" illustrates a slice of the electronics in view "A," with the nFET shown. For ease of viewing, the lines representing slices "B" through "F" are only shown in [the diagram / image / image]. Figure 7 A, but those skilled in the art will recognize these views in each of Figures 8 through 11. When referring to figure numbers, if the following letters are not present, it refers to all six views of the indicated figure. For example, for Figure 7 The reference refers to Figure 7 A to Figure 7 All of F.

[0038] Figure 8A The illustration shows the results after the deposition of spin hard mask (SOH) 700 and hard mask layer 710. Figure 7The implementation method is as follows. SOH 700 can be any suitable hard mask deposited using any suitable technique. In some implementations, SOH 700 comprises or is substantially composed of spin-coated carbon (SOC). The hard mask layer 710 can be any suitable material, including but not limited to silicon oxynitride (SiON), and deposited using any suitable technique known to those skilled in the art.

[0039] An opening 720 is formed through the hard mask layer 710 and the SOH 700. The opening exposes the I / O area of ​​the electronic device while protecting the transistor gate. The opening 720 can be formed using any suitable technique known to those skilled in the art. In some embodiments, an additional hard mask is deposited on top of the resist and patterned to form the opening in the additional hard mask. The opening is then transferred into the hard mask layer 710 and the SOH 700. In some embodiments, the opening 720 is formed by masking and etching the hard mask layer 710 and the SOH 700 through the opening in the additional hard mask. In some embodiments, the hard mask layer 710 and the SOH 700 are etched simultaneously. In some embodiments, the hard mask layer 710 and the SOH 700 are etched using different processes. Figure 8E and Figure 8F As shown, in some embodiments, openings 720 are formed on the pFET and nFET regions of the electronic device, respectively.

[0040] Figure 9 illustrates the embodiment of Figure 8 after the removal of the hard mask layer 710 and the epitaxial regrowing process performed on the first material 112 through the opening 600. Some embodiments of the epitaxial regrowing process are selective epitaxial processes. In some embodiments, the selective epitaxial process epitaxially grows the first material 112 layer through the opening 600 (also referred to as a trench). In some embodiments, the epitaxial growth results in the first material 112 layers merging into the junction 800 of the first material 112. In some embodiments, the first material 112 comprises silicon, and the epitaxy results in the merging of nanosheets of the first material 112 and clamping the opening 610. In some embodiments, the epitaxial process results in Si... <100> The growth of Si. In some implementations, the epitaxial process leads to the growth of Si. <110> The growth. In some embodiments, the epitaxial process results in the contact 800 having a conical shape (e.g., Figure 9C (As shown) Flat-topped or truncated conical (frustoconical) (e.g.) Figure 9E (As shown).

[0041] Figure 10 illustrates the embodiment of Figure 9 after the fins (contacts 800) have been trimmed by an etching process and the hard mask layer 710 has been stripped through trench 910. In some embodiments, the etching process occurs after the I / O device has been shaped via a cyclic epitaxial growth-etch process. In some embodiments, the etching process includes an HCl etch-back process. In some embodiments, the etch-back process increases the verticality of the sidewalls. In some embodiments, the etch-back process reshapes the nanosheets to reduce the severity of the points formed on top of the contacts 800 to form a fin-FET structure of the I / O device made of crystalline silicon. In some embodiments, the contacts 800 are reshaped by repeated sequential growth and etching processes, and then the SOH 700 is removed to create the opening 910.

[0042] Figure 11 illustrates the embodiment of Figure 10 after several processes. An interlayer dielectric 1300 is formed on the exposed surface. In some embodiments, the interlayer dielectric 1300 is a conformal film deposited by atomic layer deposition. The interlayer dielectric 1300 can be any suitable material known to those skilled in the art.

[0043] After forming the interlayer dielectric 1300, a high-k dielectric 1310 is formed on the interlayer dielectric 1300. The high-k dielectric 1310 can be any suitable material known to those skilled in the art. In some embodiments, the high-k dielectric 1310 comprises or is substantially composed of hafnium oxide. In some embodiments, the high-k dielectric is a conformal film deposited by atomic layer deposition.

[0044] Optional work function metal (WFM) 1320 is formed on high-k dielectric 1310. Optional work function metal 1320 can be any suitable material known to those skilled in the art, deposited using any suitable technique. In some embodiments, work function metal 1320 is a conformal film deposited by atomic layer deposition or physical vapor deposition.

[0045] Gate metal 1330 is formed on optional work function metal 1320. The gate metal can be any suitable material deposited using any suitable technique. In some embodiments, gate metal 1330 includes one or more of cobalt, tungsten, copper, molybdenum, or ruthenium. In some embodiments, gate metal 1330 is deposited using a cover deposition process. In some embodiments, gate metal 1330 is deposited using one or more of atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

[0046] After the gate metal 1330 is formed, the electronic device is planarized to lower the surface 1332 of the gate metal 1330 to expose the top surface 501 of the amorphous silicon layer 500. In some embodiments, planarization is performed by etching or chemical mechanical planarization (CMP).

[0047] Figure 12 illustrates the embodiment of Figure 11 after the formation of various contacts. Those skilled in the art will understand the process of patterning and forming various contacts. In short, in some embodiments, the hard mask layer and resist are formed and patterned using any suitable technique.

[0048] Etching through patterned mask openings creates contact apertures. In some embodiments, the etching process includes anisotropic etching. In some embodiments, the etching process creates apertures selectively for pFETs and nFETs.

[0049] Interlayer dielectric 1300 is removed, while the metal layer is deposited and planarized. The interlayer dielectric 1300 can be removed by any suitable technique known to those skilled in the art. In some embodiments, the metal layer 1700 comprises the same material as the gate metal 1330. In some embodiments, the metal layer 1700 comprises one or more of cobalt, tungsten, copper, or ruthenium. After depositing the metal layer 1700, the electronic device is planarized to lower the surface 1702 of the metal layer 1700 to expose the top surface 501 of the amorphous silicon layer 500. In some embodiments, planarization is performed by etching or chemical mechanical planarization (CMP).

[0050] like Figures 12A to 12F As shown, some embodiments of this disclosure are for the inclusion of a non-I / O gate region 1110 ( Figure 12B ), I / O gate region 1120 ( Figure 12C ), source-drain non-I / O region 1130 ( Figure 12D ), pFET region 1140 ( Figure 12E and nFET region ( Figure 12F Semiconductor device 1100.

[0051] Some embodiments of the electronic device 1100 have a non-I / O gate region 1110 with a gate-all-around structure 1112. In some embodiments, the gate-all-around structure 1112 has a nanosheet core 1111 made of a first material 112 and has an interlayer dielectric 1300 in contact with the first material 112. In some embodiments, a high-k dielectric 1310 contacts the interlayer dielectric 1300 on the side opposite to the first material 112. In some embodiments, a work function metal 1320 contacts the high-k dielectric 1310 on the side opposite to the interlayer dielectric 1310.

[0052] In some embodiments, each nanosheet 1111 made of the first material 112 is spaced a certain distance from the p-type doped silicon 117 along a third direction 193. For example, Figure 12BThe illustration shows two columns of nanosheets 1111 on the right side of the figure, each column spaced a certain distance from the p-type doped silicon 117 material. In some embodiments, each nanosheet 1111 made of the first material 112 is spaced a certain distance from the n-type doped silicon 118 along a third direction 193. For example, Figure 12B The illustration shows a column of nanosheets 1111 on the left side of the figure; this column is spaced apart from the n-type doped silicon 118 material. In some embodiments, each nanosheet 1111 is spaced apart from the adjacent nanosheet 1111 along a third direction 193, thereby creating a region of gate metal 1330 between each all-around gate structure 1112.

[0053] The number of nanosheets 1111 and / or the all-around gate structure 1112 may vary. In some embodiments, there are 2 to 7 nanosheets 1111, or 2 to 5 nanosheets, or 3 to 4 nanosheets, or a range of 3 nanosheets.

[0054] Some implementations further include a non-I / O gate region 1110 ( Figure 12B ) or I / O gate region 1120 ( Figure 12C ) one or more of the optional gate-cut pillars 502.

[0055] In some implementations, such as Figure 12C As shown, electronic device 1100 includes an I / O gate region 1120 with a finFET 1122. In some embodiments, the finFET 1122 includes a contact 800 made of a first material 112. In some embodiments, the finFET 1122 of the I / O gate region 1120 has a truncated conical top portion.

[0056] In some implementations, the pFET region 1140 ( Figure 12E ) or nFET region 1150 ( Figure 12F One or more of them contain a first material 112 epitaxially grown as a pFET 320 and / or nFET 420. In the illustrated embodiment, the pFET region 1140 ( Figure 12E The second material 114, which is epitaxially grown, serves as the pFET 320, while the nFET region 1150... Figure 12F The first material 112 with epitaxial growth is used as nFET 420.

[0057] refer to Figure 12E and Figure 13 The first material 112 for epitaxial growth forming the pFET 320 has a length extending along the second direction 192. Figure 12E and Figure 13The illustration shows an electronic device viewed along a second direction 192 on a plane (XZ plane) formed by a first direction 191 and a third direction 193. A first epitaxially grown material 112 has a width W extending along the first direction 191 and a height H extending along the third direction 193. The width W of the epitaxially grown first material 112 forming the contact 800 varies along the height H. In some embodiments, the width of the epitaxially grown first material 112 has a plurality of spaced protrusions.

[0058] The semiconductor device of claim 14, wherein the epitaxially grown first material has a length, a width, and a height, and the width has a plurality of spaced protrusions 115. Each protrusion 115 is separated from adjacent protrusions 115 by an inner spacer 116 (also referred to as an inner spacer dielectric). In some embodiments, each spacer protrusion is separated from... Figure 12E The nanosheets 1111 of the all-around gate structure 1112 of the transistor shown on the right are aligned. In some embodiments, the inner spacers have a width of 1 to 10 nm, or 2 to 8 nm, or 3 to 7 nm, or 4 to 5 nm.

[0059] Some implementations further include one or more of the following: a non-I / O gate contact 1115 electrically connected to a non-I / O gate region 1110; an I / O gate contact 1125 electrically connected to an I / O gate region 1120; a source contact 1135 electrically connected to the source (one of pFET 320 or nFET 420) of a source-drain non-I / O region 1130; a drain contact 1135 electrically connected to the drain (one of pFET 320 or nFET 420) of a source-drain non-I / O region 1130; a pFET contact 1145 electrically connected to a pFET region 1140; and an nFET contact 1155 electrically connected to an nFET region 1150. In some implementations, the I / O device ( Figure 11E and Figure 11F The width of the transistor gate (shown on the left) is greater than that of the transistor gate. Figure 11E and Figure 11F The width of the I / O gate (shown on the right) is wide. A wide gate of an I / O device allows for the application of higher voltages and / or greater currents. In some implementations, the width of the I / O gate is 1.5 times, 2 times, 4 times, 7 times, or 10 times that of the non-I / O gate.

[0060] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic associated with an embodiment is included in at least one embodiment of the disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in different places throughout this specification do not necessarily refer to the same embodiment of the disclosure. Furthermore, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0061] Although the disclosure herein has been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, comprising the following steps: Multiple dummy gates are etched above multiple fins from the substrate surface to provide multiple trenches extending along a second direction, the multiple fins extending along a first direction and the second direction intersecting the first direction, to expose several portions of the multiple fins such that several portions of the fins on the substrate surface are covered by the dummy gates, while the remaining portions of the fins are exposed between the dummy gates, the fins comprising alternating first and second material layers. Remove the gate oxide exposed across the trench; The second material layer is etched through the trenches onto the plurality of fins, such that the first material layer and the openings alternate. The first material layer is epitaxially grown through the trench to merge the first material layer into a first material junction; and The contacts were repaired using an HCl back-etching process.

2. The method of claim 1, further comprising the following steps: Multiple fins on the surface of a patterned substrate.

3. The method of claim 1, further comprising the following steps: A gate oxide is formed on the surface of the substrate to cover the plurality of fins, and the trenches formed by etching the dummy gate expose several portions of the fins having the gate oxide above them.

4. The method of claim 1, further comprising the following steps: The plurality of virtual gates extending along the second direction are formed on the plurality of fins such that several portions of the fins are covered by the virtual gates, while the remaining portions of the fins are exposed between the virtual gates.

5. The method of claim 4, further comprising the following steps: The fins are etched to expose several portions between the virtual gates.

6. The method of claim 5, further comprising the following steps: An oxide layer is deposited on the exposed substrate surface between the virtual gates.

7. The method of claim 6, further comprising the following steps: An amorphous silicon layer is deposited on the substrate, which allows the top of the dummy gate to be exposed.

8. The method of claim 7, wherein the step of forming the amorphous silicon layer includes a cover deposition process followed by chemical-mechanical planarization to expose the top of the dummy gate.

9. The method of claim 1, wherein the first material layer comprises at least one group III-V material and the second material layer comprises at least one group III-V material, and the first material layer and the second material layer comprise different materials.

10. The method of claim 9, wherein the first material layer comprises silicon (Si) and the second material layer comprises silicon germanium (SiGe).

11. A semiconductor device comprising a non-I / O gate region, an I / O gate region, a source-drain non-I / O region, a pFET region, and an nFET region, wherein the non-I / O gate region comprises a gate-all-around structure, the I / O gate region comprises a finFET, wherein one or more of the pFET region or the nFET region comprises an epitaxially grown first material layer having a length, a width, and a height, the width having a plurality of spaced protrusions.

12. The semiconductor device of claim 11, wherein the spacer protrusions are aligned with the nanosheets of the all-around gate structure.

13. The semiconductor device of claim 12, wherein there are 2 to 7 nanosheets.

14. The semiconductor device of claim 13, further comprising a gate cleavage pillar in one or more of the non-I / O gate regions or the I / O gate regions.

15. The semiconductor device of claim 11, further comprising a non-I / O gate contact electrically connected to the non-I / O gate region, an I / O gate contact electrically connected to the I / O gate region, a source contact electrically connected to the source of the source-drain non-I / O region, a drain contact electrically connected to the drain of the source-drain non-I / O region, a pFET contact electrically connected to the pFET region, and an nFET contact electrically connected to the nFET region.

16. A semiconductor device, comprising: The non-I / O gate region has a surrounding gate structure and a non-I / O gate contact, wherein the surrounding gate structure includes a plurality of spacer nanosheets; I / O gate region, including finFET and I / O junction; The source-drain non-I / O region includes the source contact and the drain contact; The pFET region includes an epitaxially grown first material layer and a pFET junction. The epitaxially grown first material layer has a length, a width, and a height. The width has a plurality of spaced protrusions, which are aligned with the spacer nanosheets. and The nFET region includes the epitaxially grown second material layer and the nFET junction.

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