FPGA-based analog-to-digital converter testing system and method

Abstract

The application provides an FPGA-based analog-to-digital converter testing system and method, the testing system comprises a host computer, an FPGA control board card, a high-precision digital-to-analog converter source board card and an analog-to-digital converter testing board card, the FPGA control board card, the high-precision digital-to-analog converter source board card and the analog-to-digital converter testing board card involved in testing and acquisition are all based on a board card structure, support plug and play, do not need bulky testing equipment and instruments, reduce the volume of the testing system, do not need special high-precision instruments and equipment, and reduce the cost of the testing system; a continuous sampling analog signal is generated based on the high-precision digital-to-analog converter, the sampling data amount is small, the data amount processed by the host computer is reduced, the data splitting and merging operation, linear fitting and subtraction calculation are combined, the data calculation amount of the host computer is further reduced, the testing time is shortened, the linear degree index of the to-be-tested analog-to-digital converter is accurately measured, and the testing efficiency is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of circuit testing technology, and in particular to an FPGA-based analog-to-digital converter testing system and method. Background Technology

[0002] Analog-to-digital converter (ADC) testing, as an important branch of current integrated circuit testing, has seen its testing requirements reach new heights with the rapid development of integrated circuits. Foreign Σ-Δ and SAR structure ADCs can achieve resolutions of up to 32 bits, while domestic SAR structure ADCs can reach 20 bits, and Σ-Δ structure ADCs can reach 32 bits. Achieving such ultra-high precision ADC testing using traditional methods not only requires connection to high-precision signal source instruments and precision testing equipment, but also necessitates a very large amount of data sampling, resulting in high testing costs and low testing efficiency.

[0003] Traditional analog-to-digital converter (ADC) separate instrument testing platforms have two structures: either a high-precision signal source instrument + ADC under test (DUT) or an ADC under test + precision testing instrument. The high-precision signal source instrument + ADC under test structure uses a high-precision signal source instrument to output a continuous analog signal. The ADC samples and converts the data, which is then transmitted back to the host computer for direct processing. This approach can achieve the most realistic linearity and signal-to-noise ratio (SNR) indicators for the ADC. However, achieving linearity requires a considerable amount of data, significantly increasing testing time. In batch testing, this method is extremely inefficient, and high-precision signal source instruments are also relatively expensive. The ADC under test + precision testing instrument structure uses a general signal source to output sampled analog signals, and a precision testing instrument calibrates the signal source. This reduces the amount of sampled data while still achieving linearity. However, precision testing instruments are expensive, and achieving dynamic performance indicators still relies on the high-precision signal source instrument. The repeated communication of the calibration algorithm significantly increases testing time and reduces testing efficiency.

[0004] Therefore, there is an urgent need for a testing technology solution for analog-to-digital converters that is both efficient and cost-effective. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an FPGA-based analog-to-digital converter (ADC) testing technology solution to improve the testing efficiency of ADCs and reduce testing costs.

[0006] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0007] An FPGA-based analog-to-digital converter testing system includes:

[0008] Host computer;

[0009] An FPGA control board, including an FPGA chip, wherein the FPGA chip is connected to the host computer;

[0010] A high-precision digital-to-analog converter (DAC) source board, comprising a high-precision DAC connected to the FPGA chip; and

[0011] An analog-to-digital converter test board includes an analog-to-digital converter under test, which is connected to the FPGA chip and the high-precision digital-to-analog converter respectively.

[0012] The host computer sends test commands to the FPGA chip; the FPGA chip controls the high-precision digital-to-analog converter to generate multiple consecutive sampled analog signals; the FPGA chip controls the analog-to-digital converter under test to acquire the sampled analog signals and perform analog-to-digital conversion on the sampled analog signals to obtain digital codes; the FPGA chip receives the digital codes and uploads them to the host computer; the host computer processes the digital codes to obtain the linearity error of the analog-to-digital converter under test.

[0013] Optionally, the FPGA control board further includes a first circuit board, a USB chip, a first ribbon cable, and a second ribbon cable. The FPGA chip, the USB chip, the first ribbon cable, and the second ribbon cable are respectively disposed on the first circuit board. The USB chip, the first ribbon cable, and the second ribbon cable are respectively connected to the FPGA chip, and the USB chip has a USB interface.

[0014] Optionally, the FPGA chip is connected to the host computer via the USB chip and an external USB data cable.

[0015] Optionally, the high-precision digital-to-analog converter source board further includes a second circuit board, a first SMA connector, and a first ribbon cable slot. The high-precision digital-to-analog converter, the first SMA connector, and the first ribbon cable slot are respectively disposed on the second circuit board, and the first SMA connector and the first ribbon cable slot are respectively connected to the high-precision digital-to-analog converter.

[0016] Optionally, the analog-to-digital converter test board further includes a third circuit board, a second SMA connector, and a second ribbon cable slot. The analog-to-digital converter under test, the second SMA connector, and the second ribbon cable slot are respectively disposed on the third circuit board, and the second SMA connector and the second ribbon cable slot are respectively connected to the analog-to-digital converter under test.

[0017] Optionally, the high-precision digital-to-analog converter is connected to the FPGA chip through the first ribbon cable slot and the first ribbon cable; the analog-to-digital converter under test is connected to the FPGA chip through the second ribbon cable slot and the second ribbon cable; and the analog-to-digital converter under test is connected to the high-precision digital-to-analog converter through the second SMA connector, an external coaxial cable, and the first SMA connector.

[0018] A test method for an FPGA-based analog-to-digital converter includes the following steps:

[0019] Provide an FPGA-based analog-to-digital converter test system as described in any of the above claims;

[0020] The FPGA chip controls the high-precision digital-to-analog converter to generate multiple consecutive sampled analog signals.

[0021] The FPGA chip controls the analog-to-digital converter under test to acquire the sampled analog signal and perform analog-to-digital conversion on the sampled analog signal to obtain a digital code.

[0022] The FPGA chip receives the digital code and uploads it to the host computer.

[0023] The host computer processes the digital code to obtain the linearity error of the analog-to-digital converter under test.

[0024] Optionally, according to the input voltage range of the analog-to-digital converter under test, each of the sampled analog signals is set continuously and at equal intervals in a preset order, wherein the preset order includes either increasing or decreasing.

[0025] Optionally, the step of processing the digital code through the host computer to obtain the linearity error of the analog-to-digital converter under test includes:

[0026] Arrange the digital codes in the preset order, and perform splitting and merging operations on each digital code to obtain N digital code sets, where N is an integer greater than or equal to 6;

[0027] The average value of the digital codes in each digital code set is obtained by averaging all the digital codes in each digital code set.

[0028] A linear fit is performed on the mean values ​​of the digital codes in the N digital code sets to obtain the fitted curve;

[0029] Based on the fitted curve, the fitted value of the mean value of the digital code for each digital code set is calculated;

[0030] For each set of digital codes, the difference between the mean of the digital codes and the fitted value of the mean of the digital codes is calculated to obtain the corresponding linearity. The maximum value among the N linearities is then identified as the linearity error.

[0031] Optionally, the step of arranging the digit codes according to the preset order and splitting and merging the digit codes to obtain N digit code sets includes:

[0032] Each of the M×N digital codes is split and merged, with M as the splitting and merging step. The M adjacent digital codes are divided into a digital code set, resulting in N digital code sets, where M is an integer greater than or equal to 8.

[0033] As described above, the FPGA-based analog-to-digital converter testing system and method provided by the present invention have at least the following beneficial effects:

[0034] Based on the overall structural design of "host computer + FPGA control board + high-precision digital-to-analog converter source board + analog-to-digital converter test board", the FPGA control board, high-precision digital-to-analog converter source board, and analog-to-digital converter test board involved in the test acquisition are all circuit board-based structures, supporting plug-and-play functionality and eliminating the need for connecting bulky test equipment, resulting in a relatively small test system size. Furthermore, the FPGA control board, high-precision digital-to-analog converter source board, and analog-to-digital converter test board are all built with integrated circuits, requiring no high-precision instruments, thus reducing the cost of the test system. In addition, the high-precision digital-to-analog converter generates continuous sampled analog signals, resulting in less sampled data compared to high-precision signal source instruments, less data processing by the host computer, and shorter test time. This effectively improves test efficiency while accurately measuring the performance indicators of the analog-to-digital converter under test. Attached Figure Description

[0035] Figure 1 The diagram shown is a structural block diagram of the FPGA-based analog-to-digital converter test system of this invention.

[0036] Figure 2 The diagram shows the steps of the FPGA-based analog-to-digital converter testing method in this invention.

[0037] Figure 3 The diagram shows the data splitting, merging, and linear fitting operations performed by the host computer in this invention. Detailed Implementation

[0038] As mentioned in the background section, regarding traditional analog-to-digital converter (ADC) testing devices, the inventors discovered that the structure of a high-precision signal source instrument + ADC under test requires a high-precision signal source instrument to output a continuous analog signal. The data sampled and converted by the ADC is then transmitted back to the host computer for direct processing. While this can achieve the most realistic linearity and signal-to-noise ratio indicators of the ADC, it requires a considerable amount of data, significantly increasing the testing time. For example, for a SAR-structured ADC with a resolution of 24 bits and a sampling rate of 1 MSPS, the sampled data volume reaches 2... 24 *32, which is approximately 9 minutes of testing time, while Σ-Δ structure analog-to-digital converters generally have lower sampling rates and higher resolutions. In batch testing, such testing efficiency is extremely low, and high-precision signal source instruments are quite expensive. For example, a Fluke high-precision signal source costs at least hundreds of thousands and sometimes as much as one or two million. The structure of the analog-to-digital converter under test + precision test instrument requires using a general signal source to output sampled analog signals and using precision test instruments to calibrate the signal source. This can reduce the amount of sampling data while still achieving linearity indicators. However, precision test instruments are expensive. For example, an Agilent 8.5-digit high-precision multimeter costs about 100,000. Moreover, achieving dynamic performance indicators still requires high-precision signal source instruments. The repeated communication of the calibration algorithm greatly increases the testing time and reduces testing efficiency.

[0039] Based on this, the present invention proposes an FPGA-based analog-to-digital converter (ADC) testing technology solution: combining data acquisition from an FPGA control board, a high-precision ADC source board, and an ADC test board with data processing from a host computer. The data acquisition device is a board-based structure that supports plug-and-play, reducing the size of the testing device and enhancing its flexibility, while also lowering testing and production costs. The high-precision ADC generates continuous sampled analog signals, which, compared to high-precision signal source instruments, reduces the amount of sampled data, correspondingly reducing the amount of data processed by the host computer, thereby shortening testing time and improving testing efficiency.

[0040] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] Please see Figures 1 to 3It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0042] like Figure 1 As shown, the present invention provides an FPGA-based analog-to-digital converter testing system, which includes:

[0043] Host computer;

[0044] FPGA control board, including FPGA chip, which is connected to host computer;

[0045] A high-precision digital-to-analog converter (DAC) source board, including the high-precision DAC itself and its connection to an FPGA chip; and...

[0046] The analog-to-digital converter test board includes an analog-to-digital converter under test (ADC), which is connected to an FPGA chip and a high-precision digital-to-analog converter (DAC).

[0047] The process involves the host computer sending test commands to the FPGA chip; the FPGA chip controlling the high-precision digital-to-analog converter to generate multiple consecutive sampled analog signals V; the FPGA chip controlling the analog-to-digital converter under test to acquire the sampled analog signals V and perform analog-to-digital conversion on the sampled analog signals V to obtain a digital code D; the FPGA chip receiving the digital code D and uploading it to the host computer; and the host computer processing the digital code D to obtain the linearity error of the analog-to-digital converter under test.

[0048] In detail, such as Figure 1 As shown, the host computer mainly plays two roles: sending test commands to the FPGA chip and controlling the test acquisition of the analog-to-digital converter under test through the FPGA chip; and receiving the digital code D uploaded by the analog-to-digital converter under test through the FPGA chip, processing the digital code D, and obtaining the linearity error of the analog-to-digital converter under test.

[0049] In detail, such as Figure 1As shown, the FPGA control board, high-precision digital-to-analog converter source board, and analog-to-digital converter test board used for data acquisition during testing are all board-based structures that support plug-and-play functionality.

[0050] In an optional embodiment of the present invention, in addition to the FPGA chip, the FPGA control board also includes a first circuit board, a USB chip, a first ribbon cable, and a second ribbon cable. The FPGA chip, USB chip, first ribbon cable, and second ribbon cable are respectively disposed on the first circuit board. The USB chip, first ribbon cable, and second ribbon cable are respectively connected to the FPGA chip, and the USB chip has a USB interface. The FPGA chip is connected to a host computer via the USB chip and an external USB data cable.

[0051] In an optional embodiment of the present invention, in addition to the high-precision digital-to-analog converter, the high-precision digital-to-analog converter source board also includes a second circuit board, a first SMA connector and a first ribbon cable slot. The high-precision digital-to-analog converter, the first SMA connector and the first ribbon cable slot are respectively disposed on the second circuit board, and the first SMA connector and the first ribbon cable slot are respectively connected to the high-precision digital-to-analog converter.

[0052] In an optional embodiment of the present invention, in addition to the analog-to-digital converter under test (ADC), the ADC test board also includes a third circuit board, a second SMA connector, and a second ribbon cable slot. The ADC under test, the second SMA connector, and the second ribbon cable slot are respectively disposed on the third circuit board, and the second SMA connector and the second ribbon cable slot are respectively connected to the ADC under test.

[0053] Specifically, the high-precision digital-to-analog converter is connected to the FPGA chip through the first cable slot and the first cable; the analog-to-digital converter under test is connected to the FPGA chip through the second cable slot and the second cable; and the analog-to-digital converter under test is connected to the high-precision digital-to-analog converter through the second SMA connector, the external coaxial cable, and the first SMA connector.

[0054] It should be noted that in the analog-to-digital converter test board, the analog-to-digital converter under test is detachably mounted on the third circuit board. It can be continuously removed and replaced to meet the testing requirements of multiple different analog-to-digital converters under test, which will not be elaborated further here.

[0055] In detail, such as Figure 1As shown, the FPGA control board, high-precision digital-to-analog converter (DAC) source board, and DAC test board are all circuit board-based structures, supporting plug-and-play functionality and eliminating the need for bulky test equipment, resulting in a relatively small test system size. The FPGA control board, high-precision DAC source board, and DAC test board are all built with integrated circuits, requiring no high-precision instruments, thus reducing the system's cost. Generating continuous sampled analog signals using a high-precision DAC reduces the amount of sampled data compared to high-precision signal source instruments, consequently reducing the amount of data processed by the host computer, thereby shortening test time and improving test efficiency. Furthermore, to further shorten test time, the host computer's data processing algorithms and workflows can be improved.

[0056] More specifically, the FPGA chip, high-precision digital-to-analog converter, and analog-to-digital converter under test involved in data acquisition during testing must meet certain test matching requirements.

[0057] In an optional embodiment of the present invention, a 24-bit Σ-Δ type analog-to-digital converter under test (ADC) has an analog power supply voltage of ±1.65V, receives a true bipolar (±2.5V) analog input signal, and has a maximum data output rate of 16kSPS. Its typical INL (Integral Nonlinearity) value is ±7ppm, indicating INL ≥ 17.2Bit. A high-precision ADC with a resolution of 20 bits is selected, with an INL ≤ ±1LSB, indicating INL ≥ 20Bit, and a typical output voltage noise value of 1.1μV P-P. Therefore, this 20-bit ADC fully meets the linearity error test requirements. Meanwhile, the clock signal of the 24-bit Σ-Δ analog-to-digital converter under test is 8.192MHz, while the maximum clock signal of the 20-bit digital-to-analog converter is 50MHz. A certain FPGA chip is selected, whose maximum I / O port output frequency is 710MHz, and the clock jitter time_jitter ≤ 3ps. Based on the relationship between signal-to-noise ratio, analog frequency, and clock jitter, the SNR (signal-to-noise ratio) can be obtained as ≥ 14.4dB. Therefore, the FPGA chip also meets the test requirements.

[0058] At the same time, such as Figure 2 As shown, corresponding to the above-mentioned FPGA-based analog-to-digital converter test system, the present invention also provides an FPGA-based analog-to-digital converter test method, which includes the following steps:

[0059] S1. Provide the above-mentioned FPGA-based analog-to-digital converter test system;

[0060] S2. Using an FPGA chip, a high-precision digital-to-analog converter is controlled to generate multiple consecutive sampled analog signals V;

[0061] S3. Using the FPGA chip, control the analog-to-digital converter under test to acquire the sampled analog signal V and perform analog-to-digital conversion on the sampled analog signal V to obtain the digital code D;

[0062] S4. Receive digital code D through the FPGA chip and upload it to the host computer;

[0063] S5. The digital code D is processed by the host computer to obtain the linearity error of the analog-to-digital converter under test.

[0064] Specifically, in step S2, according to the input voltage range of the analog-to-digital converter under test, each sampled analog signal V is set continuously and at equal intervals in a preset order. The preset order includes either increasing or decreasing. The more sampled analog signals V there are (the smaller the step size of the sampled analog signals V), i.e., the more data points are tested, the more accurate the test will be.

[0065] In an optional embodiment of the present invention, a high-precision digital-to-analog converter (DAC) is driven by an FPGA chip, so that the 20-bit high-precision DAC outputs 65,536 sampled analog signals V, each with a different voltage value, within the input voltage range of the DAC under test, in a preset order and at equal intervals. Multiple experiments have shown that when the number of sampled analog signals V exceeds 65,536, the linearity index calculated subsequently changes very little. In order to balance the relationship between test time and data volume, the high-precision DAC is selected to output 65,536 data points, with a voltage output range of -2.49 to 2.49V, covering 99.6% of the input voltage range of the DAC under test.

[0066] In detail, step S5, which processes the digital code D through a host computer to obtain the linearity error of the analog-to-digital converter under test, further includes:

[0067] S51. Arrange the digit codes in a preset order, and perform splitting and merging operations on each digit code to obtain N digit code sets, where N is an integer greater than or equal to 6.

[0068] S52. Calculate the average value of all digit codes in each digit code set to obtain the average value of the digit codes in each digit code set.

[0069] S53. Perform linear fitting on the mean values ​​of the digital codes in N digital code sets to obtain the fitting curve;

[0070] S54. Based on the fitted curve, calculate the fitted value of the mean value of the digital code for each digital code set;

[0071] S55. For each set of digital codes, calculate the difference between the mean of the digital codes and the fitted value of the mean of the digital codes to obtain the corresponding linearity. Find the maximum value among the N linearities, which is the linearity error.

[0072] More specifically, step S51, which involves arranging the individual numeric codes in a preset order and then splitting and merging them to obtain N numeric code sets, is as follows: Figure 3 As shown, it further includes:

[0073] Arrange M×N digit codes in a preset order, and perform splitting and merging operations on each M×N digit code. With M as the splitting and merging step, divide M adjacent digit codes into a digit code set, resulting in N digit code sets, where M is an integer greater than or equal to 8.

[0074] In an optional embodiment of the present invention, an FPGA chip drives the analog-to-digital converter under test (ADC) to acquire 65,536 sampled analog signals V output by a high-precision digital-to-analog converter (DAC) and perform analog-to-digital conversion to obtain 65,536 digital codes D. These 65,536 digital codes are then divided and merged to obtain N digital code sets, i.e., as follows: Figure 2 As shown in Bin[1], Bin[2], ..., Bin[N-1] and Bin[N]), multiple experiments have shown that the linearity index is stable only when the number of digital codes D contained in a digital code set is at least 8. Therefore, in the embodiment of the present invention, the value of M is 8 and the value of N is 8192, that is, there are 8192 digital code sets.

[0075] More specifically, in step S52, the average value of all digital codes D in each digital code set is calculated to obtain the average value of the digital codes for each digital code set. In an optional embodiment of the present invention, for 8192 digital code sets, the average value of the digital codes for each digital code set is calculated to obtain Bin. AVG [1] Bin AVG [2]、…、Bin AVG

[8191] and Bin AVG

[8192] ).

[0076] More specifically, in step S53, a linear fit is performed on the average digital code values ​​of the N digital code sets to obtain a fitted curve, which is a linear function. In an optional embodiment of the invention, the average digital code value Bin of 8192 digital code sets is used. AVG [1] Bin AVG [2]、…、Bin AVG

[8191] and Bin AVG

[8192] ) Perform linear fitting to obtain the fitted curve F(n)=k*n+b, as shown Figure 3As shown, F(n) is the fitted value of the mean of the digit code, n is the sorting of the digit code set, and k and b are constants.

[0077] More specifically, in step S54, the fitted value of the digital code mean for each digital code set is calculated based on the fitted curve. In an optional embodiment of the present invention, based on the fitted curve F(n)=k*n+b, the fitted value of the digital code mean for each of the 8192 digital code sets is calculated, namely F[1], F[2], ..., F

[8191] and F

[8192] ).

[0078] More specifically, in step S55, for each set of digital codes, the difference between the mean of the digital codes and the fitted value of the mean of the digital codes is calculated to obtain the corresponding linearity. The maximum value among the N linearities is then identified as the linearity error. In an optional embodiment of the present invention, for 8192 sets of digital codes, the difference between the mean of the digital codes and the fitted value of the mean of the digital codes is calculated to obtain the corresponding linearity INL, i.e., INL[1] = Bin AVG [1]-F[1],INL[2]=Bin AVG [2]-F[2],…,INL

[8191] =Bin AVG

[8191] -F

[8191] , INL

[8192] =Bin AVG

[8192] -F

[8192] , form the corresponding linearity curve, and find the maximum value INLmax among the 8192 linearities, which is the linearity error.

[0079] In an optional embodiment of the present invention, for a 24-bit Σ-Δ structure analog-to-digital converter (ADC) under test, an FPGA chip drives a high-precision digital-to-analog converter (DAC) to output 65,536 sampled analog signals V. The ADC under test converts these signals to obtain 65,536 digital codes D. The host computer splits and merges these 65,536 digital codes D into groups of eight, obtaining a set of 8,192 digital codes. The linearity error is then calculated based on linear fitting after averaging and subtraction. The overall test time is less than 5 seconds. In contrast, the test time for a structure using a high-precision signal source instrument + ADC under test is approximately 8,192 times that of the embodiment of the present invention; the test time for a structure using an ADC under test + precision testing instrument is approximately 60 seconds. Therefore, the technical solution of the present invention significantly shortens the test time and improves the test efficiency.

[0080] In summary, the FPGA-based analog-to-digital converter (ADC) testing system and method of this invention are based on an overall structural design of "host computer + FPGA control board + high-precision digital-to-analog converter (DAC) source board + ADC test board". The FPGA control board, high-precision DAC source board, and ADC test board involved in the test acquisition are all circuit board-based structures, supporting plug-and-play functionality and eliminating the need for bulky testing equipment, thus reducing the overall size of the testing system. Furthermore, the FPGA control board, high-precision DAC source board, and ADC test board are all built with integrated circuits, eliminating the need for high-precision instruments and reducing the cost of the testing system. In addition, the high-precision DAC generates continuous sampled analog signals, resulting in less sampled data compared to high-precision signal source instruments, reducing the amount of data processed by the host computer. Combined with data splitting and merging operations, linear fitting, and subtraction calculations, the computational load on the host computer is further reduced, shortening the testing time. This method effectively improves testing efficiency while accurately measuring the linearity of the ADC under test, and can be widely applied to the testing of various ADCs under test.

[0081] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An FPGA-based analog-to-digital converter testing system, characterized in that, include: Host computer; An FPGA control board, including an FPGA chip, wherein the FPGA chip is connected to the host computer; A high-precision digital-to-analog converter source board includes a high-precision digital-to-analog converter, which is connected to the FPGA chip; as well as An analog-to-digital converter test board includes an analog-to-digital converter under test, which is connected to the FPGA chip and the high-precision digital-to-analog converter respectively. The host computer sends test commands to the FPGA chip; the FPGA chip controls the high-precision digital-to-analog converter to generate multiple consecutive sampled analog signals; the FPGA chip controls the analog-to-digital converter under test to acquire the sampled analog signals and perform analog-to-digital conversion on the sampled analog signals to obtain digital codes; the FPGA chip receives the digital codes and uploads them to the host computer; the host computer processes the digital codes to obtain the linearity error of the analog-to-digital converter under test. The host computer processes the digital code to obtain the linearity error of the analog-to-digital converter under test, including: Arrange the digital codes in a preset order, and then split and merge the digital codes to obtain N digital code sets, where N is an integer greater than or equal to 6. The average value of the digital codes in each digital code set is obtained by averaging all the digital codes in each digital code set. A linear fit is performed on the mean values ​​of the digital codes in the N digital code sets to obtain the fitted curve; Based on the fitted curve, the fitted value of the mean value of the digital code for each digital code set is calculated; For each set of digital codes, the difference between the mean of the digital codes and the fitted value of the mean of the digital codes is calculated to obtain the corresponding linearity. The maximum value among the N linearities is then found to obtain the linearity error.

2. The FPGA-based analog-to-digital converter testing system according to claim 1, characterized in that, The FPGA control board also includes a first circuit board, a USB chip, a first ribbon cable, and a second ribbon cable. The FPGA chip, the USB chip, the first ribbon cable, and the second ribbon cable are respectively disposed on the first circuit board. The USB chip, the first ribbon cable, and the second ribbon cable are respectively connected to the FPGA chip, and the USB chip leads out a USB interface.

3. The FPGA-based analog-to-digital converter testing system according to claim 2, characterized in that, The FPGA chip is connected to the host computer via the USB chip and an external USB data cable.

4. The FPGA-based analog-to-digital converter testing system according to claim 2, characterized in that, The high-precision digital-to-analog converter source board also includes a second circuit board, a first SMA connector, and a first ribbon cable slot. The high-precision digital-to-analog converter, the first SMA connector, and the first ribbon cable slot are respectively disposed on the second circuit board, and the first SMA connector and the first ribbon cable slot are respectively connected to the high-precision digital-to-analog converter.

5. The FPGA-based analog-to-digital converter testing system according to claim 4, characterized in that, The analog-to-digital converter test board also includes a third circuit board, a second SMA connector, and a second ribbon cable slot. The analog-to-digital converter under test, the second SMA connector, and the second ribbon cable slot are respectively disposed on the third circuit board, and the second SMA connector and the second ribbon cable slot are respectively connected to the analog-to-digital converter under test.

6. The FPGA-based analog-to-digital converter testing system according to claim 5, characterized in that, The high-precision digital-to-analog converter is connected to the FPGA chip via the first cable slot and the first cable; the analog-to-digital converter under test is connected to the FPGA chip via the second cable slot and the second cable; and the analog-to-digital converter under test is connected to the high-precision digital-to-analog converter via the second SMA connector, an external coaxial cable, and the first SMA connector.

7. A test method for an analog-to-digital converter based on FPGA, characterized in that, Including the following steps: Provides an FPGA-based analog-to-digital converter test system according to any one of claims 1-6; The FPGA chip controls the high-precision digital-to-analog converter to generate multiple consecutive sampled analog signals. The FPGA chip controls the analog-to-digital converter under test to acquire the sampled analog signal and perform analog-to-digital conversion on the sampled analog signal to obtain a digital code. The FPGA chip receives the digital code and uploads it to the host computer. The host computer processes the digital code to obtain the linearity error of the analog-to-digital converter under test.

8. The FPGA-based analog-to-digital converter testing method according to claim 7, characterized in that, According to the input voltage range of the analog-to-digital converter under test, each of the sampled analog signals is set continuously and at equal intervals in a preset order, the preset order including either increasing or decreasing.

9. The FPGA-based analog-to-digital converter testing method according to claim 8, characterized in that, The step of processing the digital code through the host computer to obtain the linearity error of the analog-to-digital converter under test includes: Arrange the digital codes in the preset order, and perform splitting and merging operations on each digital code to obtain N digital code sets, where N is an integer greater than or equal to 6; The average value of the digital codes in each digital code set is obtained by averaging all the digital codes in each digital code set. A linear fit is performed on the mean values ​​of the digital codes in the N digital code sets to obtain the fitted curve; Based on the fitted curve, the fitted value of the mean value of the digital code for each digital code set is calculated; For each set of digital codes, the difference between the mean of the digital codes and the fitted value of the mean of the digital codes is calculated to obtain the corresponding linearity. The maximum value among the N linearities is then identified as the linearity error.

10. The FPGA-based analog-to-digital converter testing method according to claim 9, characterized in that, The step of arranging the digit codes according to the preset order and splitting and merging the digit codes to obtain N digit code sets includes: Each of the M×N digital codes is split and merged, with M as the splitting and merging step. The M adjacent digital codes are divided into a digital code set, resulting in N digital code sets, where M is an integer greater than or equal to 8.

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