Constant current source calibration circuit, constant current source drive circuit, drive chip, electronic equipment

Abstract

The present application relates to a constant current source calibration circuit, a constant current source driving circuit, a driving chip, and an electronic device, including: a calibration circuit unit, a resistor connected to the calibration circuit unit, and a selector or switch connected to both ends of the resistor; the calibration circuit unit is used to adjust the voltage drop across the resistor; the selector or switch is used to select one end of the resistor as an input terminal connected to a first bias voltage VD, and the other end as an output terminal connected to a constant current source output channel. The voltage drop across the resistor is adjusted, VD is a fixed value, and the voltage connected to the constant current source output channel is adjusted accordingly. Applying the constant current source calibration circuit to a constant current source driving circuit, a driving chip, and an electronic device can improve the constant current output accuracy thereof, and eliminate the problem of low output current accuracy caused by the threshold voltage deviation caused by the parameter mismatch of the MOS tube device itself and the different MOS tube drain voltages between different constant current source output channels caused by the input offset voltage of the operational amplifier.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a constant current source calibration circuit, a constant current source driving circuit, a driving chip, and an electronic device. Background Art

[0002] A constant current source circuit is a circuit that provides or outputs a constant current based on a reference current. Figure 1 It is a constant current source driving circuit in the prior art. Figure 1 As shown, it is composed of a reference current generating circuit, a bias generating circuit and a constant current source output channel. Among them, there are N constant current source output channels. After analysis, it can be known that the output current size of each constant current source output channel is related to the resistance R_EXT outside the chip, specifically, it is inversely proportional to the size of R_EXT. Therefore, in the prior art, the output current IOUT can be adjusted by adjusting the chip external resistance R_EXT.

[0003] However, the output current of the constant current source output channel is a proportional mirror image of the drain-source current of NM1, that is, IOUT is proportional to I1, and the proportionality coefficient is determined by the mirror ratio of the current mirror formed by the MOS tube NM_C0 and the MOS tube NM1.

[0004] In practice, due to the influence of factors such as process differences, there is a problem of poor consistency in the output channels of the constant current source, which is specifically manifested in that the actual output current is inconsistent with the expected current.

[0005] The above problems have become issues that need to be solved urgently. Summary of the invention

[0006] In view of this, the purpose of this application is to provide a constant current source calibration circuit, a constant current source driving circuit, a driving chip, and an electronic device to improve the problem of poor consistency between constant current source output channels caused by factors such as process differences.

[0007] The reasons for poor inter-channel consistency are described in detail below:

[0008] Specifically, on the one hand, the parameter mismatch of the MOS device itself will lead to threshold voltage deviation; on the other hand, the drain voltage (Vd) of the MOS tubes between different channels will be different due to the input offset voltage of the operational amplifier.

[0009] In this application, the Vd voltage of the MOS tube in the channel (for example, Figure 1 The drain voltage of NM_C0 in the circuit is calibrated to solve the above problem.

[0010] Specifically, the first aspect of the present application provides a constant current source calibration circuit, comprising:

[0011] A calibration circuit unit, a resistor connected to the calibration circuit unit, and a selector or a switch connected to both ends of the resistor;

[0012] Wherein, the calibration circuit unit is used to adjust the voltage drop across the resistor;

[0013] The selector or switch is used to select one end of the resistor as an input end connected to the first bias voltage VD, and the other end as an output end connected to the constant current source output channel.

[0014] In this solution, the selector or switch is used to select or switch the connection mode of the two terminals of the resistor. By selecting the first end or the second end of the resistor to be connected to the constant current source output channel (specifically, Figure 1 The drain voltage of NM_C0 can be adjusted in the positive or negative direction by changing the connection mode of the two terminals of the resistor (the first terminal is connected to VD, and the second terminal is connected to the drain of the MOS in the constant current source output channel, that is, the drain of NM_C0; or the second terminal is connected to VD, and the first terminal is connected to the drain of NM_C0), so as to adjust the drain voltage of NM_C0, and finally adjust the output current.

[0015] See also Figure 1-2 , the first bias voltage VD (NM1 drain voltage) is input to the non-inverting terminal of the amplifier AMP_C, and the inverting terminal of the amplifier AMP_C is connected to the drain of NM_C0. In theory, the inverting terminal voltage of the amplifier AMP_C (i.e., the drain voltage of NM_C0) is equal to the first bias voltage VD. In practice, the input offset voltage of the amplifier AMP_C will cause the inverting terminal voltage of the amplifier AMP_C to be not equal to VD. According to the scheme of the present application, a constant current source calibration circuit is set between the inverting terminal of AMP_C and the drain of NM_C0. Here, it is assumed that the voltage of the inverting terminal of the amplifier AMP_C is VD. Then the constant current source calibration circuit receives VD, calibrates it, and outputs a third bias voltage VDO to the drain of NM_C0, then VDO = VD ± IR (where I is the current flowing through the resistor R, R is the resistance value of the resistor, ± IR (or positive adjustment or reverse adjustment) is caused by the first end of the resistor R being connected to the first bias voltage VD and the other end being connected to the constant current source output channel or adopting the opposite connection method, or selecting which terminal of the resistor is connected to the drain of NM_C0). Wherein, VD is a fixed value, therefore, the desired VDO can be obtained by adjusting IR (the part adjusted by the constant current source calibration circuit), regardless of whether there is an error in VD here. When the final output current is equal to the standard accuracy (expected current), the adjustment is stopped, and the voltage VDO is the final adjusted voltage, thereby achieving the precision adjustment of the output current.

[0016] Furthermore, the calibration circuit unit includes:

[0017] A voltage source, and a voltage drop regulating circuit connected to the voltage source;

[0018] The voltage drop adjustment circuit is connected to the resistor and is used to adjust the voltage drop across the resistor;

[0019] The voltage drop regulation circuit includes a control module and a plurality of voltage-dividing resistors, which are connected in series in sequence and connected to the voltage source. The control module selects the output node of the voltage-dividing resistor based on a calibration control signal to generate a target voltage divider connected at both ends of the resistor.

[0020] Furthermore, the calibration circuit unit includes:

[0021] Calibration circuit A and / or calibration circuit B, a bias circuit connected to a current source for generating a bias current;

[0022] The bias circuit is connected to the calibration circuit A and / or calibration circuit B;

[0023] The calibration circuit A and / or calibration circuit B are connected to the resistor;

[0024] The currents of the calibration circuit A and the calibration circuit B are synchronously adjusted to synchronously adjust the current flowing through the resistor, or the current of the calibration circuit A is adjusted to adjust the current flowing through the resistor, or the current of the calibration circuit B is adjusted to adjust the current flowing through the resistor.

[0025] The calibration circuit unit is used to adjust the voltage drop of the resistor. It can be understood that through the setting of the calibration circuit A and / or the calibration circuit B, the current flowing through the resistor is actually adjusted here. Since the current changes, the voltage drop across the resistor changes.

[0026] Furthermore, the calibration circuit A and the calibration circuit B each include M groups of MOS tube components; each group of MOS tube components in the calibration circuit A and each group of MOS tube components in the calibration circuit B respectively constitute a mirror output channel A and a mirror output channel B with the bias circuit; each group of mirror output channels A and / or each group of mirror output channels B are provided with a controlled switch, and the current flowing through the resistor is adjusted by switching the controlled switch; wherein the resistor is connected to the M groups of mirror output channels A and / or the M groups of mirror output channels B.

[0027] It can be understood that in this solution, the resistor is fixed, and the voltage drop across the resistor is changed by adjusting the current flowing through the resistor, thereby adjusting the drain voltage of NM_C0.

[0028] Furthermore, the output currents of the M groups of mirror output channels A and the M groups of mirror output channels B increase or decrease in sequence in proportion.

[0029] Furthermore, the mirror ratio of the M groups of MOS tube components to the bias circuit increases exponentially by 2. Wherein, M is the number of groups of MOS tube components in the calibration circuit A and / or the calibration circuit B.

[0030] The calibration circuit unit provided in the present application essentially adjusts the current flowing through the resistor R to adjust the drain voltage of NM_C0 in the output channel.

[0031] A second aspect of the present application provides a constant current source driving circuit, comprising:

[0032] A bias generating circuit for receiving a reference current, a reference current generating circuit for generating the reference current, a constant current source output channel connected to the bias generating circuit, and a constant current source calibration circuit as described in the first aspect;

[0033] The constant current source calibration circuit calibrates the first bias voltage VD generated by the bias generation circuit to obtain a third bias voltage VDO and outputs it to the constant current source output channel;

[0034] The constant current source output channel outputs a constant current based on the third bias voltage VDO and the second bias voltage VGI generated by the bias generating circuit.

[0035] Furthermore, the reference current generating circuit includes an external resistor, and the reference current can be adjusted by adjusting the resistance value of the external resistor.

[0036] Furthermore, the constant current source output channel includes:

[0037] A first MOS transistor, X groups of second MOS transistors, and a first operational amplifier; wherein X>=1 and X is an integer;

[0038] Wherein, the first MOS transistor is used as an output switch of the constant current source output channel; the gate of the first MOS transistor is connected to the output end of the first operational amplifier; the opening and closing of the constant current source output channel is controlled by controlling the output of the first operational amplifier;

[0039] The inverting terminal of the first operational amplifier is connected to the constant current source calibration circuit, and the non-inverting terminal is connected to the first bias voltage VD;

[0040] The drain of the second MOS tube is connected to the constant current source calibration circuit, and the gate is connected to the second bias voltage VGI.

[0041] Furthermore, it also includes a current control circuit including X output terminals and at least one input terminal; the X output terminals are connected to the X groups of second MOS transistors in a one-to-one correspondence; the second bias voltage VGI is input to the input terminal of the current control circuit;

[0042] When the control signal of the corresponding output terminal is valid, the corresponding output terminal outputs the second bias voltage VGI to the gate of the corresponding second MOS transistor.

[0043] Furthermore, it also includes a current calibration control circuit, a selector, a third MOS tube, and a trimming circuit;

[0044] The input end of the selector is connected to the output end of the first operational amplifier, and the selector inputs the output signal of the first operational amplifier into the gate of the first MOS tube or the gate of the third MOS tube;

[0045] The drain of the third MOS tube is connected to the trimming circuit and the current calibration control circuit; the trimming circuit outputs the trimming current to the drain of the third MOS tube; the source of the third MOS tube is connected to the drain of the second MOS tube;

[0046] The current calibration control circuit is used to control the constant current source calibration circuit to perform calibration;

[0047] In the calibration state, the selector outputs the output signal of the first operational amplifier to the gate of the third MOS tube, and the current calibration control circuit controls the constant current source calibration circuit to adjust the current according to the drain voltage of the third MOS tube;

[0048] In the output state, the selector outputs the output signal of the first operational amplifier to the gate of the first MOS tube.

[0049] Further, the current calibration control circuit is used to control the constant current source calibration circuit to perform calibration, and its control signal includes M+1 groups of control instructions;

[0050] Among them, M groups of control instructions are used to control the current regulation of the constant current source calibration circuit; when controlling the current size of the constant current source calibration circuit (for example, the current size flowing through the resistor R), the current is adjusted step by step from small to large or from large to small. Another group of control instructions is used to control the selector or switch to select one end of the resistor to connect to the constant current source output channel. For example, when it is 1, the first terminal is selected to connect to the constant current source output channel, and the second terminal is connected to VD; when it is 0, the first terminal is selected to connect to VD, and the second terminal is selected to connect to the constant current source output channel.

[0051] A third aspect of the present application provides a driver chip, comprising the constant current source driver circuit as described in the second aspect of the present application.

[0052] A fourth aspect of the present application provides an electronic device, comprising the driver chip as described in the third aspect of the present application.

[0053] The advantages of this application are:

[0054] The present application overcomes the problem of poor channel consistency caused by the threshold voltage deviation caused by the parameter mismatch of the MOS tube device itself, and the different drain voltages of the MOS tubes between different channels caused by the input offset voltage of the operational amplifier. Specifically, based on the expected current, the output channel MOS tube drain voltage is adjusted to make the constant current source output channel output an accurate constant current, that is, the current actually output by the constant current source output channel is the expected current or is within a certain accuracy range of the expected current. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a constant current source driving circuit in the prior art;

[0056] Figure 2 A schematic diagram of a constant current source calibration circuit according to an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a calibration circuit unit according to an embodiment of the present application;

[0058] Figure 4 A specific implementation circuit diagram of a calibration circuit unit;

[0059] Figure 5 A schematic diagram of a calibration circuit unit according to another embodiment of the present application;

[0060] Figure 6 for Figure 5 A circuit diagram of a certain implementation of a medium voltage drop regulation circuit;

[0061] Figure 7 This is a schematic diagram of a constant current source driving circuit in one embodiment of the present application;

[0062] Figure 8 for Figure 7 Specific circuit examples;

[0063] Fig. 9 This is a schematic diagram of a constant current source driving circuit according to another embodiment of the present application;

[0064] Fig.10 for Fig. 9 Specific circuit examples;

[0065] Fig.11 This is the current control circuit and the X-group second MOS tube example circuit of the embodiment of the present application;

[0066] Fig.12 The current calibration control circuit of the embodiment of the present application;

[0067] Fig.13 for Fig.12Schematic diagram of the output waveform. DETAILED DESCRIPTION

[0068] The present application is further described in detail below through specific embodiments and in conjunction with the accompanying drawings. It should be noted that the embodiments recorded or described are only part of the embodiments of the present application, not all of the embodiments. The protection scope of the present application is not limited thereto.

[0069] like Figure 1 As shown, a constant current source driving circuit in the prior art is shown, which is composed of a reference current generating circuit, a bias generating circuit and a constant current source output channel.

[0070] The reference current generating circuit includes Bandgap (bandgap reference), amplifier AMP1 and MOS tube NM0. Bandgap provides reference potential VREF1 for the in-phase input terminal of amplifier AMP1, the output terminal of amplifier AMP1 is connected to the gate of NM0, and the inverting input terminal of amplifier AMP1 is connected to the source of NM0. Amplifier AMP1 clamps the source potential of NM0 to the reference potential. An external resistor R_EXT is set outside the chip. It can be seen that the current I0 flowing between the drain and source of NM0 = VREF1 / R_EXT.

[0071] The bias generation circuit includes PM0, PM1, amplifier AMP_2, amplifier AMP_3, NMOS tube NM1, etc. Among them, PM0 and PM1 form a current mirror. Here, it is assumed that I(PM1) / I(PM0) is K0. Among them, I(PM1) and I(PM0) refer to the current flowing between the drain and source of PM1 and the current flowing between the drain and source of PM0 respectively. I(PM1), that is, I1, is equal to K0*I0. VREF2 is input to the inverting input terminal of AMP_3, the non-inverting input terminal is connected to the drain of NM1, and the output terminal is connected to the gate of NM1. AMP_3 clamps the drain voltage of NM1 to VREF2.

[0072] The constant current output channel includes an amplifier AMP_C, whose non-inverting input terminal is connected to the drain of NM1, and whose inverting input terminal is connected to the source of NM_C1. Ideally, the amplifier AMP_C clamps the drain potential of NM_C0 to the non-inverting terminal potential of AMP_C, that is, the first bias voltage VD. At this time, the drain potential of NM_C0 is the same as the drain potential of NM1, the source potential of NM_C0 is the same as the source potential of NM1, the gate of NM_C0 is connected to the gate of NM1 through BUF1, and the gate potential of NM_C0 is the same as the gate potential of NM1.

[0073] At this time, the output current IOUT of the constant current source output channel is a proportional mirror image of the current flowing through the drain and source of NM1, and the size of IOUT is: I1*K1, that is, K1*K0*VREF1 / R_EXT. Among them, K1 is the mirror ratio. K1*K0 is usually fixed, so the output current IOUT of the constant current source channel can be adjusted by adjusting the resistance value of R_EXT outside the chip. It should be noted that here, Figure 1 In the figure, it is assumed that the gain of each amplifier is infinite. However, in practice, due to factors such as process differences, there is a problem of poor consistency in the output channels of the constant current source, resulting in the channel output current being inconsistent with the expected output current.

[0074] Specifically, see Figure 1 , the voltage of the drain of the MOS tube NM1 in the bias generating circuit is the first bias voltage VD of the present application, and the drain of NM1 is connected to the non-inverting input terminal of the amplifier AMP_C. In theory, the amplifier AMP3 clamps the voltage of its non-inverting terminal to VREF2, that is, the first bias voltage VD is equal to the input voltage VREF2 of the inverting input terminal of AMP3. The sources of NM1 and NM_C0 are grounded, and the gates are connected through BUF1. The drain voltage of NM1 is VD. Only when the voltage of the drain of NM_C0 is equal to the drain voltage VD of NM1, can the channel output current IOUT be kept in mirror proportion with the current between the drain and source of NM1, thereby ensuring the consistency of the accuracy of the output channel, that is, the output current of the output channel is consistent with the expected current. In practice, the drain voltage of NM_C0 will not be equal to the first bias voltage VD due to the input offset voltage of the amplifier AMP_C; in addition, NM_C0 and NM1 constitute a current mirror, and there are differences in the preparation process and parameters of the two. Even if the voltages of the two are the same, they still output different currents. Therefore, the actual IOUT is not consistent with the expected current. NM1 and NM_C0 are determined by the device itself and cannot adjust the current. Therefore, in this application, a method of adjusting or calibrating the drain voltage of NM_C0 is proposed to solve the problem of how to adjust the output current.

[0075] See also Figure 2 On the one hand, an embodiment provided by the present invention provides a constant current source calibration circuit, which includes: a calibration circuit unit, a resistor R connected to the calibration circuit unit, and a selector or switch connected to both ends of the resistor R; wherein the calibration circuit unit is used to adjust the voltage drop across the resistor R; the selector or switch is used to select one end of the resistor R as an input end connected to a first bias voltage VD, and the other end as an output end connected to a constant current source output channel.

[0076] Specifically, the calibration circuit unit receives a calibration control signal, performs calibration based on the calibration control signal, and realizes the adjustment of the voltage drop across the resistor R (the first end and the second end are represented by T1 and T2, respectively). In other words, the constant current source calibration circuit actually adjusts the voltage drop across the resistor R through the calibration circuit unit, thereby realizing the calibration of the connected VD voltage, and outputs it as VDO to the constant current source output channel after calibration. The T1 and T2 ends of the resistor R are respectively connected to the selector or switch, wherein the T1 terminal leads to the terminal VD1 and the terminal VDO2 after the selector or switch; the T2 terminal leads to the terminal VD2 and the terminal VDO1 after the selector or switch. It should be noted that in this application, VD1, VD2, VDO1, and VDO2 belong to internal logic terminals, and there are only two leads, VD and VDO, in the hardware circuit. It should also be noted that VDO (third bias voltage) represents the voltage connected to the constant current source output channel, which can be the drain of the MOS tube connected to the output channel, for example, the drain of NM_C0; VD is the first bias voltage. The first bias voltage VD can be generated by a bias generation circuit. For example, Figure 1 The voltage at the drain of the MOS tube NM1 in the bias generating circuit is the first bias voltage VD. The function of the selector or switch is to select the connection mode of the two ends of the resistor R, specifically, to select the T1 end of the resistor R to be connected to the first bias voltage VD (such as connected to the bias generating circuit and connected to the drain of the MOS tube NM1 ( Figure 8 ), connected to the inverting terminal of the amplifier AMP_C), T2 terminal connected to the constant current source output channel (such as NM_C0 drain), or, select the T2 terminal of the resistor R to connect to the first bias voltage VD, and T1 terminal to connect to the constant current source output channel. In other words, the above includes two situations (excluding the situation where the same terminal is both input and output), that is, situation 1: select VD1 led by the T1 terminal to connect to the first bias voltage VD, and VDO1 led by the T2 terminal to connect to the constant current source output channel; situation 2: select VDO2 led by the T1 terminal to connect to the constant current source output channel, and VD2 led by the T2 terminal to connect to the first bias voltage VD. Whether to select situation 1 or situation 2 is achieved through a selector or a switch. Figure 2 In the embodiment, the selector or switch receives a selection signal (SEL) and makes a selection based on the signal (one of the control instructions in the calibration control signal referred to later). <m:0>The M group of control instructions in the control command) and the SEL signal received by the selector or switch are all controlled based on the target current. This application will be specifically introduced below and will not be described in detail here.

[0077] The following is a detailed analysis of the above two situations (assuming that the current is Figure 1 , 2 In the direction of the arrow, and Figure 2 The resistance of the resistor is R, and the current flowing through it is I).

[0078] In case 1, VD1 is connected to the first bias voltage VD, VDO1 is connected to the constant current source output channel, then VDO = VD-IR;

[0079] In case 2, VD2 is connected to the first bias voltage VD, VDO2 is connected to the constant current source output channel, and VDO=VD+IR.

[0080] VD is a fixed voltage generated by the bias generating circuit. When VD does not change, VDO is related to IR. The third bias voltage VDO can be adjusted by adjusting IR. The selection of the selector or switch determines whether VDO is increased or decreased based on VD, and the value of IR determines the magnitude of the increase or decrease. It can be understood that IR can be changed by adjusting the resistance value of resistor R or adjusting the current to achieve Figure 2 Regulation of the voltage drop across the resistor R.

[0081] Optionally, the calibration circuit unit includes:

[0082] Calibration circuit A and / or calibration circuit B, a bias circuit connected to a current source for generating a bias current;

[0083] The bias circuit is connected to the calibration circuit A and / or calibration circuit B;

[0084] The calibration circuit A and / or calibration circuit B are connected to the resistor;

[0085] The currents of the calibration circuit A and the calibration circuit B are synchronously adjusted to synchronously adjust the current flowing through the resistor, or the current of the calibration circuit A is adjusted to adjust the current flowing through the resistor, or the current of the calibration circuit B is adjusted to adjust the current flowing through the resistor.

[0086] Specifically, Figure 3 A schematic diagram of a calibration circuit unit provided for an embodiment. In this case, the calibration circuit unit includes a calibration circuit A and a calibration circuit B. The bias circuit is connected to both of them at the same time. In addition, the resistor R is located (connected to) between the calibration circuit A and the calibration circuit B, that is, the calibration circuit A, the resistor R, and the calibration circuit B form a current channel, and the current in the channel can be changed by synchronously adjusting the current magnitudes of the calibration circuit A and the calibration circuit B, that is, adjusting the current flowing through the resistor R. When the resistance value of the resistor R remains unchanged, the voltage drop across the resistor R changes, that is, the aforementioned IR changes. At this time, the voltage VDO connected to the constant current source output channel (specifically, the drain voltage of the MOS (such as NM_C0) in the output channel) will be changed, thereby further realizing the current calibration.

[0087] Different from Figure 3 In the embodiment of the present application, the solution of the present application may also include only the calibration circuit A or only the calibration circuit B. For example, when only the calibration circuit A is included, the bias circuit is connected to the calibration circuit A, and the T1 end of the resistor R is connected to the calibration circuit A (or, the resistor R is connected in the path where the calibration circuit A is located). Specifically, the resistor R is connected in the mirror output channel A formed by the calibration circuit A, so that the current flowing through the resistor R is regulated by adjusting the current (output current) of the calibration circuit A, or the voltage drop across the resistor R is regulated.

[0088] Optionally, the calibration circuit A and the calibration circuit B each include M groups of MOS tube components; each group of MOS tube components in the calibration circuit A and each group of MOS tube components in the calibration circuit B respectively form a mirror output channel A and a mirror output channel B with the bias circuit; the resistor R is connected to the M groups of the mirror output channels A and / or the M groups of the mirror output channels B; each group of the mirror output channels A and each group of the mirror output channels B are connected to a controlled switch (for example, Figure 4 S <0> ~S <m-1>), and are connected to the resistor via corresponding controlled switches, and the magnitude of the current flowing through the resistor R is adjusted by switching the controlled switches. That is, each group of mirror output channels A and / or each group of mirror output channels B are connected to the resistor via controlled switches. In the present application, the current regulation of the calibration circuit A and the calibration circuit B, that is, the regulation of the current flowing through the resistor R, can be achieved by the number of controlled switches in the calibration circuit A and the calibration circuit B (controlling the on and off of the controlled switches).

[0089] Figure 4 A specific implementation circuit diagram of a calibration circuit unit provided in an embodiment of the present application, which may correspond to Figure 3 . refer to Figure 3 , Figure 4 The calibration circuit A includes M groups of MOS tube components. Each group of MOS tube components and the bias circuit form a mirror output channel A. The calibration circuit A forms a total of M groups of mirror output channels A. At the same time, each group of mirror output channels A is connected to a controlled switch (S in the figure). <0> ~S <m-1>); Similarly, the calibration circuit B also includes M groups of MOS tube components, each group of MOS tube components and the bias circuit form a mirror output channel B, and the calibration circuit B forms M groups of mirror output channels B. At the same time, each group of mirror output channels B is connected to a controlled switch (S in the figure). <0> ~S <m-1>). The resistor R is located (connected) between the M groups of mirror output channels A and the M groups of mirror output channels B. It can be understood that the current flowing through the resistor R can be adjusted by controlling the on and off of each controlled switch (i.e., by switching the controlled switch). For example, assuming that the controlled switches S in the calibration circuit A and the calibration circuit B are <0> If the controlled switch S is closed, the MOS tube components in the two branches will form a current mirror with the bias circuit, and the mirror output channel A, mirror output channel B and the channel where the resistor R is located will generate current, and a voltage drop will occur on the resistor R. <0> ~S <m-1>If the current on the resistor R is different, the voltage drop on the resistor R will change. Based on this principle, VDO can be adjusted. It should be noted that in this embodiment, the controlled switches with the same sign in the calibration circuit A and the calibration circuit B (such as S in the calibration circuit A) <0> , S in calibration circuit B <0> ), should be opened (closed) or closed (opened) synchronously to ensure that the current magnitudes of calibration circuit A and calibration circuit B are synchronized. For example, S in calibration circuit A <0> , S <1> , S <2> Close (open), and at the same time, calibrate S in circuit B <0> , S <1> , S <2> Also closed (open). At this time, G is used to represent the mirror ratio of the corresponding MOS tube component, then the current flowing through the resistor R is equal to G*ICAL, G=K / T*VS<2:0>. Among them, K / T is a constant, that is, a fixed amount, and VS<2:0> is the number of MOS tubes in the corresponding MOS tube component at this time. Therefore, it can be understood that what actually needs to be adjusted to adjust the current flowing through the resistor R is the value of VS<(M-1):0>, that is, the number of MOS tubes in the corresponding MOS tube component that are electrically connected to the resistor R (the branch switch is closed). Optionally, MOS tubes with the same parameters are used in each MOS tube component to ensure that the mirror ratio is accurate and uniform. In addition, M also represents the accuracy of the adjustment. The larger its value, the higher the range and resolution of the adjustment.

[0090] Optionally, the mirror ratios of the M groups of MOS tube components are configured in an exponentially increasing manner of 2, which are 2 0 , 2 1 ……2 M-2 , 2 M-1 Specifically, the mirror ratio of the M groups of MOS tube components and the bias circuit is configured in an exponentially increasing manner of 2, which is 2 0 , 2 1 ……2 M-2 , 2 M-1 That is to say, each group of MOS tube components and the bias circuit form a current mirror, and the ratio of the output current of the current mirror to the input current is 2 0 , 2 1 ……2 M-2 , 2 M-1 The mirror ratio of the M groups of MOS tube components in the calibration circuit A and the calibration circuit B can be set in the above manner regardless of whether the scheme includes both the calibration circuit A and the calibration circuit B or only one of the calibration circuit A or the calibration circuit B. Then, when adjusting, the output current of the M groups of mirror output channels A and the output current of the M groups of mirror output channels B increase or decrease in proportion. In other words, adjustment in a jump manner is not allowed, but must be made in 2 0 , 2 1 ……2 M-2 , 2 M-1 Adjust in a forward or reverse order to determine whether the output accuracy requirements are met.

[0091] See also Figure 5 , the calibration circuit unit includes a voltage source and a voltage drop adjustment circuit. The voltage drop adjustment circuit receives a calibration control signal, and based on this, adjusts the voltage drop on the resistor R. Specifically, the calibration circuit unit (specifically, the voltage drop adjustment circuit in the calibration circuit unit) is connected to one end of the resistor R, wherein the voltage source, the voltage drop adjustment circuit, and the resistor R form a current channel. In one embodiment, the voltage drop adjustment circuit can be a circuit with adjustable resistance, such as a sliding rheostat, which can adjust the equivalent resistance in the above-mentioned current channel (note that it is not to adjust the resistance value of the aforementioned resistor R, in fact, the resistance value of the resistor R is fixed). The above-mentioned current channel can be understood as a closed loop, so that the resistor R has a current formed. Since the voltage source is a fixed voltage source, that is, the voltage value of its output is fixed, according to Ohm's law, I=U / R (here, R has nothing to do with the aforementioned resistor R, but is used as a symbol to represent the resistance value to express Ohm's law), U is fixed, and I is inversely proportional to R. Therefore, when the resistance value of the effective resistor in the channel is changed, the current in the channel will change synchronously. Since the resistance value of resistor R remains unchanged, the voltage drop across it will change. From another perspective, it can also be considered that the effective resistance in the channel changes. Since the resistance value of resistor R remains unchanged, its voltage division changes.

[0092] The voltage drop adjustment circuit can be implemented by controlling the connection of other resistors, for example, increasing or decreasing other resistors; or setting the resistance adjustment circuit to a resistor with adjustable resistance value such as a sliding rheostat.

[0093] Figure 6 exist Figure 5 Based on the above, a more specific embodiment of a calibration circuit unit is provided, wherein the calibration circuit unit comprises:

[0094] A voltage source, and a voltage drop regulating circuit connected to the voltage source;

[0095] The voltage drop adjustment circuit is connected to the resistor and is used to adjust the voltage drop across the resistor;

[0096] The voltage drop regulation circuit includes a control module and a plurality of voltage-dividing resistors, which are connected in series in sequence and connected to the voltage source. The control module selects the output node of the voltage-dividing resistor based on a calibration control signal to generate a target voltage divider connected at both ends of the resistor.

[0097] Please continue to see Figure 5-Figure 6 The voltage drop regulation circuit includes a plurality of resistors connected in series (which may be called voltage dividing resistors, represented by R0 to R(M-1) in the figure); the voltage dividing resistors R0-R(M-1) are connected in series in sequence, and the control module receives the calibration control signal S <m-1:0>, and based on this, the corresponding output node of the voltage-dividing resistor is selected to be connected to the resistor R, changing the voltage drop on the resistor R. Optionally, the control module is a multiplexer MX0, and the number of its input terminals corresponds to the number of voltage-dividing resistors connected in series or the number of output nodes of the voltage-dividing resistors. For example, if the voltage-dividing resistors are selected to be M, then the selector MX0 is an M-way selector.

[0098] In the present application, the voltage source and current source in the calibration circuit unit may be the voltage generated by the bias generating circuit of the driving chip or the current generated by the reference current generating module, or may be independent.

[0099] The second aspect of the present application provides a constant current source driving circuit, such as Figure 7-8 , the constant current source driving circuit comprises: a bias generating circuit receiving a reference current, a reference current generating circuit generating the reference current, a constant current source output channel connected to the bias generating circuit, and a constant current source calibration circuit as in any of the aforementioned embodiments;

[0100] The constant current source calibration circuit calibrates the first bias voltage VD generated by the bias generation circuit to obtain a third bias voltage VDO and outputs it to the constant current source output channel;

[0101] The constant current source output channel outputs a constant current based on the third bias voltage VDO and the second bias voltage VGI generated by the bias generating circuit.

[0102] Next, Figure 7 It should be noted that unless otherwise specified in this application, the bias generating circuit, the reference current generating circuit, the constant current source output channel ( Figure 1 , 8 , 10 all include these three modules) are all circuits that can be known and implemented by any technology in this field, rather than referring to a specific circuit.

[0103] refer to Figure 1 , 8 The reference current generating circuit structure of the two is the same, both include Bandgap (bandgap reference voltage source), NMOS tube and operational amplifier. Among them, Bandgap generates reference voltage VREF1 and inputs it to the non-inverting terminal of the operational amplifier. The inverting terminal of the operational amplifier is connected to the source of the NMOS tube NM0, and the operational amplifier clamps the source potential to VREF1. The source of the NMOS tube is grounded through the resistor R_EXT outside the chip. The current I0 flowing between the drain and source of NM0 = VREF1 / R_EXT, where R_EXT represents the resistance value of the resistor R_EXT. And Fig.10 Zhongyu Figure 1 , 8 There is a slight difference in the reference current Iref. The output end of the reference current generation and adjustment circuit is connected to the current range selection circuit to output current to it. The current range selection circuit outputs a high-precision reference current Iref to the bias generation circuit according to the control signal C[0:L].

[0104] The bias generating circuit generates a first bias voltage VD and a second bias voltage VGI. The constant current source output channel can output a constant current based on VD and VGI. Specifically, the bias generating circuit receives the above current I0 and is also connected to a reference voltage VREF2. Figure 1 , 8 , there is only a slight difference in the bias generation circuit, namely Figure 8 The reference potential selection circuit is used to generate VREF2. Figure 1 , 8 In the bias generation circuit, the PM0 drain-source current is I0, and PM0 and PM1 form a current mirror, that is, the PM1 drain-source current I1 is the mirror image of the PM0 drain-source current I0. The operational amplifier AMP3 clamps the NM1 drain voltage to VREF2, and the terminal potential derived from the drain is the first bias voltage VD. Figure 1 In theory, AMP_C can clamp the drain voltage of NM_C0 to the first bias voltage VD, that is, VREF2. In addition to being connected to the gate of NM1, the output end of the operational amplifier AMP3 is also connected to a gain BUF1, and the other end of the gain BUF1 is connected to the gate of NM_C0. Fig.10 The bias generation circuit in Figure 1 , 8 The bias generating circuit in the embodiment of the present invention is composed of Bandgap, operational amplifier, NMOS tube and gain BUF1. Similarly, Bandgap generates a reference voltage (VREF). AMP3 clamps the drain potential of NM1 to VREF, thereby providing a first bias voltage VD. VGI is also output by gain BUF1 connected to the output end of AMP3. It should be noted that the bias generating circuit is actually a conventional circuit in this field. Therefore, in addition to the several forms introduced above, there are many other forms in practice.

[0105] The constant current source output channel is used to output constant current IOUT. Figure 1 , 8 , 10 both give the specific circuit of the constant current source output channel. It is mainly composed of an operational amplifier and a MOS tube to form a mirror output channel. Figure 1 It is a constant current source output channel in the prior art, and the inverting end of the operational amplifier AMP_C is connected to the drain of the MOS tube NM_C0. Figure 8 , 10 In the embodiment, the inverting end of the operational amplifier AMP_C is connected to the drain of the MOS tube NM_C0 after passing through the constant current source calibration circuit, and the constant current source calibration circuit adjusts the drain voltage of NM_C0, thereby finally adjusting the output current of the constant current source output channel. That is, the constant current source calibration circuit receives the first bias voltage VD, calibrates it and outputs the third bias voltage VDO to the constant current source output channel. Here, the constant current source calibration circuit receives the first bias voltage VD by connecting to the inverting end of the amplifier. In the present application, one end of the constant current source calibration circuit can also be directly connected to the bias generation circuit to receive the first bias voltage VD, for example, connected to the drain of NM1.

[0106] Figure 1 , 8 The constant current source drive circuit shown generally has the following problems:

[0107] 1. The constant current source driver chips on the market have a wide output range. The maximum value of most constant current source driver chips is more than ten times the minimum value of the output. If, as mentioned above, an external resistor is used to adjust the current, the changes in I0, I1 and IOUT are all more than 10 times. At the same time, according to the above analysis, I0 = VREF1 / R_EXT, I1 = K0*I0, it can be seen that the smaller the external resistor, the larger I0 will be, and the larger I1 will be. The higher the current is bound to lead to higher power consumption of the constant current source driver chip.

[0108] 2. Satisfy the accuracy requirement of the minimum output current by increasing the area of ​​the MOS tube, for example, by increasing the length and width of the MOS tube; in particular, increasing the length is the most effective; by increasing the width-to-length ratio W / L of the MOS tube to meet the maximum output current, increasing the length while increasing W / L (the width will inevitably increase), which will inevitably lead to the problem of large chip area. In addition, since the current accuracy is proportional to the arithmetic square root of the device area, and due to the production process, when the area increases to a certain value, the current accuracy cannot be continuously improved, resulting in the difficulty of improving the current accuracy.

[0109] 3. When the output current is very small, the |VGS| (absolute value of VGS) of each MOS tube is also very small, which will cause the performance of the current mirror to deteriorate, thereby affecting the accuracy of the output constant current source, which is specifically manifested as a deterioration in accuracy.

[0110] For the above problem, an embodiment of the present application provides a solution, which does not use an external resistor for adjusting the reference current I0. Fig. 9 As shown, the constant current source driving circuit also includes: a bias generating circuit, a reference current generating circuit, a constant current source output channel, and a current control circuit connected in series between the constant current source output channel and the bias generating circuit; the constant current source output channel is one or more. Among them, the current control circuit can adjust the current size of the constant current source output channel, and it includes at least one input terminal and X (an integer greater than or equal to 1, whose value is determined by the constant current source output channel, for example, determined by the number of groups of the second MOS tubes of the constant current source output channel in the following text) output terminals (VG0[0:X-1]); the X output terminals are connected to the X groups of second MOS tubes in a one-to-one correspondence; the second bias voltage VGI is input to the input terminal of the current control circuit; when the control signal of the corresponding output terminal (for example Fig.11 When S[0], ..., S[X-1]) are valid, the corresponding output terminal outputs the second bias voltage VGI to the gate of the corresponding second MOS transistor (the second MOS transistor will be introduced later). In this way, the mirror ratio of the constant current source output channel can be adjusted by the control signal of the corresponding output terminal.

[0111] Optionally, the constant current source output channel includes:

[0112] A first operational amplifier, a first MOS transistor NM_C1, and X groups of second MOS transistors; wherein X>=1 and X is an integer;

[0113] Wherein, the first MOS transistor NM_C1 serves as an output switch of the constant current source output channel; the gate of the first MOS transistor NM_C1 is connected to the output end of the first operational amplifier; the opening and closing of the constant current source output channel is controlled by controlling the output of the first operational amplifier AMP_C;

[0114] The inverting terminal of the first operational amplifier is connected to the constant current source calibration circuit, and the non-inverting terminal is connected to the first bias voltage VD (i.e., connected to the port of the bias generating circuit outputting VD, such as the drain of NM1);

[0115] The drain of the second MOS tube is connected to the constant current source calibration circuit and is used to receive the third bias voltage VDO output by the constant current source calibration circuit, and the gate is connected to the second bias voltage VGI.

[0116] It should be noted that, in addition to being an output switch, the first MOS transistor NM_C1 is also used to eliminate static electricity. Fig.10 , the first amplifier AMP_C receives a control signal OE[0:N] and operates based on the control signal.

[0117] X groups of second MOS transistors are the second MOS transistors in the previous embodiment. As in the previous embodiment, the second bias voltage VGI is input to the input end of the current control circuit; when the control signal (e.g. Fig.11 When the control signal of a certain output terminal is valid, the corresponding output terminal outputs the second bias voltage VGI to the corresponding second MOS tube. It can be understood that in the current control circuit, the X output terminals correspond to the X groups of second MOS tubes here one by one. When the control signal of a certain output terminal is valid, the output terminal outputs the second bias voltage VGI to the gate of the second MOS tube connected or corresponding thereto. In this way, the on-off of the second MOS tube can be controlled, thereby adjusting the mirror ratio of the constant current source output channel. In other words, the output current IOUT of the constant current source output channel can be adjusted.

[0118] NM_C1 is used as an output switch. Since the output of AMP_C is connected to the gate (control terminal) of NM_C1, the opening and closing of the constant current source output channel is controlled by controlling the output of the first operational amplifier AMP_C. When NM_C1 is turned on, the constant current source output channel can output a constant current when other conditions are met; when NM_C1 is turned off or disconnected, the constant current source output channel no longer outputs a constant current. The inverting terminal of the first operational amplifier AMP_C is connected to one end of the constant current source calibration circuit, and the in-phase terminal is connected to the first bias voltage VD; the other end of the constant current source calibration circuit is connected to the drain of the second MOS tube and the source of the first MOS tube NM_C1. In other words, the constant current source calibration circuit calibrates or adjusts the inverting terminal voltage of AMP_C and outputs it as VDO to the drain of the second MOS tube and the source of the first MOS tube NM_C1.

[0119] Combination Fig.11 , which provides a specific solution of the above-mentioned X groups of second MOS transistors and current control circuits in an embodiment. Among them, the X groups of second MOS transistors ( Fig.11 NMOS transistors, NM_C0 to NM_C0X-1) are connected in parallel. Specifically, the drains of the second MOS transistors are connected, the sources are grounded, and the gates are connected to the current control circuit. Fig.10 , the drains of the second MOS tubes are connected in common and then connected in common with the source of NM_C1 and the constant current source calibration circuit (when there is no constant current source calibration circuit, the common point potential is the first bias voltage VD, and when there is a constant current source calibration circuit, the common point potential is the voltage after the first bias voltage is corrected, or the third bias voltage VDO). The gates of the second MOS tubes are connected to the current control circuit. Specifically, the current control circuit includes X selectors or switches (MX0 to MXX-1), an input terminal for receiving the second bias voltage VGI, and X output terminals (VGO[0] to VGO[X-1]). Fig.11 It can be seen that the X output terminals are the output terminals of the X selectors or switches. The X output terminals are connected to the gates of the NMOS tubes (NM_C0-NM_CX-1) in the X groups of MOS tubes in a one-to-one correspondence, that is, one output terminal (or the output terminal of a selector or switch) is connected to one group of the X groups of MOS tubes. It can be understood that each selector or switch can determine whether the corresponding output terminal is turned on or off (select the output GND potential or VGI, GND corresponds to off, VGI corresponds to on). Among them, when the output terminal is turned on, the corresponding selector or switch can output the second bias voltage VGI to the gate of the second MOS tube connected thereto, so as to control the corresponding second MOS tube to turn on and output current. Based on this, the number of the second MOS tubes turned on can be controlled by the selector or switch, so as to control or adjust the mirror ratio (here the mirror ratio refers to the mirror ratio between the output current and the reference current) to achieve the adjustment of the output current. It can be seen that the solution provided in this embodiment can achieve the adjustment of the output current without adjusting the resistance value of the resistor outside the chip.

[0120] In a possible implementation, a regulation scheme for a constant current source calibration circuit is also provided. This scheme can enable the current source calibration circuit to achieve automatic / precise regulation. Figure 8 , 10 The constant current source calibration circuit also includes a current calibration control circuit, a selector, a third MOS tube, and a trimming circuit;

[0121] The input end of the selector is connected to the output end of the first operational amplifier, and the selector inputs the output signal of the first operational amplifier into the gate of the first MOS tube or the gate of the third MOS tube;

[0122] The drain of the third MOS tube is connected to the trimming circuit and the current calibration control circuit; the trimming circuit outputs the trimming current to the drain of the third MOS tube; the source of the third MOS tube is connected to the drain of the second MOS tube NM_C0;

[0123] The current calibration control circuit is used to control the constant current source calibration circuit to perform calibration;

[0124] In the calibration state, the selector outputs the output signal of the first operational amplifier to the gate of the third MOS tube, and the current calibration control circuit controls the constant current source calibration circuit to adjust the current according to the drain voltage of the third MOS tube;

[0125] In the output state, the selector outputs the output signal of the first operational amplifier to the gate of the first MOS tube.

[0126] In this solution, the input end of the selector Mux2-1 is connected to the output end of AMP_C, which can selectively output the output signal of AMP_C to the gate of NM_C or the gate of NM_C1. In other words, the output signal of AMP_C is input to the gate of NM_C or the gate of NM_C1 in a two-or-one manner through the selector (referring to selecting one from the gate of NM_C and the gate of NM_C1 to receive the output signal of AMP_C).

[0127] This solution includes two states: calibration state and output state. When the selector connects the output signal of AMP_C to the gate of NM_C, calibration can be performed; when the selector connects the output signal of AMP_C to the gate of NM_C1 instead of the gate of NM_C, normal current output can be performed.

[0128] Specifically, in the calibration state, the selector MUX2_1 outputs the output signal of the first operational amplifier AMP_C to the gate of the third MOS transistor NM_C, and the current calibration control circuit controls the constant current source calibration circuit to adjust the current according to the drain voltage of the third MOS transistor NM_C;

[0129] In the output state, the selector outputs the output signal of the first operational amplifier AMP_C to the gate of the first MOS transistor AMP_C1. At this time, the constant current source output channel can be opened normally, and the output current is used to power external devices.

[0130] As can be seen from the above, the constant current source calibration circuit adjusts the voltage drop across the resistor R by means of a calibration control signal. In this embodiment, the automatic adjustment method is emphasized, but in fact, the calibration control signal can also be manually controlled.

[0131] See also Figure 4 , Figure 5-6 , which changes the current or resistance to achieve the change or adjustment of the voltage drop, and the way to change the current or resistance is by connecting to different nodes. That is, all calibration methods are achieved by controlling the nodes. The current calibration control circuit provided in this embodiment has universal adaptability. Figure 8 , 10 As shown, the current calibration control circuit outputs the calibration control signal, using S <m:0>It can be understood that the calibration control signal actually consists of M+1 groups. Among the M+1 groups of signals, one group is used to control the selector or switch to determine which end of the resistor is connected to the constant current source output channel and which end is connected to the first bias voltage VD (for example, connected to the inverting end of AMP_C), and the remaining M groups (such as, Figure 4 , Figure 6 Medium S <m-1:0>) is to control the constant current source calibration circuit to adjust the current, for example, to control the on and off of the controlled switches connected to the M groups of MOS tube components in the calibration circuit unit, thereby ultimately controlling the current flowing through the resistor R ( Figure 4 ); or, control Figure 6 The selection of selector MX0 in determines the voltage drop across the resistor R.

[0132] by Figure 4 For example, calibration circuit A and calibration circuit B both include M groups of MOS tubes, and each group of MOS tubes is connected in series with a controlled switch. <0> -S <m-1>is a calibration control signal, which is used to control the state (on, off) of each controlled switch. <m:0>The signals can be divided into two types according to their functions, one of which (for example, using VS <m>Indicates) used to control selectors or switches, the remaining M group S <0> -S <m-1>Used to control the controlled switches in calibration circuit A and calibration circuit B. Among them, VS <m>The control selector or switch actually selects which end of the resistor R (the two ends are T1 and T2 respectively) is connected to the constant current source output channel (i.e., the drain of the second MOS tube) and which end is connected to the first bias voltage VD. In addition, the M controlled switches of the calibration circuit A and the calibration circuit B are controlled by the M groups (S <m-1:0>) is controlled to achieve closing / closing, thereby controlling the mirror ratio of the mirror output formed by the calibration circuit A and / or the calibration circuit B and the bias circuit to adjust the current flowing through the resistor R or the voltage drop across the resistor R. Similarly, when only the calibration circuit A or the calibration circuit B is included, it can be understood that the method of adjusting the current or voltage drop of the resistor R is substantially the same as the aforementioned Figure 4 same.

[0133] Similarly, Figure 6 For example, the selector MX0 receives the M group of signals S in the M+1 group of calibration control signals. <m-1:0>, according to S <m-1:0>Select the corresponding voltage divider node and connect it to resistor R. Another set of calibration control signals is VS <m>Indicates that its function is the same as the above Figure 4 The same is true in that they are both used to control the selector or switch, that is, to select which end of the resistor R (the two ends are T1 and T2 respectively) is connected to the drain of the second MOS tube.

[0134] In one implementation, a specific current calibration control circuit is provided, such as Fig.12 , taking M=4 as an example for explanation.

[0135] See also Figure 8 , 10 In the calibration state, the selector MUX2_1 outputs the output signal of the first operational amplifier AMP_C to the gate of the third MOS tube NM_C, and the drain of the third MOS tube NM_C is connected to the current calibration control circuit. The current calibration control circuit controls the constant current source calibration circuit to adjust the current according to the drain voltage (V_FLAG) of the third MOS tube NM_C. The trimming circuit generates a trimming current (IREF), which is connected to the drain of the third MOS tube and outputs IREF to the drain of the third MOS tube. IREF is a high-precision target current, which is actually a reference current that is trimmed to the set current accuracy (which can be understood as the aforementioned expected current. During calibration, if the output current of the constant current source output channel is consistent with the reference current, it is considered that the calibration of the constant current source output channel is completed. When the constant current source output channel enters the output state later, its output will not have deviation). In the calibration state, the third MOS tube NM_C is turned on, and the current of the drain of the third MOS tube NM_C (drain-source current) is equal to the current of the constant current source output channel (recorded as IOUT). Under ideal conditions (i.e., when the consistency is good), the channel output current IOUT[0:N] is equal to IREF. Among them, IOUT[0:N] represents the current of the N+1 constant current source output channels.

[0136] However, in reality, the output current IOUT[0:N] of each channel will deviate from IREF because of various non-ideal factors that may cause current deviations between channels and chips. For these reasons, it is necessary to perform current calibration on each channel in turn (channel-by-channel current calibration).

[0137] When calibrating a channel, the output of the first operational amplifier AMP_C is connected to the gate of NM_C (as described above, this can be achieved through the selector MUX2-1). At this time, the output of the first operational amplifier AMP_C is not connected to NM_C1, that is, it is disconnected. The IREF generated by the trimming circuit can be used to calibrate the channel. Specifically, compare the size of IREF and IOUT:

[0138] When IOUT < IREF, the third MOS transistor will have a very high drain voltage V_FLAG. At this time, the current calibration control circuit is connected to the drain of the third MOS transistor NM_C, and the current calibration control circuit will recognize the drain voltage as 1. When it is recognized as 1, S can be adjusted <m:0>To increase IOUT; that is, the current calibration control circuit outputs S to the constant current source calibration circuit <m:0>, come through S <m:0>Control the constant current source calibration circuit to adjust the IOUT increase;

[0139] When IOUT>IREF, the third MOS tube NM_C has a very low drain voltage V_FLAG, and the current calibration control circuit will recognize the drain voltage as 0. When it is recognized as 0, similarly, by adjusting S <m:0>To reduce or decrease IOUT;

[0140] In this way, S <m:0>, until, when IOUT is adjusted and the trimmed current IREF is within a close accuracy range, the system latches the calibration value after stopping the adjustment.

[0141] Finally, after the channel calibration is completed, the output end of the amplifier AMP_C is no longer connected to the third MOS tube (disconnected), but is connected to the gate of NM_C1. At this time, the channel can work or display normally.

[0142] It is worth noting that the above embodiment is for a common anode driver chip, and its output channel selects NMOS tube as output. The solution provided in this application is also applicable to a common cathode chip, which differs from the above common anode chip only in the type of MOS tube. Specifically, for a common cathode chip, a PMOS tube is used as output, and other MOS tube types are flipped accordingly.

[0143] It should be noted that the constant current source calibration circuit in this application is actually a current calibration circuit. In terms of principle and function, the selector or switch can select the connection method of the first end and the second end of the resistor R. Different connection methods can determine how the voltage drop across the resistor R changes (increase or decrease), which can determine how the voltage of the drain of the MOS tube of the constant current source output channel changes. In this way, what is actually achieved is the adjustment or calibration of the output current. Therefore, in essence, Figure 2-6 The entire circuit is a current calibration circuit.

[0144] Fig.12 A current calibration control circuit is provided in an embodiment of the present application. A compensation register including a 5-bit calibration control signal is taken as an example below (the present application only takes 5 bits as an example, but it can be any number of bits in practice). Fig.12 In the process, the first D flip-flop receives the control clock CLK and generates the clock signal CKS in turn. <5> -CKS <0> and END_FLAG signal (END_FLAG signal is used to end calibration. When it is high, calibration ends. When it is low, calibration begins.) <5> -CKS <0> and END_FLAG signal such as Fig.13 As shown, the starting time is different. The output of the first D flip-flop is connected to an input terminal of the OR gate. The output terminal of the second D flip-flop (lock represents its output signal) is connected to the other input terminal of the OR gate.

[0145] When the END_FLAG signal is valid (high level), the second D flip-flop outputs a high level, that is, Lock is high. Since the output terminal of the second D flip-flop is connected to one input terminal of the OR gate, at this time, the output of the OR gate must be high, the OR gate is locked, and the output CKSi<5:0> of the OR gate is high and will not flip. It can be understood that when Lock was low before, the output of the OR gate was related to the signal received by its other input terminal, that is, related to CKS<5:0>. Specifically, the signal CKSi<5:0> output by the OR gate is the same as the signal CKS<5:0> it receives. At this time, the OR gate is not locked.

[0146] Take the compensation register of the 5-bit calibration control signal as an example below. The current calibration control circuit collects the drain voltage of NM_C (V_FLAG signal) and stores the V_FLAG signal into each bit of the compensation register VS<4:0> in sequence. Fig.13 For Fig.12 The schematic diagram of the output waveform. Refer to Figure 12-13 for a detailed description below.

[0147] The compensation register S<4:0> includes a 4-bit offset compensation register S<3:0> and a 1-bit offset compensation polarity register S<4>. Among them, when S<4> is 0, then VDO < VD; when S<4> is 1, then VDO > VD. The magnitude of the current in the calibration circuit unit is controlled by S<3:0>. As mentioned before, the 4-bit S<3:0> actually controls the magnitude of the current in the calibration circuit unit (for example, by controlling Figure 4 the on / off of the controlled switch in to control the current of calibration circuit A and / or B), thereby controlling the magnitude of the current flowing through the resistor R. When the current flowing through R changes, the voltage drop across R will change. Thus, the voltage difference between the output VDO and VD is adjusted, thereby adjusting the drain voltage of the MOS in the constant current source output channel and ultimately achieving the purpose of adjusting the output current. It should be noted particularly that initially, the EN signal is at a low level, Fig.13 the D flip-flop in is reset when EN is low, and at this time the control circuit is not working; when EN becomes high, the current calibration starts.

[0148] The following details the specific calibration process.

[0149] Compare the initial IOUT with the reference current IREF and explain them separately for IOUT < IREF and IOUT > IREF:

[0150] (1) When IOUT > IREF, the drain voltage V_FLAG of NM_C is very low, and the calibration control circuit recognizes it as 0 (V_FLAG = 0). At this time, relevant adjustments are needed to reduce IOUT. Specifically, V_FLAG is sampled at the rising edge of CKSi<5>, and the sampled value is stored in VS<4>. At this time, the offset compensation polarity register S<4> = 0; when S<4> is 0, then VDO < VD. In the next clock cycle, IOUT is still compared with the reference current IREF: if IOUT > IREF, V_FLAG is 0. At this time, V_FLAG is sampled at the rising edge of CKSi<4>, and the sampled value is stored in VS<3>. As Fig.13 shown, VS<3> passes through an inverter, and the output of the inverter is 1. At this time, S<3> = 1. Take Figure 4 for example, then the controlled switch corresponding to S<3> in calibration circuit A or calibration circuit B conducts. It can be understood that at this time, S<3:0> increases, and the current in the calibration circuit unit increases accordingly. At this time, the voltage drop across the resistor R (the voltage difference between VDO and VD) increases. It can be understood that at this time, VDO decreases, so IOUT decreases accordingly, and IOUT will approach IREF, or in other words, the deviation between the two will decrease. If IOUT < IREF, V_FLAG will be 1. V_FLAG is sampled at the rising edge of CKSi<4>, and the sampled value is stored in VS<3>. As Fig.13 shown, VS<3> passes through an inverter, and the output of the inverter is 0. At this time, S<3> = 0. Proceed in the above manner in turn until each bit in S<3:0> has been compared. When the comparison is completed, take Figure 4 for example, then the on / off state of the final controlled switch is determined, and the voltage drop across the resistor R will also be determined, thus realizing the final calibration of IOUT.

[0151] (2) When IOUT < IREF, the drain voltage of NM_C will be very high. The current calibration control circuit is connected to the drain of NM_C, and the current calibration control circuit will recognize the drain voltage as 1 (V_FLAG = 1). At this time, relevant adjustments are needed to increase IOUT. Specifically, V_FLAG is sampled at the rising edge of CKSi<5>, and the sampled value is stored in VS<4>. The offset compensation polarity register S<4> = 1. When S<4> is 1, then VDO > VD. When VDO increases, IOUT will increase, so as to narrow the gap between IOUT and the reference current IREF. In the next clock cycle, IOUT is compared with the reference current IREF: if IOUT < IREF, V_FLAG is 1. At this time, V_FLAG is sampled at the rising edge of CKSi<4>, and the sampled value is stored in VS<3>. See Fig.13 , at this time, S <3> =1. Then S <3> The corresponding controlled switch is turned on. It can be understood that at this time, S<3:0> increases, and the current in the calibration circuit unit increases accordingly. At this time, the voltage drop across the resistor R (the voltage difference between VDO and VD) increases. As VDO increases, the current IOUT increases, gradually approaching IREF and narrowing the gap with it. If IOUT>IREF, V_FLAG is 0, and CKSi <4> The rising edge samples V_FLAG, VS <3> Stores the collected value. Fig.13 , at this time, S <3> = 0. Then S <3> The corresponding controlled switch is turned off. The above method is repeated until each bit in S<3:0> is compared.

[0152] Before the next current calibration, the D flip-flop needs to be reset, that is, EN needs to be set low. At this time, the Lock signal output by the second D flip-flop is low, and the input of one end of the OR gate is low, then the output of the OR gate output depends on the signal received at its other input end. At this time, the OR gate is unlocked.

[0153] The third aspect of the present application provides a driver chip, which can be applied to an LED display screen and is a constant current driver chip for an LED display screen, and includes a constant current source driver circuit as provided in the second aspect of the present application.

[0154] A fourth aspect of the present application provides an electronic device, which may be an LED billboard, a display screen device, etc. The electronic device includes a driver chip as provided in the third aspect of the present application.

[0155] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the embodiments can be referred to each other. The above is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims. < / m> < / m> < / m>

Claims

1. A constant current source driving circuit, characterized in that: include: A bias generating circuit for receiving a reference current, a reference current generating circuit for generating the reference current, a constant current source output channel connected to the bias generating circuit, and also includes a constant current source calibration circuit; The constant current source output channel includes a first operational amplifier and a second MOS transistor NM_CO forming a current mirror with the MOS transistor NM1 in the bias generating circuit; wherein the non-inverting terminal of the first operational amplifier is used to input the first bias voltage VD provided by the bias generating circuit; The constant current source calibration circuit includes a calibration circuit unit, a resistor connected to the calibration circuit unit, and a selector or switch connected to both ends of the resistor; wherein the calibration circuit unit is used to adjust the voltage drop across the resistor; the selector or switch is used to select one end of the resistor as an input end connected to the inverting end of the first operational amplifier, and the other end as an output end to output a third bias voltage VDO to the drain of the second MOS tube NM_CO; The constant current source output channel outputs a constant current based on the third bias voltage VDO and the second bias voltage VGI generated by the bias generating circuit.

2. A constant current source driving circuit according to claim 1, characterized in that: The calibration circuit unit comprises: A voltage source, and a voltage drop regulating circuit connected to the voltage source; The voltage drop adjustment circuit is connected to the resistor and is used to adjust the voltage drop across the resistor; The voltage drop regulation circuit includes a control module and a plurality of voltage-dividing resistors, which are connected in series in sequence and connected to the voltage source. The control module selects the output node of the voltage-dividing resistor based on a calibration control signal to generate a target voltage divider connected at both ends of the resistor.

3. A constant current source driving circuit according to claim 1, characterized in that: The calibration circuit unit comprises: Calibration circuit A and / or calibration circuit B, a bias circuit connected to a current source for generating a bias current; The bias circuit is connected to the calibration circuit A and / or calibration circuit B; The calibration circuit A and / or calibration circuit B are connected to the resistor; The currents of the calibration circuit A and the calibration circuit B are synchronously adjusted to synchronously adjust the current flowing through the resistor, or the current of the calibration circuit A is adjusted to adjust the current flowing through the resistor, or the current of the calibration circuit B is adjusted to adjust the current flowing through the resistor.

4. A constant current source driving circuit according to claim 3, characterized in that: The calibration circuit A and the calibration circuit B each include M groups of MOS tube components; each group of MOS tube components in the calibration circuit A and each group of MOS tube components in the calibration circuit B respectively form a mirror output channel A and a mirror output channel B with the bias circuit; each group of mirror output channels A and / or each group of mirror output channels B are provided with a controlled switch, and the current flowing through the resistor is adjusted by switching the controlled switch; wherein the resistor is connected to the M groups of mirror output channels A and / or the M groups of mirror output channels B.

5. A constant current source driving circuit according to claim 4, characterized in that: The mirror ratio of the M groups of MOS tube components and the bias circuit increases exponentially by 2.

6. A constant current source driving circuit according to claim 1, characterized in that: The constant current source output channel further includes: a first MOS transistor, and the second MOS transistor is X groups; wherein X>=1 and X is an integer; Wherein, the first MOS transistor is used as an output switch of the constant current source output channel; the gate of the first MOS transistor is connected to the output end of the first operational amplifier; the opening and closing of the constant current source output channel is controlled by controlling the output of the first operational amplifier; The gate of the second MOS tube is connected to the second bias voltage VGI.

7. A constant current source driving circuit according to claim 6, characterized in that: It also includes a current control circuit including X output terminals and at least one input terminal; the X output terminals are connected to the X groups of second MOS transistors in a one-to-one correspondence; the second bias voltage VGI is input to the input terminal of the current control circuit; When the control signal of the corresponding output terminal is valid, the corresponding output terminal outputs the second bias voltage VGI to the gate of the corresponding second MOS transistor.

8. A constant current source driving circuit according to claim 6, characterized in that: It also includes a current calibration control circuit, a selector, a third MOS tube, and a trimming circuit; The input end of the selector is connected to the output end of the first operational amplifier, and the selector inputs the output signal of the first operational amplifier into the gate of the first MOS tube or the gate of the third MOS tube; The drain of the third MOS tube is connected to the trimming circuit and the current calibration control circuit; the trimming circuit outputs the trimming current to the drain of the third MOS tube; the source of the third MOS tube is connected to the drain of the second MOS tube; The current calibration control circuit is used to control the constant current source calibration circuit to perform calibration; In the calibration state, the selector outputs the output signal of the first operational amplifier to the gate of the third MOS tube, and the current calibration control circuit controls the constant current source calibration circuit to adjust the current according to the drain voltage of the third MOS tube; In the output state, the selector outputs the output signal of the first operational amplifier to the gate of the first MOS tube.

9. A driver chip, characterized in that: It comprises a constant current source driving circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the driving chip as claimed in claim 9.

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