FPGA IO module layout method based on module connection relationship

By optimizing the layout position of the IO module based on the module connection relationship on the FPGA chip, the problem that the random layout of the IO module in the prior art is difficult to ensure the layout quality, and better global layout quality and timing performance are achieved.

CN115048892BActive Publication Date: 2025-03-18WUXI ESIONTECH CO LTD
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Patent Information

Application Number
CN202210723992.5
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-06-24
Publication Date
2025-03-18
Estimated Expiration
2042-06-24

AI Technical Summary

Technical Problem

The random layout of IO modules in existing FPGA chips is difficult to ensure layout quality, which affects the subsequent global layout quality and timing.

Method used

The IO module layout method based on the module connection relationship is adopted. By obtaining the layout position of the predetermined functional module in the user input netlist, the IO layout position of the IO module to be laid is determined, so that the signal connection relationship between it and the connected functional modules reaches the optimal comprehensive circuit performance.

Benefits of technology

By considering the comprehensive circuit performance, the layout position of the IO module is optimized, the quality and timing performance of subsequent global layouts are improved, and the problems caused by random layouts are avoided.

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Abstract

The present application discloses an IO module layout method based on module connection relationship of FPGA, which relates to the field of FPGA technology. The method determines the IO layout position of the IO module to be laid out based on the layout position of each predetermined functional module connected to the IO module to be laid out, so that the comprehensive circuit performance of each group of signal connection relationship between each predetermined functional module connected thereto is optimal. From the perspective of optimizing the comprehensive circuit performance, the method assists the layout by using the connection information of the functional modules provided by the user input netlist and the layout position of the predetermined functional modules fixed in advance, which can avoid the problems caused by conventional random layout, thereby making the subsequent global layout quality better.
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