Light-emitting display device

Abstract

A light-emitting display device is disclosed. The light-emitting display device includes: a light-emitting display panel including a plurality of pixels, each of the plurality of pixels operates in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light-emitting period; a data driving circuit for providing a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for the initialization period, the sampling period, the offset voltage formation period, the data writing period, and the light-emitting period of the corresponding pixel; and a timing controller for controlling the data driving circuit and the gate driving circuit, wherein the offset voltage formation period is longer than the sampling period.

Description

[0001] This application is a divisional application of the invention patent application with application number 201811406378.6, application date November 23, 2018, and invention name “Luminous display device and driving method thereof”. Technical Field

[0002] The present invention relates to a light emitting display device and a driving method thereof. Background Art

[0003] In the field of display devices, liquid crystal display (LCD) devices are widely used because they are lightweight and have low power consumption, but they require a separate light source such as a backlight. In contrast, light-emitting display devices can display images through self-luminous devices. Compared with LCD devices, light-emitting display devices have fast response time, low power consumption, and excellent viewing angles, and thus have attracted much attention as next-generation display devices.

[0004] A general light-emitting display device includes a pixel circuit formed for each pixel, and the pixel circuit controls the magnitude of a current flowing from a driving power source to a light-emitting device by switching a driving transistor according to a data voltage, thereby causing the light-emitting device to emit light to display a predetermined image.

[0005] In a general light-emitting display device, the current flowing through the light-emitting device of each pixel may change due to a change in the threshold voltage of the driving transistor caused by a process variation. Therefore, since the data current output from the driving transistor is different for each pixel even if the same data voltage is applied, the pixel circuit of the general light-emitting display device may include an internal compensation circuit for compensating the threshold voltage of the driving transistor. It is difficult to obtain uniform image quality.

[0006] In the related art, a pixel circuit having an internal compensation circuit samples a threshold voltage of a driving transistor during a sampling period, stores the sampled voltage in a capacitor, and compensates for the threshold voltage of the driving transistor using the sampled voltage stored in the capacitor.

[0007] However, there may be a difference between the sampled voltage and the actual threshold voltage of the driving transistor. In addition, due to the threshold voltage variation between the driving transistors provided in the pixels, sampling variation may occur between the sampled voltages stored in the capacitors of the pixels. As a result, the image quality may be degraded due to the voltage variation between the pixels caused by the sampling voltage variation. Summary of the invention

[0008] Accordingly, the present invention is directed to a light emitting display device and a driving method thereof that substantially obviate one or more problems due to limitations and disadvantages of the related art.

[0009] An object of the present invention is to provide a light emitting display device and a driving method thereof for preventing image quality degradation caused by voltage variation between pixels due to threshold voltage variation between driving transistors provided in the pixels.

[0010] Additional features and advantages of the present invention will be listed in the following description, and some of these features and advantages will be obvious from the description or can be understood through the practice of the present invention. These purposes and other advantages of the present invention can be realized and obtained through the structures specifically pointed out in the specification and its claims and the accompanying drawings.

[0011] To achieve these and other advantages and in accordance with the intent of the present invention, as embodied and generally described herein, a light-emitting display device may include: a light-emitting display panel including a plurality of pixels, each of the plurality of pixels operating in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light-emitting period; a data driving circuit for providing a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for the initialization period, sampling period, offset voltage formation period, data writing period, and light-emitting period of the corresponding pixel; and a timing controller for controlling the data driving circuit and the gate driving circuit, wherein the offset voltage formation period is longer than the sampling period.

[0012] In another aspect, a method for driving a light-emitting display device is provided, wherein the light-emitting display device includes a plurality of pixels, each of the plurality of pixels having a light-emitting device and a pixel circuit connected to the light-emitting device, the method may include: operating each pixel in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light-emitting period, wherein the offset voltage formation period is longer than the sampling period.

[0013] In yet another aspect, a light-emitting display device may include: a light-emitting display panel of a plurality of pixels, each of the plurality of pixels being operated in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light-emitting period; a data driving circuit for providing a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for the initialization period, the sampling period, the offset voltage formation period, the data writing period, and the light-emitting period of the corresponding pixel; and a timing controller for controlling the data driving circuit and the gate driving circuit, wherein each pixel includes a light-emitting device and a pixel circuit connected to the light-emitting device, wherein each pixel circuit includes: a driving circuit. a driving transistor having a gate electrode connected to a first pixel node, a source electrode connected to a second pixel node, and a drain electrode connected to a third pixel node; a switching circuit for providing a reference voltage or the data voltage to the first pixel node; an initialization transistor for providing an initialization voltage to the second pixel node; a light emission control transistor for providing a pixel driving voltage to the third pixel node, wherein the light emission control transistor is turned off during the initialization period and the data writing period and is turned on during the sampling period, the offset voltage forming period, and the light emission period; and a storage capacitor connected between the first pixel node and the second pixel node.

[0014] In yet another aspect, a light-emitting display device may include: a light-emitting display panel including a plurality of pixels, each of the plurality of pixels being operated in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light-emitting period; a data driving circuit for providing a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for the initialization period, the sampling period, the offset voltage formation period, the data writing period, and the light-emitting period of the corresponding pixel; and a timing controller for controlling the data driving circuit and the gate driving circuit, wherein each pixel includes a light-emitting device and a pixel circuit connected to the light-emitting device, wherein each pixel circuit includes: a driving circuit. A driving transistor having a gate electrode connected to a first pixel node, a source electrode connected to a second pixel node, and a drain electrode connected to a third pixel node; and a storage capacitor connected between the first pixel node and the second pixel node, wherein in the sampling period: the first pixel node receives a reference voltage, the second pixel node electrically floats, and the third pixel node receives a pixel driving voltage, wherein in the offset voltage forming period: each of the first pixel node and the second pixel node electrically floats, and the third pixel node receives the pixel driving voltage, wherein in the data writing period: each of the second pixel node and the third pixel node electrically floats, and the first pixel node receives the data voltage.

[0015] It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this application, illustrate exemplary embodiments of the present invention and together with the description serve to explain the principle of the present invention. In the drawings:

[0017] Figure 1 is a schematic diagram showing a light emitting display device according to an exemplary embodiment of the present invention;

[0018] Figure 2 Yes Display Figure 1 A diagram of an exemplary pixel shown in ;

[0019] Figure 3 It is a graphic Figure 2 An operation timing diagram of the operation of the pixel shown in ;

[0020] Figure 4 Yes Display Figure 1A diagram of another exemplary pixel shown in ;

[0021] Figure 5 It is a graphic Figure 4 An operation timing diagram of the operation of the pixel shown in ;

[0022] Fig. 6A and 6B is a diagram illustrating characteristics of a sampling period and an offset voltage forming period of two driving transistors having different threshold voltages in a light emitting display device according to an exemplary embodiment of the present invention;

[0023] Figure 7 1 is a waveform diagram showing a simulation operation result of three pixels arranged in the same horizontal line and including driving transistors having different threshold voltages in a light emitting display device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0025] Various modifications and variations may be made in the light emitting display device and driving method thereof of the present invention without departing from the spirit or scope of the present invention, which will be apparent to those skilled in the art. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

[0026] The shapes, sizes, proportions, angles and quantities disclosed in the accompanying drawings for the purpose of describing exemplary embodiments of the present invention are merely examples, and the present invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, when it is determined that a detailed description of the related known technology would unnecessarily obscure the key points of the present invention, the detailed description will be omitted.

[0027] Where "including," "having," and "comprising" are used in this application, other parts may be added unless "only" is used.

[0028] When interpreting an element, even if it is not explicitly stated, the element should be interpreted as including a range of error.

[0029] When describing a positional relationship, for example, when the positional relationship between two parts is described as “on,” “above,” “below,” and “after,” one or more other parts may be set between the two parts, unless “just” or “directly” is used.

[0030] When describing a time relationship, for example, when a time sequence is described as "after," "subsequently," "next," and "before," discontinuous cases may be included unless "directly" or "directly" is used.

[0031] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention.

[0032] The term "at least one" should be understood to include any and all combinations of one or more of the relevant listed items. For example, "at least one of a first item, a second item, and a third item" means all combinations of two or more items selected from the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0033] Those skilled in the art will fully appreciate that the features of the exemplary embodiments of the present invention may be combined or combined with each other in part or in whole, and may interoperate and drive each other in various ways in technology. The exemplary embodiments of the present invention may be implemented independently of each other, or implemented together in a mutually dependent relationship.

[0034] Hereinafter, a light-emitting display device and a driving method thereof according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. When adding reference numerals to the elements of each figure, similar reference numerals may refer to similar elements although they are shown in different figures. In the following description, when it is determined that a detailed description of a related known function or configuration would unnecessarily obscure the key points of the present invention, the detailed description will be omitted.

[0035] Figure 1 is a schematic diagram showing a light emitting display device according to an exemplary embodiment of the present invention.

[0036] Reference Figure 1 , a light emitting display device according to an exemplary embodiment of the present invention includes a light emitting display panel 100 , a timing control unit 300 , a data driving circuit 500 , and a gate driving circuit (or gate driver) 700 .

[0037] The light emitting display panel 100 may include a display area AA (eg, an active area) defined on a substrate and a non-display area IA (eg, an inactive area) surrounding the display area AA.

[0038] The display area AA may include a plurality of pixels P, which are respectively arranged in a plurality of pixel areas defined by first to mth (where m is a natural number equal to or greater than 2) gate lines GL1 to GLm, first to mth light emission control lines ECL1 to ECLm, and a plurality of data lines DL1 to DLp (where p is a natural number equal to or greater than 2). In addition, the display area AA may further include first to mth initialization control lines ICL1 to ICLm and first to mth sampling control lines SCL1 to SCLm. In addition, the display area AA may further include a plurality of pixel driving voltage lines provided with a pixel driving voltage VDD, a plurality of initialization voltage lines provided with an initialization voltage Vini, a plurality of reference voltage lines provided with a reference voltage Vref, and a cathode electrode layer CEL provided with a cathode voltage VSS (see Figure 2 ).

[0039] The pixels P according to the exemplary embodiment may be arranged in a stripe structure. In this case, each pixel P may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and may further include a white sub-pixel.

[0040] However, the exemplary embodiment is not limited thereto, and according to another exemplary embodiment, a plurality of pixels P may be arranged in a Pentile structure in the display area AA. In this case, each of the plurality of pixels P may include one red sub-pixel, two green sub-pixels, and one blue sub-pixel arranged one-dimensionally in a polygonal shape. For example, each pixel P having a Pentile structure may include one red sub-pixel, two green sub-pixels, and one blue sub-pixel arranged one-dimensionally in an octagonal shape. In this case, the blue sub-pixel may have the largest size, and each of the two green sub-pixels may have the smallest size.

[0041] Each of the plurality of pixels P arranged in the length direction of the gate line GL may be connected to the gate line GL passing through the corresponding pixel region, the emission control line ECL, the initialization control line ICL, the sampling control line SCL, the data line DL, the pixel driving voltage line, the initialization voltage line, the reference voltage line, and the cathode electrode layer CEL. One pixel driving voltage line, one initialization voltage line, and one reference voltage line may be connected to one sub-pixel or one unit pixel.

[0042] A plurality of pixels P are operated in the order of an initialization period, a sampling period, an offset voltage formation period, a data writing period, and a light emitting period (e.g., a signal), and emit light by a data current corresponding to a data voltage supplied to a data line DL. Here, the offset voltage formation period may be set to be longer than the sampling period. According to an exemplary embodiment, the sampling period may be set to be less than or equal to 1.5 horizontal periods. As an example, a horizontal period may refer to a time for driving a pixel of a horizontal row (e.g., a gate line). In addition, according to an exemplary embodiment, the offset voltage formation period may be set to be two to six times longer than the sampling period.

[0043] The non-display area IA may be disposed along an edge of the substrate to surround the display area AA. A portion of the non-display area IA may be disposed on the substrate and may include a pad portion connected to the data lines DL1 to DLp.

[0044] The timing controller 300 may arrange the input video data Idata into pixel-based digital data Pdata suitable for driving the light-emitting display panel 100 , and may generate a data control signal DCS from the timing synchronization signal TSS to provide the data control signal DCS to the data driving circuit 500 .

[0045] The timing controller 300 may generate a gate control signal GCS based on the timing synchronization signal TSS and may provide the gate control signal GCS to the gate driving circuit 700. The gate control signal GCS includes a gate start signal, a plurality of gate clocks, a plurality of carry clocks, a plurality of sampling clocks, and a plurality of initialization clocks. The gate control signal GCS may be provided to the gate driving circuit 700 via a pad portion.

[0046] The data driving circuit 500 may be connected to the data lines DL1 to DLp provided in the light-emitting display panel 100. The data driving circuit 500 may convert the pixel-based digital data Pdata into the pixel-based analog data voltage by using a plurality of reference gamma voltages based on the data control signal DCS provided from the timing controller 300. The data driving circuit 500 may provide the pixel-based analog data voltage to the corresponding data line DL.

[0047] The gate driving circuit 700 is connected to the first to m-th gate lines GL1 to GLm, the first to m-th light emission control lines ECL1 to ECLm, the first to m-th initialization control lines ICL1 to ICLm, and the first to m-th sampling control lines SCL1 to SCLm provided in the display area AA. The gate driving circuit 700 may provide each pixel P with a control signal having a voltage level determined for an initialization period, a sampling period, an offset voltage forming period, a data writing period, and a light emission period of each pixel P based on a gate control signal GCS. The control signal may include an initialization control signal, a sampling control signal, a scanning control signal, and a light emission control signal.

[0048] According to an exemplary embodiment, the gate driving circuit 700 generates a scanning control signal having the same period and a periodically shifted phase, and sequentially provides the scanning control signal to a plurality of gate lines GL1 to GLm. The gate driving circuit 700 also generates an initialization control signal having the same period and a periodically shifted phase, and sequentially provides the initialization control signal to a plurality of initialization control lines ICL1 to ICLm. The gate driving circuit 700 additionally generates a sampling control signal having the same period and a periodically shifted phase, and sequentially provides the sampling control signal to a plurality of sampling control lines SCL1 to SCLm. The gate driving circuit 700 also generates a carry signal having the same period and a periodically shifted phase. The gate driving circuit 700 additionally generates a light emission control signal based on at least two different carry signals, and provides the light emission control signal to the first to mth light emission control lines ECL1 to ECLm, the light emission control signal including a first gate-off voltage level and a second gate-off voltage level having different phase differences.

[0049] The gate drive circuit 700 may be formed in the left and / or right portion of the non-display area of ​​the substrate along with the process of manufacturing the thin film transistor of the pixel P. For example, the gate drive circuit 700 may be formed in the left portion of the non-display area of ​​the substrate and may be operated using a single feeding scheme to provide a scan control signal to a plurality of gate lines GL. As another example, the gate drive circuit 700 may be formed in the left and right portions of the non-display area of ​​the substrate and may be operated using a double feeding scheme to provide a scan control signal to a plurality of gate lines GL. As yet another example, the gate drive circuit 700 may be formed in the left and right portions of the non-display area of ​​the substrate and may be operated using a double feeding interlacing scheme to provide a scan control signal to a plurality of gate lines GL.

[0050] The light emitting display device according to the exemplary embodiment of the present invention may further include a level shifter unit 900 which level-shifts the gate control signal GCS.

[0051] The level shifter unit 900 may shift the high logic voltage level of the gate control signal GCS to the gate-on voltage level based on the gate-on voltage provided from the gate-on voltage source and the gate-off voltage provided from the gate-off voltage source. The level shifter unit 900 may also shift the low logic voltage level of the gate control signal GCS to the gate-off voltage level. The level shifter unit 900 may provide the level-shifted high logic voltage and low logic voltage to the gate driving circuit 700. In an example, the level shifter unit 900 may be built into, for example, the timing control unit 300 to become a part of the circuit of the timing control unit 300.

[0052] Figure 2 Yes Display Figure 1 , which shows one pixel (or one sub-pixel) of the light-emitting display panel 100 connected to an arbitrary gate line and an arbitrary data line.

[0053] Reference Figure 1 and 2 According to an exemplary embodiment of the present invention, the pixel P may include a pixel circuit PC and a light emitting device ELD.

[0054] The light emitting device ELD may be sandwiched between a first electrode (e.g., an anode electrode) connected to the pixel circuit PC and a second electrode (e.g., a cathode electrode) connected to the cathode electrode layer CEL. According to an exemplary embodiment, the light emitting device ELD may include an organic light emitting unit, a quantum dot light emitting unit, or an inorganic light emitting unit, or may include a micro light emitting diode device. The light emitting device ELD emits light by a data current provided from the pixel circuit PC.

[0055] The pixel circuit PC can be connected to the gate line GL, the light emitting control line ECL, the initialization control line ICL, the sampling control line SCL, the data line DL, the pixel driving voltage line PL, the initialization voltage line IL and the reference voltage line RL, and can provide the light emitting device ELD with a data current corresponding to the data voltage Vdata provided to the data line DL.

[0056] The pixel circuit PC may include a driving transistor Tdr, an initialization transistor Tini, a light emission control transistor Tem, a switching circuit SC (or a switching unit), and a storage capacitor Cst.

[0057] The driving transistor Tdr may be connected between the pixel driving voltage line PL and the light emitting device ELD, and may be switched according to the voltage of the storage capacitor Cst to control the current flowing from the pixel driving voltage line PL to the light emitting device ELD. According to an exemplary embodiment, the driving transistor Tdr may include a gate electrode electrically connected to the first pixel node Q, a source electrode electrically connected to the second pixel node A, and a drain electrode electrically connected to the third pixel node B.

[0058] The initialization transistor Tini may provide the initialization voltage Vini provided from the initialization voltage line IL to the second pixel node A connected to the source electrode of the driving transistor Tdr in response to the initialization control signal ICS. That is, the initialization transistor Tini may be turned on by the initialization control signal of the gate-on voltage level provided during the initialization period to provide the initialization voltage Vini to the second pixel node A. According to an exemplary embodiment, the initialization transistor Tini may include a gate electrode electrically connected to the adjacent initialization control line ICL, a first source / drain electrode electrically connected to the initialization voltage line, and a second source / drain electrode connected to the second pixel node A. The initialization transistor Tini may be turned on only during the initialization period according to the initialization control signal ICS.

[0059] The light emission control transistor Tem may supply the pixel driving voltage VDD supplied from the pixel driving voltage line PL to the third pixel node B connected to the drain electrode of the driving transistor Tdr in response to the light emission control signal ECS. That is, the light emission control transistor Tem may be turned off by the light emission control signal ECS of the gate-off voltage level supplied during the initialization period and the data writing period to block the pixel driving voltage VDD supplied to the third pixel node B, and may be turned on by the light emission control signal ECS of the gate-on voltage level supplied during the sampling period, the offset voltage forming period, and the light emission period to supply the pixel driving voltage to the third pixel node B.

[0060] According to an exemplary embodiment, the light emission control transistor Tem may include a gate electrode electrically connected to an adjacent light emission control line ECL, a first source / drain electrode electrically connected to a pixel driving voltage line PL, and a second source / drain electrode electrically connected to a third pixel node B. According to the light emission control signal ECS, the light emission control transistor Tem may be turned off during an initialization period and a data writing period and may be turned on during a sampling period, an offset voltage forming period, and a light emission period.

[0061] The switch circuit SC may provide the reference voltage Vref or the data voltage Vdata to the first pixel node Q. That is, the switch circuit SC may provide the reference voltage Vref to the first pixel node Q during the initialization period and the sampling period, and may provide the data voltage Vdata to the first pixel node Q during the data writing period. According to an exemplary embodiment, the switch circuit SC may include a first switch transistor Tsw1 that provides the data voltage Vdata to the first pixel node Q and a second switch transistor Tsw2 that provides the reference voltage Vref to the first pixel node Q.

[0062] The first switching transistor Tsw1 may provide an actual data voltage Vdata provided from the data line DL to the first pixel node Q in response to the scan control signal SS. That is, the first switching transistor Tsw1 may be turned on by the scan control signal SS of the gate-on voltage level provided during the data writing period to provide the actual data voltage Vdata to the first pixel node Q. According to an exemplary embodiment, the first switching transistor Tsw1 may include a gate electrode electrically connected to the adjacent gate line GL, a first source / drain electrode electrically connected to the adjacent data line DL, and a second source / drain electrode electrically connected to the first pixel node Q. The first switching transistor Tsw1 may be turned on only during the data writing period according to the scan control signal SS.

[0063] The second switch transistor Tsw2 may provide the reference voltage Vref provided from the reference voltage line RL to the first pixel node Q in response to the sampling control signal SCS. That is, the second switch transistor Tsw2 may be turned on by the sampling control signal SCS of the gate-on voltage level provided during the initialization period and the sampling period to provide the reference voltage Vref to the first pixel node Q. According to an exemplary embodiment, the second switch transistor Tsw2 may include a gate electrode electrically connected to the adjacent sampling control line SCL, a first source / drain electrode electrically connected to the first pixel node Q, and a second source / drain electrode electrically connected to the reference voltage line RL. The second switch transistor Tsw2 may be turned on only during the initialization period and the sampling period according to the sampling control signal SCS.

[0064] For the driving transistor Tdr, the first switching transistor Tsw1, the second switching transistor Tsw2, the initialization transistor Tini and the light emission control transistor Tem, the first source / drain electrode and the second source / drain electrode may be defined as a source electrode or a drain electrode according to the direction of current.

[0065] Each of the driving transistor Tdr, the first switching transistor Tsw1, the second switching transistor Tsw2, the initialization transistor Tini, and the light emission control transistor Tem has a material including zinc oxide (ZnO), indium zinc oxide (InZnO), or indium gallium zinc oxide (InGaZnO). 4 ) or the like. However, exemplary embodiments are not limited thereto, and the semiconductor layer may include single crystal silicon, polycrystalline silicon, or an organic material other than the oxide semiconductor material.

[0066] Each of the driving transistor Tdr, the first switching transistor Tsw1, the second switching transistor Tsw2, the initialization transistor Tini, and the light emission control transistor Tem may be an n-type thin film transistor. However, the exemplary embodiment is not limited thereto, and each of the driving transistor Tdr, the first switching transistor Tsw1, the second switching transistor Tsw2, the initialization transistor Tini, and the light emission control transistor Tem may be a p-type thin film transistor.

[0067] The storage capacitor Cst is connected between the first pixel node Q and the second pixel node A. That is, the storage capacitor Cst is connected between the gate electrode and the source electrode of the driving transistor Tdr. The storage capacitor Cst stores the difference voltage between the voltage of the first pixel node Q and the voltage of the second pixel node A, which varies according to the operation timing of the pixel P, stores the data voltage minus the reference voltage Vref and the data offset voltage Voffset (Vdata-Vref-Voffset), and uses the stored voltage to switch the driving transistor Tdr. The storage capacitor Cst is arranged in the overlapping area between the first pixel node Q and the second pixel node A. The storage capacitor Cst may include a first capacitor electrode electrically connected to the first pixel node Q, a second capacitor electrode overlapping the first capacitor electrode and electrically connected to the second pixel node A, and a capacitive layer arranged between the first capacitor electrode and the second capacitor electrode. Here, the characteristic voltage of the driving transistor Tdr may include a threshold voltage.

[0068] Figure 3 It is a graphic Figure 2 An operation timing diagram of the operation of the pixel shown in FIG.

[0069] Reference Figures 1 to 3 , the pixel P according to the exemplary embodiment of the present invention may be operated in the order of an initialization period IP, a sampling period (or compensation period) SP, an offset voltage forming period OVFP, a data writing period (or data programming period) DWP, and a light emitting period EP.

[0070] In the initialization period IP, first, the storage capacitor Cst may be initialized by the initialization voltage Vini provided to the initialization voltage line IL. In addition, in the initialization period IP, in response to the light emission control signal ECS of the first gate-off voltage level Voff, the initialization control signal ICS of the gate-on voltage level Von, and the sampling control signal SCS, the reference voltage Vref is provided to the reference voltage line RL. That is, in the initialization period IP, the light emission control transistor Tem may be turned off (i.e., OFF1) by the light emission control signal ECS of the first gate-off voltage level Voff, and the initialization transistor Tini may be turned on by the initialization control signal ICS of the gate-on voltage level Von to provide the initialization voltage Vini to the second pixel node A. Subsequently, the second switch transistor Tsw2 may be turned on by the sampling control signal SCS of the gate-on voltage level Von to provide the reference voltage Vref to the first pixel node Q, and the first switch transistor Tsw1 may be kept in a turned-off state by the scanning control signal SS of the gate-off voltage level Voff. Thus, the storage capacitor Cst may be initialized with the initialization voltage corresponding to the difference voltage between the initialization voltage Vini and the reference voltage Vref.

[0071] In the sampling period SP, the sampling voltage corresponding to the threshold voltage of the driving transistor Tdr can be stored in the storage capacitor Cst by the pixel driving voltage VDD provided to the pixel driving voltage line PL in response to the sampling control signal SCS of the gate-on voltage level Von and the light emission control signal ECS of the gate-on voltage level Von and the reference voltage Vref provided to the reference voltage line RL. In addition, in the sampling period SP, the light emission control transistor Tem can be turned on (i.e., ON) by the light emission control signal ECS of the gate-on voltage level Von, the initialization transistor Tini can be turned off by the initialization control signal ICS of the gate-off voltage level Voff, the second switch transistor Tsw2 can be kept in a turned-on state by the sampling control signal SCS of the gate-on voltage level Von, and the first switch transistor Tsw1 can be kept in a turned-off state by the scanning control signal SS of the gate-off voltage level Voff. Thus, the reference voltage Vref can be provided to the first pixel node Q by the second switch transistor Tsw2, and the second pixel node A can be electrically floated according to the turning-off of the initialization transistor Tini. Therefore, the driving transistor Tdr can be turned on by the reference voltage Vref of the first pixel node Q to operate as a source follower, and when the source voltage is the value obtained by subtracting the threshold voltage V of the driving transistor Tdr from the reference voltage Vref, TH The voltage obtained is "Vref-V TH", the driving transistor Tdr may be turned off, and thus the sampling voltage (or compensation voltage) corresponding to the threshold voltage of the driving transistor Tdr may be charged into the storage capacitor Cst. For example, a voltage close to the threshold voltage V TH The voltage or the threshold voltage V of the driving transistor Tdr TH The difference voltage between the reference voltage Vref (Vref-V TH ) can be charged into the storage capacitor Cst. In the sampling period SP, due to the threshold voltage variation ΔV between pixels P TH , a change ΔV in the sampling voltage (hereinafter referred to as sampling voltage change ΔV) may occur.

[0072] In the offset voltage forming period OVFP, a data offset voltage corresponding to the current flowing through the driving transistor Tdr may be formed at the first pixel node Q by the pixel driving voltage VDD provided to the third pixel node B from the pixel driving voltage line PL in response to the light emitting control signal ECS of the gate-on voltage level Von and the sampling voltage stored in the storage capacitor Cst. In addition, in the offset voltage forming period OVFP, the light emitting control transistor Tem may be kept in a turned-on state (i.e., ON) by the light emitting control signal ECS of the gate-on voltage level Von, the initialization transistor Tini may be kept in a turned-off state by the initialization control signal ICS of the gate-off voltage level Voff, the second switch transistor Tsw2 may be turned off by the sampling control signal SCS of the gate-off voltage level Voff, and the first switch transistor Tsw1 may be kept in a turned-off state by the scanning control signal SS of the gate-off voltage level Voff. Thus, since the supply of the reference voltage Vref may be blocked, the first pixel node Q may become an electrically high impedance (or floating) state. In addition, the voltage of the second pixel node A may vary according to the sampling current flowing through the driving transistor Tdr turned on by the sampling voltage stored in the storage capacitor Cst. In addition, due to the change in the potential of the second pixel node A, the voltage of the first pixel node Q, which may be in a high impedance state, may become (or shift to) a voltage including the data offset voltage Voffset according to the voltage coupling (or bootstrapping) of the storage capacitor Cst. As an example, in the offset voltage formation period OVFP, the final voltage of the first pixel node Q may be higher than the final voltage of the sampling period SP, for example, the final voltage of the first pixel node Q may be a voltage (Vref+Voffset) obtained by adding the reference voltage Vref and the data offset voltage Voffset. In the offset voltage formation period OVFP, the voltage of the second pixel node A may vary according to the sampling voltage change ΔV.

[0073] In the data writing period DWP, the data voltage Vdata supplied from the data line DL may be supplied to the first pixel node Q in response to the scan control signal SS of the gate-on voltage level Von and the emission control signal ECS of the second gate-off voltage level Voff.

[0074] In the data writing period DWP, the first switching transistor Tsw1 can be turned on by the scanning control signal SS of the gate-on voltage level Von, the light emitting control transistor Tem can be turned off (i.e., OFF2) by the light emitting control signal ECS of the second gate-off voltage level Voff, the second switching transistor Tsw2 can be kept in a turned-off state by the sampling control signal SCS of the gate-off voltage level Voff, and the initialization transistor Tini can be kept in a turned-off state by the initialization control signal ICS of the gate-off voltage level Voff. In addition, the actual data voltage Vdata can be provided to the data line DL from the data driving circuit. Thus, the actual data voltage Vdata can be provided to the first pixel node Q by the first switching transistor Tsw1, and the second pixel node A can be kept in an electrically floating state according to the turning-off of the initialization transistor Tini. Therefore, the voltage of the first pixel node Q may be shifted from a voltage (Vref+Voffset) obtained by adding the reference voltage Vref and the data offset voltage Voffset to the actual data voltage Vdata, and the first pixel node Q may be shifted to a voltage (Vdata-Vref-Voffset) obtained by subtracting the reference voltage Vref and the data offset voltage Voffset from the actual data voltage Vdata, as shown in the following Expression 1. That is, the pixel driving voltage VDD supplied to the driving transistor Tdr may be blocked by turning off the light emission control transistor Tem, so that no current flows through the driving transistor Tdr. When the actual data voltage Vdata is applied to the first pixel node Q in a state where no current flows in the driving transistor Tdr, a voltage proportional to the data voltage (Vdata-Vref-Voffset) obtained by subtracting the reference voltage Vref and the data offset voltage Voffset from the actual data voltage Vdata is additionally added to the storage capacitor Cst by coupling due to a voltage change of the first pixel node Q. Thus, the sampling voltage variation ΔV between pixels P can be removed by the voltage variation of the storage capacitor Cst (or the voltage variation between the first pixel node Q and the second pixel node A). In this case, the voltage additionally added to the storage capacitor Cst can be expressed as a voltage that can be coupled with the voltage variation of the first pixel node Q, such as the expression α(Vdata-Vref-Voffset). Here, α (alpha) refers to a transfer rate.

[0075] ΔV Q =Vdata -(V ref +V offset ) (1)

[0076] In the light emission period EP, the light emitting device ELD may emit light through the voltage of the storage capacitor Cst and the pixel driving voltage VDD in response to the light emission control signal ECS of the gate-on voltage level Von.

[0077] In the light emission period EP, the light emission control transistor Tem may be turned on (i.e., ON) by the light emission control signal ECS of the gate-on voltage level Von, the first switch transistor Tsw1 may be turned off by the scan control signal SS of the gate-off voltage level Voff, and the second switch transistor Tsw2 and the initialization transistor Tini may be kept in the off state by the corresponding control signals SCS and ICS of the gate-off voltage level Voff. Thus, the voltage stored in the storage capacitor Cst may be provided to the first pixel node Q, and the pixel driving voltage VDD may be provided to the drain electrode of the driving transistor Tdr through the light emission control transistor Tem. Therefore, by enabling the current to flow through the driving transistor Tdr, the source voltage (e.g., the voltage of the second pixel node) may be increased, the voltage of the storage capacitor Cst may be maintained, and the gate voltage of the driving transistor Tdr (e.g., the voltage of the first pixel node) may be increased in coupling with the voltage increase of the second pixel node. Thus, the threshold voltage variation between the pixels P may be eliminated by the voltage variation of the storage capacitor Cst (or the voltage variation between the first pixel node Q and the second pixel node A). As a result, the source current flowing through the driving transistor Tdr (data current supplied to the light emitting device) depends only on the actual data voltage and the reference voltage, and is not affected by the threshold voltage of the driving transistor Tdr.

[0078] As described above, the light-emitting display device according to the exemplary embodiment of the present invention can form a data offset voltage at the gate electrode of the driving transistor through the offset voltage formation period of each pixel between the sampling period and the data writing period. Therefore, the sampling voltage variation between pixels and the threshold voltage variation between the driving transistors provided in the pixels can be compensated, and thus the sampling voltage variation between pixels caused by the threshold voltage variation between the driving transistors provided in the pixels can be reduced.

[0079] Figure 4 Yes Display Figure 1 , wherein Figure 2 The switch circuit SC of the pixel circuit PC shown in FIG. 1 is changed. Therefore, only the switch circuit and its related elements will be described below, and repeated description of the remaining elements will be omitted.

[0080] Figure 5 It is a graphic Figure 4An operation timing diagram of the operation of the pixel shown in FIG.

[0081] Reference Figure 1 , 4 5, the switching circuit SC of the pixel circuit PC provided in the pixel P according to the present exemplary embodiment may be turned on during the initialization period and the sampling period to provide the reference voltage Vref to the first pixel node Q, and may be turned on during the data writing period to provide the data voltage Vdata to the first pixel node Q. According to an exemplary embodiment, the switching circuit SC may include a switching transistor Tsw.

[0082] In response to the scan control signal SS, the switching transistor Tsw may provide the reference voltage Vref provided from the data line DL to the first pixel node Q, and then may provide the actual data voltage Vdata provided from the data line DL to the first pixel node Q. That is, the switching transistor Tsw may be turned on (i.e., ON1) by the scan control signal SS of the first gate-on voltage level provided during the initialization period and the sampling period to provide the reference voltage Vref to the first pixel node Q, and then may be turned on (i.e., ON2) by the scan control signal SS of the second gate-on voltage level provided during the data writing period to provide the actual data voltage Vdata to the first pixel node Q. According to an exemplary embodiment, the switching transistor Tsw may include a gate electrode electrically connected to the adjacent gate line GL, a first source / drain electrode electrically connected to the adjacent data line DL, and a second source / drain electrode electrically connected to the first pixel node Q. The switching transistor Tsw may be turned on only during the initialization period, the sampling period, and the data writing period according to the scan control signal SS.

[0083] The light emitting display device including the switching circuit SC can switch the switching transistor Tsw according to the scan control signal SS and can sequentially supply the reference voltage Vref and the actual data voltage Vdata sequentially supplied from the data line DL to the first pixel node Q according to the switching of the switching transistor Tsw. Figure 1 The plurality of sampling control lines SCL1 to SCLm and the plurality of reference voltage lines RL1 to RLm in the light-emitting display panel 100 shown in the figure are provided, and a circuit in the gate driving circuit 700 for providing a sampling control signal to the plurality of sampling control lines SCL1 to SCLm is also omitted, so that the size of the gate driving circuit 700 and the number of control lines and voltage lines formed in the light-emitting display panel 100 can be reduced.

[0084] Figure 1 The data driving circuit 500 shown in FIG. 5 may alternately supply a reference voltage Vref and an actual data voltage Vdata to the data line DL in units of one (1) horizontal period or 1.5 horizontal periods.

[0085] In addition, the gate driving circuit 700 can provide each pixel P with an initialization control signal, a scanning control signal, and a light emitting control signal having a voltage level determined for the initialization period, sampling period, offset voltage formation period, data writing period, and light emitting period of each pixel P based on the gate control signal GCS.

[0086] The gate driving circuit 700 may generate a scan control signal having the same period and a periodically shifted phase, and may provide the scan control signal to a plurality of gate lines GL1 to GLm in sequence. The gate driving circuit 700 may also generate an initialization control signal having the same period and a periodically shifted phase, and may provide the initialization control signal to a plurality of initialization control lines ICL1 to ICLm in sequence. The gate driving circuit 700 may additionally generate a carry signal having the same period and a periodically shifted phase. The gate driving circuit 700 may further generate a light emitting control signal including a first gate-off voltage level and a second gate-off voltage level having different phase differences based on at least two different carry signals. The gate driving circuit 700 may additionally provide the light emitting control signal to the first to mth light emitting control lines ECL1 to ECLm.

[0087] Reference Figure 1 , 4 and 5, the pixel P according to the exemplary embodiment of the present invention may operate in the order of an initialization period IP, a sampling period (or compensation period) SP, an offset voltage forming period OVFP, a data writing period (or data programming period) DWP, and a light emitting period EP.

[0088] In the initialization period IP, first, the storage capacitor Cst may be initialized by the initialization voltage Vini supplied to the initialization voltage line IL and the reference voltage Vref supplied to the data line DL in response to the initialization control signal ICS of the gate-on voltage level Von, the scan control signal SS of the first gate-on voltage level Von, and the light emission control signal ECS of the first gate-off voltage level Voff. That is, in the initialization period IP, the light emission control transistor Tem may be turned off (i.e., OFF1) by the light emission control signal ECS of the first gate-off voltage level Voff, and the initialization transistor Tini may be turned on by the initialization control signal ICS of the gate-on voltage level Von to supply the initialization voltage Vini to the second pixel node A. Subsequently, the switching transistor Tsw may be turned on (i.e., ON1) by the scan control signal SS of the first gate-on voltage level Von to supply the reference voltage Vref to the first pixel node Q. Thus, the storage capacitor Cst may be initialized with the initialization voltage corresponding to the difference voltage between the initialization voltage Vini and the reference voltage Vref.

[0089] In the sampling period SP, a sampling voltage corresponding to the threshold voltage of the driving transistor Tdr can be stored in the storage capacitor Cst by providing the pixel driving voltage VDD to the pixel driving voltage line PL in response to the scanning control signal SS of the first gate-on voltage level Von and the emission control signal ECS of the gate-on voltage level Von and the reference voltage Vref provided to the data line DL.

[0090] In the sampling period SP, the light emission control transistor Tem may be turned on by the light emission control signal ECS of the gate-on voltage level Von, the initialization transistor Tini may be turned off by the initialization control signal ICS of the gate-off voltage level Voff, and the switching transistor Tsw may be turned on by the scanning control signal SS of the gate-on voltage level Von. Thus, the reference voltage Vref may be provided to the first pixel node Q through the switching transistor Tsw, and the second pixel node A may be electrically floated according to the turning off of the initialization transistor Tini. Therefore, the driving transistor Tdr may be turned on by the reference voltage Vref of the first pixel node Q to operate as a source follower, and when the source voltage is the value obtained by subtracting the threshold voltage V of the driving transistor Tdr from the reference voltage Vref, the second pixel node A may be electrically floated. TH The voltage obtained is "Vref-V TH ", the driving transistor Tdr may be turned off, and thus the sampling voltage (or compensation voltage) corresponding to the threshold voltage of the driving transistor Tdr may be charged into the storage capacitor Cst. For example, a voltage close to the threshold voltage V TH The voltage or the threshold voltage V of the driving transistor Tdr TH The difference voltage between the reference voltage Vref (Vref-V TH ) can be charged into the storage capacitor Cst. In the sampling period SP, due to the threshold voltage variation ΔV between pixels P TH , a change ΔV in the sampling voltage (hereinafter referred to as sampling voltage change ΔV) may occur.

[0091] In the offset voltage forming period OVFP, a data offset voltage corresponding to the current flowing through the driving transistor Tdr can be formed at the first pixel node Q by providing the pixel driving voltage VDD from the pixel driving voltage line PL to the third pixel node B in response to the light emitting control signal ECS of the gate-on voltage level Von and the sampling voltage stored in the storage capacitor Cst.

[0092] In the offset voltage forming period OVFP, the light emitting control transistor Tem may be kept in the on state by the light emitting control signal ECS of the gate on voltage level Von, the initialization transistor Tini may be kept in the off state by the initialization control signal ICS of the gate off voltage level Voff, and the switch transistor Tsw may be kept in the off state by the scanning control signal SS of the gate off voltage level Voff. Thus, since the supply of the reference voltage Vref may be blocked, the first pixel node Q may become an electrically high impedance (or floating) state. In addition, the voltage of the second pixel node A may vary according to the sampling current flowing through the driving transistor Tdr that may be turned on by the sampling voltage stored in the storage capacitor Cst. In addition, due to the change in the potential of the second pixel node A, the voltage of the first pixel node Q in the high impedance state may become (or shift to) a voltage including the data offset voltage Voffset according to the voltage coupling (or bootstrapping) of the storage capacitor Cst. As an example, in the offset voltage forming period OVFP, the final voltage of the first pixel node Q may be higher than the final voltage of the sampling period SP, for example, the final voltage of the first pixel node Q may be a voltage (Vref+Voffset) obtained by adding the reference voltage Vref and the data offset voltage Voffset. In the offset voltage forming period OVFP, the voltage of the second pixel node A may vary according to the sampling voltage variation ΔV.

[0093] In the data writing period DWP, the data voltage Vdata supplied from the data line DL may be supplied to the first pixel node Q in response to the scan control signal SS of the gate-on voltage level Von and the emission control signal ECS of the second gate-off voltage level Voff.

[0094] In the data writing period DWP, the switching transistor Tsw may be turned on (i.e., ON2) by the scanning control signal SS of the second gate-on voltage level Von, the light emission control transistor Tem may be turned off (i.e., OFF2) by the light emission control signal ECS of the second gate-off voltage level Voff, and the initialization transistor Tini may be kept in a turned-off state by the initialization control signal ICS of the gate-off voltage level Voff. In addition, the actual data voltage Vdata may be provided to the data line DL from the data driving circuit. Thus, the actual data voltage Vdata may be provided to the first pixel node Q by the switching transistor Tsw, and the second pixel node A may remain electrically floating according to the turning off of the initialization transistor Tini. Therefore, the voltage of the first pixel node Q may be shifted from the voltage (Vref+Voffset) obtained by adding the reference voltage Vref and the data offset voltage Voffset to the actual data voltage Vdata, and the first pixel node Q may be shifted to the voltage (Vdata-Vref-Voffset) obtained by subtracting the reference voltage Vref and the data offset voltage Voffset from the actual data voltage Vdata, as shown in the above equation 1. This change is the same as described above, so its repeated description will be omitted.

[0095] In the light emission period EP, the light emitting device ELD may emit light through the voltage of the storage capacitor Cst and the pixel driving voltage VDD in response to the light emission control signal ECS of the gate-on voltage level Von.

[0096] In the light emission period EP, the light emission control transistor Tem may be turned on by the light emission control signal ECS of the gate-on voltage level Von, the switch transistor Tsw may be turned off by the scan control signal SS of the gate-off voltage level Voff, and the initialization transistor Tini may be kept in the off state by the initialization control signal ICS of the gate-off voltage level Voff. Thus, the voltage stored in the storage capacitor Cst may be provided to the first pixel node Q, and the pixel driving voltage VDD may be provided to the drain electrode of the driving transistor Tdr through the light emission control transistor Tem. Therefore, by enabling current to flow through the driving transistor Tdr, the source voltage (e.g., the voltage of the second pixel node) may be increased, the voltage of the storage capacitor Cst may be maintained, and the gate voltage of the driving transistor Tdr (e.g., the voltage of the first pixel node) may be increased in coupling with the voltage increase of the second pixel node. Thus, the threshold voltage variation between the pixels P may be eliminated by the voltage variation of the storage capacitor Cst (or the voltage variation between the first pixel node Q and the second pixel node A). As a result, the source current flowing through the driving transistor Tdr (data current supplied to the light emitting device) depends only on the actual data voltage and the reference voltage, and is not affected by the threshold voltage of the driving transistor Tdr.

[0097] The light emitting display device according to the exemplary embodiment of the present invention may have Figure 2 The same effect as the pixels shown in .

[0098] Fig. 6A and 6B is a diagram illustrating characteristics of a sampling period and an offset voltage forming period of two driving transistors having different threshold voltages in a light emitting display device according to an exemplary embodiment of the present invention.

[0099] First, refer to Fig. 6A , assuming that the first driving transistor Tdr1 and the second driving transistor Tdr2 have ΔV TH When describing the characteristics of the second driving transistor Tdr2 with reference to the first driving transistor Tdr1, the threshold voltage V TH Can be V T +c, the threshold voltage V of the second driving transistor Tdr2 TH Can be V T +ΔV TH +c. The current characteristic I1 (V gs ) and the current characteristic I2 (V gs ) can be expressed as the following expression (2):

[0100] I1(V gs )=l 0 g(V gs -V T ),

[0101] I2(V gs )=l 0 g(V gs -V T -ΔV TH ),

[0102] g(O)=1 (2)

[0103] Where V T Vgs represents the gate-source voltage.

[0104] During the sampling period of the pixel, the voltage V A The change can be expressed as the following expression (3):

[0105]

[0106] The reference voltage Vref and the sampling voltage V TC may be a constant, and C is the sum of the capacitance Cst of the storage capacitor Cst and other parasitic capacitances Cp (Cst+Cp). Here, other parasitic capacitances Cp may include an auxiliary capacitor and / or a capacitance of a light emitting device.

[0107] In addition, the current Id of the driving transistor Tdr after sampling can be "10 4 C <Id<10 6 C”.

[0108] For the first driving transistor Tdr1, when at sampling time t s When integration is performed during the period, the following equation (4) can be obtained. In addition, the sampling voltage V can be obtained using the following expression (4): T :

[0109]

[0110] After the sampling period, the threshold voltage of the first driving transistor Tdr1 changes by using ΔV TH and the sampling voltage changes ΔV, the gate-source voltage V gs and the gate current I 0 g(ΔV) can be expressed as the following expression (5):

[0111] V gs =V T +ΔV TH +ΔV

[0112] I=l 0 g(ΔV) (5)

[0113] Therefore, in equation (5), there is a threshold voltage variation between driving transistors of pixels, and thus a sampling voltage variation ΔV may occur during the sampling period, and the sampling voltage variation ΔV may be compensated during the above-mentioned offset voltage forming period.

[0114] Reference Figure 6B , when the pixel driving voltage is applied to the drain electrode of the driving transistor during the offset voltage forming period, the reference voltage Vref provided to the first pixel node Q may be blocked. f During this period, the gate electrode (or the first pixel node) of the driving transistor is in a high impedance state, and the voltage of the source electrode (or the second pixel node) of the driving transistor changes due to the current flowing through the driving transistor due to the pixel driving voltage. As shown in the following expression (6), the voltage change dV A It changes according to the sampling voltage change ΔV.

[0115]

[0116] Since the reference voltage Vref provided to the first pixel node Q is blocked, the voltage between the first pixel node Q and the second pixel node A changes by Δ(V Q -V A ) can be expressed as the following expression (7):

[0117]

[0118] Where η is the reverse transfer rate of the drive transistor, ΔV A is the voltage change of the second pixel node A.

[0119] Considering the reverse transfer rate η of the driving transistor, the voltage change dV between the first pixel node Q and the second pixel node A QA It can be expressed as the following expression (8):

[0120]

[0121] Furthermore, during the offset voltage forming period, the data offset voltage Voffset may be formed according to the reverse transfer rate η of the driving transistor in Expression (7) and the voltage change of the second pixel node A in Expression (6), as shown in the following Expression (9):

[0122]

[0123] Due to the voltage change dV between the first pixel node Q and the second pixel node A occurring during the offset voltage forming period QA , current flows through the driving transistor, so the gate-source voltage of the driving transistor may gradually decrease and change, but the difference in current caused by the voltage change is negligible and can be ignored.

[0124] Therefore, by adding the voltage variation between the first pixel node Q and the second pixel node A during the offset voltage forming period, the voltage of the storage capacitor Cst, that is, the gate-source voltage V gs It can be expressed as the following expression (10):

[0125] V gs =V T +ΔV TH +ΔV+dV QA (10)

[0126] During the data writing period after the offset voltage forming period, the pixel driving voltage applied to the drain electrode of the driving transistor may be blocked, and the data voltage Vdata may be applied to the first pixel node Q. Thus, the voltage of the first pixel node Q changes by ΔV Q It can be expressed as Expression (11), which can be affected by the offset voltage Voffset programmed during the offset voltage formation period.

[0127] ΔV Q =V data -(V ref +V offset )

[0128]

[0129] During the data writing period, the pixel driving voltage applied to the drain electrode of the driving transistor may be blocked. Thus, when no current flows through the driving transistor, the voltage change Δ(V Q -V A ) can be expressed as the following expression (12). When current flows into the second pixel node A during the data writing period, the voltage variation of the second pixel node A generates an error. Therefore, according to an exemplary embodiment of the present invention, the data writing period is performed while no current flows into the second pixel node A.

[0130]

[0131] Where ΔV Q is the voltage change of the first pixel node Q, and α is the transmission rate.

[0132] The transfer rate α can be determined by the capacitance of the pixel ~Cp / (Cp+Cst), which is independent of the transistor characteristics. Considering the transfer rate α, by coupling and adding the voltage change ΔV of the first pixel node Q Q , the voltage of the storage capacitor Cst when no current flows through the drive transistor, that is, the gate-source voltage V of the drive transistor gs It can be expressed as the following equation (13):

[0133] V gs =α(V data -(V ref +V offset ))+dV QA +V T +ΔV TH +ΔV

[0134] =α(V data -V ref )+V T +ΔV TH+dV

[0135]

[0136] As expressed in expression (13), the voltage added to the storage capacitor Cst during the data writing period of the pixel can be expressed as α(Vdata-Vref-Voffset). Thus, the data offset voltage Voffset for compensating for the sampling voltage variation ΔV between pixels can be programmed (or set) to satisfy the condition of the following equation (14):

[0137] αV offset =ΔV+c 1 +o(ΔV) 2 (14)

[0138] where c 1 is a constant, o(ΔV) 2 is a second-order function of the sampling voltage change ΔV. Optionally, expression (14) may include other changes besides the sampling voltage change ΔV, and this case may also be removed.

[0139] Furthermore, the voltage Vcst stored in the storage capacitor Cst after the sampling period, the offset voltage forming period, and the data writing period can be expressed as the following expression (15):

[0140] V cst =α(V data -V ref )+V T +ΔV TH +C 2 (15)

[0141] where c 2 is a constant.

[0142] According to an exemplary embodiment of the present invention, as expressed in Expression (16), the current and voltage of the driving transistor after the data writing period of each pixel may have a value determined by the threshold voltage V TH (V T +ΔV TH +c) The difference caused by the sampling voltage change ΔV corresponding to the offset voltage. f Set as the optimal offset voltage formation time t 0 , so that when the voltage on the left side is equal to the voltage on the right side in the following expression (17), the above difference can be expressed as the following expression (18).

[0143] I(V gs )=I 0 g(α(V data -V ref )+dV)

[0144]

[0145]

[0146]

[0147] dV=c+o(ΔV) 2 (@t f =t 0 ) (17)

[0148]

[0149]

[0150]

[0151] Therefore, the current I(V gs ) and the change in threshold voltage ΔV TH It is irrelevant, as shown in the following expression (19):

[0152] I(V gs )=I 0 g(α(V data -V ref )-g′(0) -1 ) (19)

[0153] According to an exemplary embodiment of the present invention, during the offset voltage forming period, the voltage of the first pixel node may vary according to the noise voltage Vn (e.g., kickback voltage) and the data offset voltage programmed based on the current. In this case, the noise voltage Vn may be added to the equation of the data offset voltage Voffset as in Expression (9) and Expression (10). In this case, the gate-source voltage V gs The “transfer rate×Vn” changes, but this change can be removed during the data writing period. In addition, the sampling current during the sampling period can be adjusted according to the gate-source voltage V of the driving transistor caused by the noise voltage Vn. gs This can be expressed as the sampling voltage V of expression (5) T changes.

[0154] According to an exemplary embodiment of the present invention, when an additional voltage approximately linearly proportional to the threshold voltage of the driving transistor is added at the initial stage of the light emitting period of each pixel, the data offset voltage Voffset may be set to compensate (or subtract) the additional voltage kΔV (ΔV TH ), as shown in the following expression (20):

[0155]

[0156] According to an exemplary embodiment of the present invention, at the beginning of the light emission period of a pixel (or during the settling period), a voltage change (βΔV TH ), as shown in the following expression (21), where β represents a constant value determined by the mobility and parasitic capacitance of the driving transistor. In addition, by setting the data offset voltage Voffset to the optimal voltage formation time t satisfying the following expression (22): 0 And the voltage change ΔV condition can compensate for the voltage change.

[0157] βΔV TH (=βg(Vi)ΔV) (21)

[0158]

[0159]

[0160] When it is assumed that the time t near the optimum offset voltage formation time according to the exemplary embodiment of the present invention is t 0 +Δt, the sampling voltage change ΔV corresponds to the threshold voltage change ΔV TH The gate voltage g(Vi) of the gate electrode is represented by the following expression (23):

[0161]

[0162]

[0163]

[0164]

[0165] Time t and threshold voltage change ΔV near the optimal offset voltage formation time TH (which imparts a predetermined variation between pixels) may have a hyperbolic relationship as shown in the following expression (24):

[0166]

[0167] Considering the sampling time t s The optimum offset voltage formation time t 0 The relationship between t and t can be obtained as follows: s Reduce the optimal offset voltage formation time t 0Therefore, according to an exemplary embodiment of the present invention, the offset voltage forming period t 0 Can be set to the sampling time t s long, for example, the offset voltage formation period t 0 Can be set to be the sampling time t s In this case, the sampling time t s Can be set equal to or less than 1.5 horizontal periods.

[0168]

[0169]

[0170]

[0171] where S is the S factor (sub-threshold slope) of the drive transistor.

[0172] Therefore, when considering the sampling time t s Set the offset voltage forming period t 0 When the current I(V gs ) can be expressed as the following expression (26). In this case, the change in current caused by the change in threshold voltage can be fundamentally eliminated.

[0173]

[0174] As a result, the light-emitting display device according to the exemplary embodiment of the present invention can form a data offset voltage Voffset at the gate electrode (e.g., the first pixel node) of the driving transistor through the offset voltage formation period of each pixel between the sampling period and the data writing period. Therefore, the sampling voltage variation between pixels and the threshold voltage variation between the driving transistors provided in the pixels can be compensated, thereby reducing the voltage variation between pixels caused by the threshold voltage variation between the driving transistors provided in the pixels, allowing the image quality to be improved.

[0175] Figure 7 It is displayed in Figure 2 and 3 0 is a waveform diagram of a simulation operation result of three pixels arranged in the same horizontal line and including driving transistors having different threshold voltages in a light emitting display device according to an exemplary embodiment of the present invention.

[0176] from Figure 7It can be seen that when the driving transistors of the pixels have different threshold voltages, data offset voltages Voffset having different amplitudes can be formed at the first pixel node connected to the gate electrode of the driving transistor during the offset voltage formation period OVFP. Therefore, voltage variations between pixels and threshold voltage variations between driving transistors disposed in the pixels can be compensated by the data offset voltage Voffset formed at the first pixel node during the offset voltage formation period OVFP.

[0177] According to the present invention, the light emitting display device and the driving method thereof are not limited to Figures 2 to 4 The pixel structure shown in . These pixels can be applied to any light-emitting display device and its driving method that operate in the order of initialization period, sampling period (or internal compensation period), data writing period and light-emitting period. In this case, by inserting an offset voltage forming period having a longer time than the sampling period between the sampling period and the data writing period, the same effect can be achieved.

[0178] By utilizing the light-emitting display device and the driving method thereof according to an exemplary embodiment of the present invention, sampling voltage variations between pixels and threshold voltage variations between driving transistors arranged in the pixels can be compensated, thereby reducing sampling voltage variations between pixels caused by threshold voltage variations between driving transistors arranged in the pixels, allowing image quality to be improved.

[0179] The present invention is not limited to the aforementioned exemplary embodiments and the accompanying drawings, and various substitutions, modifications and variations may be made without departing from the spirit of the present invention, which will be apparent to those skilled in the art. Therefore, the scope of the present invention may be defined by the appended claims, and all changes or modifications derived from the meaning and scope of the claims and their equivalents shall be interpreted as being included within the scope of the present invention.

Claims

1. A light-emitting display device, comprising: A light emitting display panel including a plurality of pixels, each of the plurality of pixels being operated in the order of an initialization period, a sampling period, an offset voltage forming period, a data writing period, and a light emitting period; A data driving circuit, the data driving circuit is used to provide a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for an initialization period, a sampling period, an offset voltage forming period, a data writing period, and a light emitting period of the corresponding pixel; and a timing controller, the timing controller being used to control the data driving circuit and the gate driving circuit, Each pixel includes a light emitting device and a pixel circuit connected to the light emitting device, Each pixel circuit includes: a driving transistor having a gate electrode connected to a first pixel node, a source electrode connected to a second pixel node, and a drain electrode connected to a third pixel node; a switching circuit for providing a reference voltage or the data voltage to the first pixel node; an initialization transistor for providing an initialization voltage to the second pixel node; a light emission control transistor for providing a pixel driving voltage to the third pixel node, wherein the light emission control transistor is turned off during the initialization period and the data writing period and is turned on during the sampling period, the offset voltage forming period, and the light emission period; and a storage capacitor connected between the first pixel node and the second pixel node. Each pixel circuit includes only one light emission control transistor and one capacitor, and a data offset voltage is formed at the gate electrode of the driving transistor through an offset voltage forming period of each pixel between the sampling period and the data writing period. 2 . The light emitting display device according to claim 1 , wherein the offset voltage forming period is longer than the sampling period. 3 . The light emitting display device according to claim 1 , wherein the sampling period is equal to or less than 1.5 horizontal periods. 4 . The light emitting display device according to claim 1 , wherein in the offset voltage forming period, the voltage of the first pixel node changes by coupling with a voltage change of the second pixel node corresponding to a current flowing through the driving transistor.

5. The light emitting display device according to claim 4, wherein the switch circuit comprises: a first switch transistor, the first switch transistor being configured to provide the data voltage to the first pixel node; as well as A second switch transistor is used for providing the reference voltage to the first pixel node.

6. The light emitting display device according to claim 5, wherein: The first switch transistor is turned on only during the data writing period; The second switch transistor is turned on only during the initialization period and the sampling period; and The initialization transistor is turned on only during the initialization period.

7. A light-emitting display device according to claim 5, wherein the gate driving circuit is used to provide a scanning control signal for switching the first switching transistor, a sampling control signal for switching the second switching transistor, an initialization control signal for switching the initialization transistor, and a light-emitting control signal for switching the light-emitting control transistor to the corresponding pixel.

8. The light emitting display device according to claim 7, wherein: Each of the scanning control signal, the sampling control signal, the initialization control signal, and the light emitting control signal has a gate-on voltage level and a gate-off voltage level, wherein in the sampling period, each of the initialization control signal and the scanning control signal has the gate-off voltage level, and each of the sampling control signal and the light emission control signal has the gate-on voltage level, In the offset voltage forming period, each of the initialization control signal, the sampling control signal and the scanning control signal has the gate-off voltage level, and the light emission control signal has the gate-on voltage level.

9. The light emitting display device according to claim 1, wherein: The switch circuit includes a switch transistor, the switch transistor is turned on during the initialization period and the sampling period to provide the reference voltage to the first pixel node, and is turned on during the data writing period to provide the data voltage to the first pixel node; and The initialization transistor is turned on only during the initialization period.

10. The light-emitting display device according to claim 9, wherein the gate driving circuit is further used to provide a scanning control signal for switching the switching transistor, an initialization control signal for switching the initialization transistor, and a light-emitting control signal for switching the light-emitting control transistor to the corresponding pixel. 11 . The light emitting display device according to claim 1 , wherein the second pixel node is electrically floated when the initialization transistor is turned off.

12. The light-emitting display device according to claim 1, wherein in the offset voltage formation period, the data offset voltage corresponding to the current flowing through the driving transistor is formed at the first pixel node by providing a pixel driving voltage from a pixel driving voltage line to the third pixel node in response to a light-emitting control signal of a gate-on voltage level and a sampling voltage stored in the storage capacitor.

13. A light-emitting display device, comprising: A light emitting display panel including a plurality of pixels, each of the plurality of pixels being operated in the order of an initialization period, a sampling period, an offset voltage forming period, a data writing period, and a light emitting period; A data driving circuit, the data driving circuit is used to provide a data voltage to each pixel; a gate driving circuit for providing a control signal to each pixel, the control signal having a voltage level determined for an initialization period, a sampling period, an offset voltage forming period, a data writing period, and a light emitting period of the corresponding pixel; and a timing controller, the timing controller being used to control the data driving circuit and the gate driving circuit, Each pixel includes a light emitting device and a pixel circuit connected to the light emitting device, Each pixel circuit includes: a driving transistor having a gate electrode connected to a first pixel node, a source electrode connected to a second pixel node, and a drain electrode connected to a third pixel node; a light emission control transistor for providing a pixel driving voltage to the third pixel node; and a storage capacitor connected between the first pixel node and the second pixel node. Wherein during the sampling period: the first pixel node receives a reference voltage, the second pixel node is electrically floating, and the third pixel node receives a pixel driving voltage. wherein in the offset voltage forming period: each of the first pixel node and the second pixel node is electrically floating, and the third pixel node receives the pixel driving voltage, Wherein during the data writing period: each of the second pixel node and the third pixel node is electrically floating, and the first pixel node receives the data voltage, Each pixel circuit includes only one capacitor, and a data offset voltage is formed at a gate electrode of the driving transistor through an offset voltage forming period of each pixel between the sampling period and the data writing period. 14 . The light emitting display device according to claim 13 , wherein the reference voltage is supplied to the first pixel node through a data line connected to the pixel circuit. 15 . The light emitting display device according to claim 13 , wherein the offset voltage forming period is longer than the sampling period. 16 . The light emitting display device according to claim 13 , wherein the sampling period is equal to or less than 1.5 horizontal periods. 17 . The light emitting display device according to claim 13 , wherein the offset voltage forming period is two to six times longer than the sampling period.

18. The light emitting display device according to claim 13, wherein in the initialization period: the third pixel node is electrically floating, the first pixel node receives the reference voltage, and the second pixel node receives an initialization voltage, In the light emitting period: the data voltage and the reference voltage provided to the first pixel node are blocked, the initialization voltage provided to the second pixel node is blocked, and the third pixel node receives the pixel driving voltage. 19 . The light emitting display device according to claim 18 , wherein in the offset voltage forming period, the voltage of the first pixel node changes by coupling with a voltage change of the second pixel node corresponding to the current flowing through the driving transistor.

20. The light-emitting display device according to claim 13, wherein in the offset voltage formation period, the data offset voltage corresponding to the current flowing through the driving transistor is formed at the first pixel node by providing a pixel driving voltage from a pixel driving voltage line to the third pixel node in response to a light-emitting control signal of a gate-on voltage level and a sampling voltage stored in the storage capacitor. 21 . The light emitting display device according to claim 13 , wherein the light emitting control transistor is turned off during the initialization period and the data writing period, and is turned on during the sampling period, the offset voltage forming period, and the light emitting period. 22 . The light emitting display device according to claim 1 , wherein in the offset voltage forming period, a final voltage of the first pixel node is higher than a final voltage of the sampling period.

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