Pixel circuit configured to control a light emitting element

Abstract

The present invention relates to a pixel circuit configured to control a light-emitting element. The pixel circuit includes a driving transistor, which is configured to control the driving current of the light-emitting element. A first capacitor element and a second capacitor element are connected in series between the gate and the source of the driving transistor. A first switching transistor is configured to switch the connection / disconnection between a data line and an intermediate node between the first capacitor element and the second capacitor element. A second switching transistor is configured to switch the connection / disconnection between the gate and the drain of the driving transistor. A third switching transistor is configured to switch the connection / disconnection between the intermediate node and a reference power line. A fourth switching transistor is configured to switch the supply / non-supply of a driving current from the driving transistor to the light-emitting element. A fifth switching transistor is configured to switch the connection / disconnection between the anode of the light-emitting element and the reset power line.

Description

Technical Field

[0001] The present invention relates to a pixel circuit configured to control a light emitting element. Background Art

[0002] Organic light-emitting diode (OLED) elements are current-driven self-luminous elements, so they do not require a backlight. In addition, OLED elements have the advantages of achieving low power consumption, wide viewing angles, and high contrast. They are expected to contribute to the development of flat-panel display devices.

[0003] An active matrix (AM) OLED display device includes a transistor for selecting a pixel and a driving transistor for supplying current to the pixel. The transistor in the OLED display device is a thin film transistor (TFT); typically, a low temperature polysilicon (LTPS) TFT is used.

[0004] The threshold voltage and charge mobility of TFTs vary. Since the driving transistors determine the luminous intensity of the OLED display device, variations in their electrical characteristics may cause uneven brightness. Therefore, a typical OLED display device includes an adjustment circuit for compensating for variations and offsets in the threshold voltage of the driving transistors.

[0005] OLED displays may exhibit ghosting, a phenomenon known as image sticking. For example, when a full-screen image at an intermediate light level is displayed after displaying a black and white checkerboard pattern for a certain period of time, the OLED display may display a ghost of the checkerboard pattern at a different light level for a period of time.

[0006] This is caused by the hysteresis effect of the driving transistor. The hysteresis effect causes a phenomenon in which the leakage current in the field effect transistor flows differently when the gate-source voltage changes from a high voltage to a low voltage and when the gate-source voltage changes from a low voltage to a high voltage.

[0007] That is, different drain currents flow between pixels whose luminous intensity changes from black gray to middle gray and pixels whose luminous intensity changes from white gray to middle gray. For this reason, the OLED display device emits light of different intensities. This difference in drain current lasts for several frames, so the difference in luminous intensity is visually recognized as ghosting. This behavior of drain current can be explained by the current transient response characteristics through the hysteresis effect. Summary of the invention

[0008] The ghost image caused by the image sticking after displaying the black and white checkerboard pattern can be a type in which the area displaying black becomes relatively dark or a type in which the area displaying black becomes relatively bright. The same applies to the area displaying white. The image sticking depends on the current transient response characteristics caused by the hysteresis effect of the driving TFT and the characteristics of the threshold voltage compensation applied by the pixel circuit to the driving TFT. Therefore, a technology for reducing the image sticking of the pixel circuit is needed.

[0009] One aspect of the present invention is a pixel circuit configured to control the light emission of a light emitting element, the pixel circuit comprising: a light emitting element; a driving transistor configured to control a driving current of the light emitting element; a first capacitor element and a second capacitor element, which are connected in series between a gate and a source of the driving transistor; a first switching transistor configured to switch the connection / disconnection between a data line and an intermediate node located between the first capacitor element and the second capacitor element; a second switching transistor configured to switch the connection / disconnection between a gate and a drain of the driving transistor; a third switching transistor configured to switch the connection / disconnection between the intermediate node and a reference power line; a fourth switching transistor configured to switch the supply / non-supply of a driving current from the driving transistor to the light emitting element; and a fifth switching transistor configured to switch the anode of the light emitting element. The invention relates to a method for controlling the connection / disconnection between a first switching transistor and a reset power line, wherein, during an initialization period, the first switching transistor is turned off, and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are turned on, wherein, during a threshold compensation period after the initialization period, the first switching transistor and the fourth switching transistor are turned off, and the second switching transistor, the third switching transistor, and the fifth switching transistor are turned on, wherein, during a data writing period after the threshold compensation period, the first switching transistor is turned on, and the second switching transistor, the third switching transistor, the fourth switching transistor, and the fifth switching transistor are turned off, and wherein, during a light emitting period after the data writing period, the fourth switching transistor is turned on, and the first switching transistor, the second switching transistor, the third switching transistor, and the fifth switching transistor are turned off.

[0010] One aspect of the present invention is a pixel circuit configured to control the light emission of a light emitting element, the pixel circuit comprising: a light emitting element; a driving transistor configured to control the driving current of the light emitting element; a third capacitor element and a fourth capacitor element, which are connected in series between the gate and the source of the driving transistor; a sixth switching transistor, which is configured to switch the connection / disconnection between the gate of the driving transistor and a data line; a seventh switching transistor, which is configured to switch the supply / non-supply of current from a positive power line to the driving transistor; a connecting line, which connects an intermediate node between the driving transistor and the seventh switching transistor and an intermediate node between the third capacitor element and the fourth capacitor element; an eighth switching transistor, which is configured to switch the connection / disconnection between the gate of the driving transistor and a reference power line; a ninth switching transistor, which is configured to switch the supply / non-supply of current from the driving transistor to the light emitting element; and a tenth switching transistor , which is configured to switch the connection / disconnection between the reset power line and the intermediate node located between the driving transistor and the ninth switching transistor, wherein, during the initialization period, the sixth switching transistor is turned off, and the seventh switching transistor, the eighth switching transistor, the ninth switching transistor and the tenth switching transistor are turned on, wherein, during the threshold compensation period after the initialization period, the eighth switching transistor and the tenth switching transistor are turned on, and the sixth switching transistor, the seventh switching transistor and the ninth switching transistor are turned off, wherein, during the data writing period after the threshold compensation period, the sixth switching transistor is turned on, and the seventh switching transistor, the eighth switching transistor, the ninth switching transistor and the tenth switching transistor are turned off, and wherein, during the light emitting period after the data writing period, the seventh switching transistor and the ninth switching transistor are turned on, and the sixth switching transistor, the eighth switching transistor and the tenth switching transistor are turned off.

[0011] One aspect of the present invention is a pixel circuit configured to control the light emission of a light emitting element, the pixel circuit comprising: a light emitting element; a driving transistor configured to control a driving current of the light emitting element; a fifth capacitor and a sixth capacitor, which are connected in series between a gate and a source of the driving transistor; an eleventh switching transistor configured to switch the connection / disconnection between a data line and an intermediate node between the fifth capacitor and the sixth capacitor; a twelfth switching transistor configured to switch the supply / non-supply of current from a positive power line to the driving transistor; a thirteenth switching transistor configured to switch the connection / disconnection between the gate of the driving transistor and a reference power line; a fourteenth switching transistor configured to switch the connection / disconnection between an intermediate node between the driving transistor and the twelfth switching transistor and an intermediate node between the fifth capacitor and the sixth capacitor; and a fifteenth switching transistor configured to switch the connection / disconnection between the gate of the driving transistor and the reference power line. The device is configured to switch the connection / disconnection between the anode of the light-emitting element and the reset power line, wherein, during the initialization period, the eleventh switching transistor is turned off, and the twelfth switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned on, wherein, during the threshold compensation period after the initialization period, the eleventh switching transistor and the twelfth switching transistor are turned off, and the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned on, wherein, during the data writing period after the threshold compensation period, the eleventh switching transistor is turned on, and the twelfth switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned off, and wherein, during the light-emitting period after the data writing period, the twelfth switching transistor is turned on, and the eleventh switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned off.

[0012] One aspect of the present invention reduces image sticking of a display device.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 Schematically shows an example of a configuration of an OLED display device of a display apparatus;

[0015] Figure 2 A configuration example of a pixel circuit and its control signal according to one embodiment of the present specification is shown;

[0016] Figure 3 Control within one frame period Figure 2 A timing diagram of signals of the pixel circuit shown;

[0017] Figure 4AIt shows that during the initialization period, Figure 2 Transistor conduction, potentials at some nodes, and current flow in the pixel circuit shown;

[0018] Figure 4B It is shown that during the Vth compensation period, Figure 2 Transistor conduction, potentials at some nodes, and current flow in the pixel circuit shown;

[0019] Figure 4C It shows that during the data writing period, Figure 2 The transistors in the pixel circuit shown are turned on and the potentials at some nodes;

[0020] Figure 5A shows the temporal variation of a selection signal for consecutive pixel rows;

[0021] Figure 5B shows the temporal variation of another selection signal for consecutive pixel rows;

[0022] Figure 5C shows the time variation of the light emission control signal of consecutive pixel rows;

[0023] Figure 6 A pixel circuit in another configuration example of one embodiment of the present specification is shown;

[0024] Fig. 7A It shows that during the initialization period, Figure 6 The transistor in the pixel circuit shown is turned on;

[0025] Figure 7B It is shown that during the Vth compensation period, Figure 6 Transistor conduction, potentials at some nodes, and current flow in the pixel circuit shown;

[0026] Figure 8 A pixel circuit in still another configuration example of one embodiment of the present specification is shown;

[0027] Fig. 9 A pixel circuit in still another configuration example of one embodiment of the present specification is shown;

[0028] Fig.10 It is used to control the Fig. 9 A timing diagram of signals of the pixel circuit shown;

[0029] Fig.11A It shows that during the initialization period, Fig. 9 The transistors in the pixel circuit shown are turned on and the potentials at some nodes;

[0030] Fig. 11B It is shown that during the Vth compensation period, Fig. 9 The transistors in the pixel circuit shown are turned on and the potentials at some nodes;

[0031] Fig. 11C It shows that during the data writing period, Fig. 9 The transistors in the pixel circuit shown are turned on and the potentials at some nodes;

[0032] Fig. 12A Another configuration example of a pixel circuit and its control signal according to one embodiment of the present specification is shown;

[0033] Fig. 12B It is used to control Fig. 12A A timing diagram of signals of the pixel circuit shown;

[0034] Fig.13A Another configuration example of a pixel circuit and its control signal according to one embodiment of the present specification is shown;

[0035] Fig. 13B It is used to illustrate Fig.13A A diagram of the effect of a pixel circuit preventing a through current from flowing from one power source to another power source;

[0036] Fig.14 It is used to control the Fig.13A A timing diagram of signals of the pixel circuit shown;

[0037] Fig.15 Schematically shows a circuit for supplying a control signal to Fig.13A An example of a circuit layout of a pixel circuit is shown;

[0038] Fig.16 shows the change of driving current (transient current) of two pixels in negative image sticking;

[0039] Fig.17 is a graph indicating measured values ​​of the relationship between the ratio of the difference between the transient current and the expected current L |ΔIR| / L and the Vth compensation period;

[0040] Fig.18 An example of a phase difference between a select signal and a data signal is shown;

[0041] Fig.19A Provides simulation results of relevant examples regarding time variations of the gate voltage Vg of the drive transistor, the selection signal S2, and the data signal Vdata;

[0042] Fig.19BProvides simulation results of time variations of a gate voltage Vg of a driving transistor, a selection signal S2, and a data signal Vdata according to an embodiment of the present specification;

[0043] Fig. 20A Simulation results for relevant examples of the dependence of gate voltage on phase difference are provided;

[0044] Fig. 20B Provides simulation results on the dependence of gate voltage on phase difference according to one embodiment of the present specification;

[0045] Fig.21A shows the flow of current in the pixel circuit during the initialization period;

[0046] Fig.21B Shows Fig.21A An equivalent circuit for the circuit shown; and

[0047] Fig. 22 Examples of the potentials of the selection signal and the light emission control signal are shown. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Common elements in the drawings are denoted by the same reference numerals, and each element in the drawings may be exaggerated in size and / or shape for a clear understanding of the description.

[0049] Disclosed below are techniques for improving drive current control in electroluminescent display devices, and more specifically, techniques for reducing image sticking in electroluminescent display devices. Electroluminescent display devices are display devices that utilize light-emitting elements that emit light in response to a drive current, such as organic light-emitting diode (OLED) display devices.

[0050] Display the configuration of the device

[0051] Figure 1 A configuration example of an OLED display device 10 of a display apparatus is schematically shown. Figure 1 The horizontal direction is the X-axis direction, the vertical direction is the Y-axis direction, and the Y-axis direction is perpendicular to the X-axis direction. The OLED display device 10 includes a thin film transistor (TFT) substrate 100 on which an OLED element (organic light emitting element) is formed, and a packaging substrate 150 for packaging the OLED element.

[0052] The space between the TFT substrate 100 and the encapsulation substrate 150 is filled with an inert gas such as dry nitrogen and sealed. Instead of the encapsulation substrate 150, a structural encapsulation unit having a different structure, for example, a structural encapsulation unit using thin film encapsulation, may be used.

[0053] Scanning circuits 131 and 132, a driver IC 134, and a demultiplexer 136 are provided around the cathode electrode region 114 outside the display region 125 of the TFT substrate 100. The driver IC 134 is connected to an external device through a flexible printed circuit (FPC) 135. The scanning circuits 131 and 132 drive the scanning lines on the TFT substrate 100.

[0054] For example, the driver IC 134 is mounted with an anisotropic conductive film (ACF). The driver IC 134 supplies a power supply signal and a timing signal (control signal) to the scanning circuits 131 and 132 , and further supplies a data signal to the demultiplexer 136 .

[0055] The demultiplexer 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer greater than 1). The demultiplexer 136 changes the output data line of the data signal from the driver IC 134 d times in each scanning period to drive d times the data lines of the output pin of the driver IC 134.

[0056] The display area 125 includes a plurality of OLED elements (pixels) and a plurality of pixel circuits for controlling the light emission of the plurality of pixels. In the example of a color OLED display device, each OLED element emits light of one color of red, blue and green. The plurality of pixel circuits constitute a pixel circuit array.

[0057] As will be described later, each pixel circuit includes a driving TFT (driving transistor) and a storage capacitor storing a signal voltage for determining a driving current of the driving TFT. The data signal transmitted by the data line is adjusted for the threshold voltage Vth of the driving TFT and stored in the storage capacitor. The voltage of the storage capacitor determines the gate voltage (Vgs) of the driving TFT. The adjusted control voltage in the storage capacitor changes the conductance of the driving TFT in an analog manner to supply a forward bias current corresponding to the light emission level to the OLED element.

[0058] Pixel circuit configuration

[0059] Figure 2 A configuration example of a pixel circuit 200 and a control signal thereof in one embodiment of the present specification is shown. The pixel circuit 200 is included in the kth pixel circuit row (k is an integer). The pixel circuit 200 includes six transistors (TFT) P1 to P6, each of which has a gate, a source and a drain. All transistors P1 to P6 in this example are p-type TFTs. The p-type TFT can be a low-temperature polysilicon TFT. Transistor P2, transistor P3, transistor P4, transistor P5 and transistor P6 are respectively a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor and a fifth switching transistor.

[0060] The transistor P1 is a driving transistor for controlling the amount of current flowing to the OLED element E1. The source of the driving transistor P1 is connected to the power line 241 for transmitting the positive power supply potential VDD. The driving transistor P1 controls the amount of current supplied from the power line 241 to the OLED element E1 according to the voltage stored in the storage capacitor elements C1 and C2 connected in series. The storage capacitor elements C1 and C2 maintain the written voltage throughout the one frame period. The cathode of the OLED element E1 is connected to the power line 204 for transmitting the negative power supply potential VEE from the cathode power supply. The storage capacitor elements C1 and C2 are the first capacitor element and the second capacitor element, respectively.

[0061] Capacitor elements C1 and C2 are connected in series between a power line 241 for transmitting a positive power supply potential VDD and the gate of a driving transistor P1. One end of capacitor element C1 is connected to power line 241, and the other end of capacitor element C1 is connected to one end of capacitor element C2. The other end of capacitor element C2 is connected to the gate of driving transistor P1. The source / drain of transistor P4 and the source / drain of transistor P2 are connected to an intermediate node between capacitor elements C1 and C2.

[0062] The composite capacitor of the series-connected storage capacitor elements C1 and C2 stores the voltage between the gate of the driving transistor P1 and the power line 241 or the source of the driving transistor P1. The source of the driving transistor P1 is connected to the power line 241; the source potential is at the positive power supply potential VDD. Therefore, the storage capacitor elements C1 and C2 store the gate-source voltage of the driving transistor P1.

[0063] The transistor P5 is a light emission control switching transistor for controlling the on / off supply of the driving current to the OLED element E1 and the light emission of the OLED element E1 caused thereby. The source of the transistor P5 is connected to the drain of the driving transistor P1. The transistor P5 switches the on / off supply of the current to the OLED element E1 connected from its drain. The gate of the transistor P5 is connected to the control signal line 233 for transmitting the light emission control signal Em, and the transistor P5 is controlled by the light emission control signal Em from the scanning circuit 132. The light emission control signal is a selection signal for controlling the light emission of the OLED element E1.

[0064] The transistor P6 is used to provide a reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor P6 is connected to the power line 242 for transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1. The reset potential Vrst can be equal to the negative power supply potential VEE. Then, the transmission line (power line) can be shared between the reset potential Vrst and the negative power supply potential VEE.

[0065] The gate of transistor P6 is connected to the control signal line 231 for transmitting the selection signal S1, and transistor P6 is controlled by the selection signal S1. When transistor P6 is turned on by the selection signal S1 from the scanning circuit 131, transistor P6 supplies the reset potential Vrst transmitted by the power line 242 to the anode of the OLED element E1. Transistors P5 and P6 also supply the reset potential Vrst to the gate of the driving transistor P1 through transistor P3.

[0066] Transistor P3 is a switching transistor (threshold compensation transistor) that writes a voltage for applying threshold calibration (threshold compensation) to the drive transistor P1 into the storage capacitor elements C1 and C2, and is also a transistor for resetting the gate potential of the drive transistor P1. The source and drain of transistor P3 are connected to the gate and drain of the drive transistor P1. Therefore, when transistor P3 is turned on, the drive transistor P1 is diode-connected.

[0067] Transistor P4 is used to write the voltage for applying threshold compensation to driving transistor P1 into storage capacitor elements C1 and C2. Transistor P4 controls whether to supply reference potential Vref to storage capacitor elements C1 and C2. Reference potential Vref can be equal to positive power supply potential VDD. Then, a transmission line (power line) can be shared between reference potential Vref and positive power supply potential VDD. One end of the source / drain of transistor P4 is connected to the power line 202 for transmitting reference potential Vref, and the other end is connected to the intermediate node between capacitor elements C1 and C2. The gate of transistor P4 is connected to the control signal line 231 for transmitting selection signal S1, and transistor P4 is controlled by the selection signal S1 input to its gate from scanning circuit 131.

[0068] Transistors P3, P6 and P4 are controlled by selection signal S1. Therefore, these transistors P3, P6 and P4 are turned on / off at the same time. During the period when these transistors are turned on, transistor P5 is turned on to reset the gate potential of driving transistor P1, and then turned off. When transistors P3 and P4 are turned on, transistor P1 is a diode-connected transistor. The threshold compensation voltage based on positive power supply potential VDD and reference potential Vref is written into storage capacitor elements C1 and C2.

[0069] Transistor P2 is a switching transistor for selecting a pixel circuit to be supplied with a data signal and writing a data signal (data signal voltage) Vdata into storage capacitor elements C1 and C2. One end of the source / drain of transistor P2 is connected to storage capacitor elements C1 and C2, and the other end is connected to a data line 237 for transmitting a data signal Vdata.

[0070] The gate of transistor P2 is connected to a control signal line 232 for transmitting a selection signal S2 from the scanning circuit 131. Transistor P2 is controlled by the selection signal S2. The selection signal S2 is a signal different from the selection signal S1. For the pixel circuit 200, the selection signal S2 is a selection signal for controlling the supply of the data signal Vdata to the storage capacitor elements C1 and C2. When transistor P2 is turned on, transistor P2 supplies the data signal Vdata supplied from the driver IC 134 through the data line 237 to the storage capacitor elements C1 and C2.

[0071] Operation of pixel circuit

[0072] Figure 3 It is used to control the Figure 2 2 is a timing diagram of signals of the pixel circuit 200 shown. Figure 3 2 is a timing diagram for selecting the k-th pixel circuit row and writing the data signal Vdata into the pixel circuit 200. Specifically, Figure 3 The signals shown are a selection signal S1, a selection signal S2, a light emission control signal Em, and a data signal Vdata.

[0073] The period before time T1 is the light-emitting period. The selection signals S1 and S2 are high level, and the light-emitting control signal Em is low level. During this period, transistor P5 is turned on, and the remaining transistors are turned off. Therefore, the voltage stored in the composite capacitor of the series-connected storage capacitor elements C1 and C2 causes the drive current to be supplied from the power line 241 through the drive transistor P1 and the transistor P5 to the OLED element E1, so that the OLED element E1 emits light.

[0074] The period from time T1 to time T2 is the initialization period. At time T1, the selection signal S1 changes from a high level to a low level. The selection signal S2 remains at a high level and the light emission control signal Em remains at a low level. Transistors P3, P4, and P6 are turned on at time T1. Transistor P2 remains off and transistor P5 remains on.

[0075] Figure 4A 1 shows the conduction of transistors in the pixel circuit 200, the potentials at some nodes, and the flow of current during the initialization period. Current flows from the transmission line 202 of the reference potential Vref through transistors P4, P3, P5, and P6 to the transmission line 242 of the reset potential Vrst. Another current flows from the transmission line 241 of the positive power supply potential VDD through transistors P1, P5, and P6 to the transmission line 242 of the reset potential Vrst.

[0076] The potential at the intermediate node between the capacitor elements C1 and C2 becomes the reference potential Vref. The charge stored in the capacitor element C2 is discharged to initialize (reset) the gate potential of the driving transistor P1. The gate potential of the driving transistor P1 becomes the reset potential Vrst. The reset potential Vrst supplied to the gate of the driving transistor P1 per frame resets the voltage corresponding to the luminous grayscale of the previous frame and reduces the hysteresis effect. In addition, the anode potential of the OLED element is initialized. The anode potential is reduced to the reset potential Vrst, which prevents the OLED element E1 from abnormally emitting light in periods other than the luminous period.

[0077] return Figure 3 , the light emitting control signal Em changes from a low level to a high level at time T2. The selection signal S1 remains at a low level, and the selection signal S2 remains at a high level. In response to the change in the light emitting control signal Em, the transistor P5 is turned off. This state is maintained from time T2 to time T3. The time period from time T2 to time T3 is the threshold voltage (Vth) compensation period of the driving transistor P1.

[0078] Figure 4B 1 shows the conduction of transistors in the pixel circuit 200, the potential at some nodes, and the flow of current during the Vth compensation period (threshold compensation period). Transistor P3 remains on; the drain and gate of the driving transistor P1 are connected. The driving transistor P1 is in a diode connection state. Current flows from the transmission line 241 of the positive power supply potential VDD to the capacitive element C2 through the transistors P1 and P3.

[0079] The gate-source voltage of the driving transistor P1 drops to the threshold voltage and the current stops. The source potential of the driving transistor P1 is the positive power supply potential VDD, and the gate potential becomes the potential (VDD+Vth). The potential at the node between the capacitor elements C1 and C2 is the reference potential Vref.

[0080] return Figure 3 At time T3, the selection signal S1 changes from a low level to a high level, and the selection signal S2 changes from a high level to a low level. The light-emitting control signal Em remains at a high level. Transistors P3, P4, and P6 are turned off in response to the change of the selection signal S1. Transistor P2 is turned on in response to the change of the selection signal S2. Since the light-emitting control signal Em remains at a high level, transistor P5 remains turned off. The period from time T3 to time T4 is a data writing period for writing data signals to the storage capacitor elements C1 and C2.

[0081] Figure 4C1 shows the transistors in the pixel circuit 200 being turned on and the potentials at some nodes during the data writing period. Only the transistor P2 is turned on. The intermediate node between the capacitor elements C1 and C2 is supplied with a data signal (data potential) Vdata and its potential changes from the reference potential Vref to the data signal Vdata. The gate potential of the driving transistor P1 changes to (VDD+Vth+Vdata-Vref) according to the law of conservation of charge.

[0082] return Figure 3 At time T4, the selection signal S2 changes from a low level to a high level, and the light emission control signal Em changes from a high level to a low level. The selection signal S1 remains at a high level. The transistor P2 is turned off in response to the change of the selection signal S2. The transistor P5 is turned on in response to the change of the light emission control signal Em. The transistors P3, P4, and P6 remain turned off.

[0083] The period after time T4 is a light emitting period. The driving transistor P1 supplies a driving current to the OLED element E1 through the transistor P5 according to the voltage between the positive power supply potential VDD and the above potential (VDD+Vth+Vdata-Vref). This state lasts until the time T1 of the next frame.

[0084] The data writing period (also referred to as one horizontal (1H) period) is defined as a reference period. Figure 3 The length of the initialization period in the illustrated example is equal to the length of the reference period. The length of the Vth compensation period is greater than the reference period and is an integral multiple of the reference period. Figure 3 The Vth compensation period in the example is six times the reference period. This circuit allows the length of the Vth compensation period to be adjusted without changing the data writing period. By adjusting the Vth compensation period, image sticking can be effectively reduced.

[0085] For example, the initialization period may be determined to have a length of 1H to 3H and the Vth compensation period may be determined to have a length of 3H to 40H. In other words, the Vth compensation period may be determined to be 3 to 40 times the data writing period. As described above, the length of 1H is the length of the data writing period, which may be about 3μs.

[0086] Figure 5A 1 and 2 show the time variation of the selection signal S1 of the consecutive pixel rows. The selection signal S1 is outputted from the shift register circuit of the scanning circuit 131 to each pixel row in sequence. Figure 5A The graph shows the time changes of the start pulse ST of the shift register circuit, the selection signal S1_1 of the first row, and the selection signal S1_2 of the second row.

[0087] These selection signals S1 of each row are shifted by a unit time (1H period). The length of each selection signal S1 is Figure 3 The same as in the example.

[0088] Figure 5B 1 and 2 show the time variation of the selection signal S2 of the consecutive pixel rows. The selection signal S2 is outputted from the shift register circuit of the scanning circuit 131 to each pixel row in sequence. Figure 5B The time changes of the start pulse ST of the shift register circuit, the selection signal S2_1 of the first row, and the selection signal S2_2 of the second row are shown.

[0089] These selection signals S2 for each row are offset by a unit time (1H period). The length of each selection signal S2 is Figure 3 The same as in the example.

[0090] Figure 5C 1 shows the time variation of the light emission control signal Em for consecutive pixel rows. The light emission control signal Em is output from the shift register circuit in the scanning circuit 132 to each pixel row in sequence. Figure 5C The time variation of the start pulse ST of the shift register circuit, the light emitting control signal Em_1 of the first row, and the light emitting control signal Em_2 of the second row are shown. These light emitting control signals Em of each row are offset by a unit time (1H period). The length of each light emitting control signal Em is Figure 3 The same as in the example.

[0091] Reference Figures 3 to 5C The pixel circuit 200 depicted includes six transistors P1 to P6 and two capacitive elements C1 and C2, and is controlled by three control signals S1, S2 and Em. Due to the small circuit size and the small number of control signals, the pixel circuit 200 helps achieve narrow bezels and high resolution while effectively reducing image sticking.

[0092] As described above, the pixel circuit 200 resets the anode potential of the OLED element E1 with the reset potential Vrst. Therefore, the OLED element E1 is prevented from abnormally emitting light during a period when light emission is not expected, thereby achieving a high contrast ratio.

[0093] In addition, the pixel circuit 200 is adjustable during the Vth compensation period, regardless of the data writing period. Appropriate Vth compensation and the resulting reduction in image sticking are achieved by determining the appropriate length of the Vth compensation period. This feature produces a good effect, especially under high frame rate driving.

[0094] The pixel circuit 200 includes two capacitive elements C1 and C2 connected in series between the gate and source of the driving transistor P1. These capacitive elements C1 and C2 connected in series store a control voltage for controlling the amount of driving current to be supplied from the driving transistor P1. As described above, the gate potential of the driving transistor P1 after data writing does not depend on the capacitance of the capacitive elements C1 and C2. Therefore, the driving current of the OLED element is not affected by the manufacturing deviation of the capacitive elements C1 and C2.

[0095] At the same time, the pixel circuit including the series capacitor element shows a steep change (slope) of the current Ioled in the OLED element relative to the data signal Vdata (large Ioled-Vdata characteristic). Therefore, low power consumption is achieved by narrowing the range of the data signal Vdata. From the opposite point of view, high brightness display is achieved within the narrow range of the data signal Vdata.

[0096] Other pixel circuits

[0097] Hereinafter, other examples of pixel circuits are described. Figure 6 The pixel circuit 300 in another configuration example of one embodiment of the present specification is shown. The pixel circuit 300 includes six transistors P11 to P16 and two storage capacitance elements C11 and C12. The transistors P11 to P16 are p-type TFTs.

[0098] The transistor P12, the transistor P13, the transistor P14, the transistor P15 and the transistor P16 are respectively the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the ninth switch transistor and the tenth switch transistor. Figure 6 The pixel circuit of the pixel circuit shown may be configured with an n-type TFT. The storage capacitor elements C11 and C12 are the third capacitor element and the fourth capacitor element, respectively.

[0099] Transistor P11 is a driving transistor for controlling the amount of current flowing to OLED element E1. Driving transistor P11 controls the amount of current to be supplied to OLED element E1 from a power supply of positive power supply potential VDD according to the voltage stored in storage capacitor element C12. This is because both ends of storage capacitor element C11 are connected to potential VDD. Storage capacitor element C12 maintains the written voltage throughout one frame period.

[0100] Generally speaking, when the potential of the data line changes with a horizontal period as a cycle, the parasitic capacitance between the data line and the gate node of the driving transistor affects the gate node potential of the driving transistor, thereby changing the brightness (crosstalk). In the case where the data voltage is stored in a composite capacitor of the series capacitors C1 and C2, the capacitance is small and crosstalk is easily caused. In contrast, a configuration in which the data voltage is stored in a single capacitor (e.g. Figure 6 The circuit in the embodiment of the present invention is characterized in that the frequency of crosstalk occurrence is low due to the large capacitance. The storage capacitor element C11 contributes to the threshold voltage compensation. The cathode of the OLED element E1 is connected to the power supply line 304 for transmitting the negative power supply potential VEE from the cathode power supply.

[0101] exist Figure 6 In the configuration example of , the capacitor elements C11 and C12 are connected in series between the power supply line 341 for transmitting the positive power supply potential VDD and the gate of the driving transistor P11. One end of the storage capacitor element C11 is connected to the power supply line 341. One end of the storage capacitor element C12 is connected to the gate of the driving transistor P11. The intermediate node between the storage capacitor elements C11 and C12 is connected to the source of the driving transistor P11.

[0102] The voltage of the storage capacitor elements C11 and C12 is the voltage between the gate of the driving transistor P11 and the power supply line 341. The source of the driving transistor P11 is connected to the power supply line 341 through the switching transistor P13. When the transistor P13 is turned on, the storage capacitor element C12 stores the gate-source voltage of the driving transistor P11.

[0103] Transistors P13 and P15 are switching transistors for controlling the on / off of the light emission of the OLED element E1. The source of the transistor P13 is supplied with a positive power supply potential VDD, and the drain of the transistor P13 is connected to the source of the driving transistor P11. The source of the transistor P15 is connected to the drain of the driving transistor P11. The gates of the transistors P13 and P15 are connected to the light emission control line 333; the transistors P13 and P15 are identically controlled by the light emission control signal Em input to their gates from the scanning circuit 132.

[0104] The transistor P16 is used to provide the anode of the OLED element E1 with a reset potential Vrst. One end of the source / drain of the transistor P16 is connected to the power supply line 342 for transmitting the reset potential Vrst, and the other end is connected to the node between the drain of the driving transistor P11 and the source of the switching transistor P15.

[0105] The gate of transistor P16 is connected to the selection signal line 331 for transmitting the selection signal S1; transistor P16 is controlled by the selection signal S1. When transistor P16 is turned on by the selection signal S1 input to its gate from the scanning circuit 131, transistor P16 supplies the reset potential Vrst transmitted by the power supply line 342 to the anode of the OLED element E1 during the period in which transistor P15 is turned on.

[0106] The transistor P14 is a switching transistor that writes a voltage for applying threshold compensation to the driving transistor P11 into the storage capacitor element C12. The transistor P14 controls whether or not the reference potential Vref is supplied to the storage capacitor element C12.

[0107] One end of the source / drain of the transistor P14 is connected to the power supply line 302 for transmitting the reference potential Vref, and the other end is connected to one end of the storage capacitor element C12. The gate of the transistor P14 is connected to the selection signal line 331 for transmitting the selection signal S1; the transistor P14 is controlled by the selection signal S1 input to its gate from the scanning circuit 131.

[0108] When transistor P14 is turned on, driving transistor P11 operates as a source follower circuit so that its threshold voltage is written to capacitor C12 located between the gate and source of driving transistor P11. The voltage of storage capacitor C11 is determined by the threshold voltage of driving transistor P11 and the voltage between positive power supply potential VDD and reference potential Vref.

[0109] The transistor P12 is a switching transistor for selecting a pixel circuit to be supplied with a data signal Vdata and writing the data signal (data signal voltage) Vdata to the gate of the driving transistor P11. One end of the source / drain of the transistor P12 is connected to a data line 337 for transmitting the data signal Vdata, and the other end is connected to the storage capacitor element C12.

[0110] The gate of transistor P12 is connected to a selection signal line 332 for transmitting a selection signal S2. Transistor P12 is controlled by the selection signal S2 supplied from the scanning circuit 131. When transistor P12 is turned on, transistor P12 supplies a data signal Vdata supplied from the driver IC 134 to the gate of the driving transistor P11 through a data line 337.

[0111] Storage capacitor elements C11 and C12 are connected in series between a power line 341 for transmitting a positive power supply potential VDD and the gate of the driving transistor P11. The potential at the node between the storage capacitor elements C11 and C12 is supplied to the source of the driving transistor P11. The potential at the node between the storage capacitor elements C11 and C12 is based on the data signal Vdata, the reference potential Vref, the threshold voltage Vth of the driving transistor P11, and the capacitance of the storage capacitor elements C11 and C12. Specifically, it is expressed as (Vdata*C1 / (C1+C2)-Vth+Vref*C1 / (C1+C2).

[0112] Afterwards, when the light emission control signal Em becomes low level, the potential at the node becomes VDD, but the voltage stored in the storage capacitor element C12 is maintained. Therefore, the potential of the gate node of the driving transistor P11 becomes ((Vdata-Vref)*C1 / (C1+C2)+VDD+Vth). In other words, the gate-source voltage of the driving transistor P11 is maintained at ((Vdata-Vref)*C1 / (C1+C2)+Vth) during the light emission period.

[0113] Figure 6 The timing diagram of the signal used to control the pixel circuit 300 in one frame period is similar to Figure 3 The timing diagram is the same. Fig. 7A 1 shows that the transistors are turned on during the initialization period. During the initialization period, transistors P16 and P15 are turned on. Therefore, the reset potential Vrst is supplied to the anode of the OLED element E1. Therefore, the OLED element E1 is prevented from abnormally emitting light during the period when it is not expected to emit light. The transistor P14 is turned on and resets the gate of the driving transistor P11 with the potential Vref.

[0114] Figure 7B The diagram shows the transistors in the pixel circuit 300 being turned on, the potentials at some nodes, and the flow of current during the Vth compensation period. The transistors P14 and P16 are turned on, and the other transistors are turned off.

[0115] Since the transistor P14 is turned on, the reference potential Vref is supplied to the gate of the driving transistor P11. Since the transistor P16 is turned on, the reset potential Vrst is supplied to the drain of the driving transistor P11. The potential at the source of the driving transistor P11 or the node between the storage capacitor elements C11 and C12 becomes Vref-Vth. The storage capacitor element C12 stores the threshold voltage Vth of the driving transistor P11. After the Vth compensation period, the data signal Vdata is supplied to the gate of the driving transistor P11 and the storage capacitor element C12.

[0116] As described above, the pixel circuit 300 resets the anode potential of the OLED element E1 with the reset potential Vrst. Therefore, the OLED element E1 is prevented from abnormally emitting light during a period when light emission is not expected, thereby achieving a high contrast ratio.

[0117] In addition, the pixel circuit 300 is adjustable in the Vth compensation period, regardless of the data writing period. Appropriate Vth compensation and the resulting reduction of image sticking are achieved by determining the appropriate length of the Vth compensation period. Especially under high frame rate driving, its short horizontal period 1H makes the problem more prominent; this feature produces a great effect.

[0118] The pixel circuit 300 supplies a reset potential Vrst or a low potential to the drain of the driving transistor P11 during the Vth compensation period. Therefore, the drain-source voltage of the driving transistor P11 is always large enough. Even if the driving transistor P11 has a normally-on characteristic and the gate-source voltage becomes positive, current flows through the driving transistor P11 to apply Vth compensation because the potential of the drain is fixed at Vrst.

[0119] Next, still another example of the pixel circuit is described. Figure 8 A pixel circuit 400 in still another configuration example of one embodiment of the present specification is shown. The pixel circuit 400 includes six transistors P21 to P26 and two storage capacitor elements C21 and C22. The transistors P21 to P26 are p-type TFTs.

[0120] The transistor P22, the transistor P23, the transistor P24, the transistor P25, and the transistor P26 are respectively the eleventh switch transistor, the twelfth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor, and the fifteenth switch transistor. Figure 8 The pixel circuit of the pixel circuit shown may be configured with an n-type TFT. Storage capacitor elements C21 and C22 are a fifth capacitor element and a sixth capacitor element, respectively.

[0121] The transistor P21 is a driving transistor for controlling the amount of current flowing to the OLED element E1. The driving transistor P21 controls the amount of current to be supplied to the OLED element E1 from the power supply of the positive power supply potential VDD according to the voltage stored in the storage capacitor elements C21 and C22. The storage capacitor elements C21 and C22 maintain the written voltage throughout the one frame period. The cathode of the OLED element E1 is connected to the power supply line 404 for transmitting the negative power supply potential VEE from the cathode power supply.

[0122] exist Figure 8 In the configuration example of , storage capacitor elements C21 and C22 are connected in series between a power supply line 441 for transmitting a positive power supply potential VDD and the gate of a driving transistor P21. One end of the storage capacitor element C21 is connected to the power supply line 441. One end of the storage capacitor element C22 is connected to the gate of the driving transistor P21. The intermediate node between the storage capacitor elements C21 and C22 is connected to the source / drain of the transistor P25.

[0123] The voltage of the storage capacitor elements C21 and C22 is the voltage between the gate of the driving transistor P21 and the power supply line 441. The source of the driving transistor P21 is connected to the power supply line 441 through the switching transistor P23. When the transistor P23 is turned on, the storage capacitor elements C21 and C22 store the gate-source voltage of the driving transistor P21.

[0124] The transistor P23 is a switching transistor for controlling the on / off of the light emission of the OLED element E1. The source of the transistor P23 is supplied with a positive power supply potential VDD, and the drain of the transistor P23 is connected to the source of the driving transistor P21. The gate of the transistor P23 is connected to the light emission control line 433, and the transistor P23 is controlled by the light emission control signal Em input to its gate from the scanning circuit 132.

[0125] The transistor P26 is used to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of the transistor P26 is connected to the power supply line 442 for transmitting the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0126] The gate of transistor P26 is connected to the selection signal line 431 for transmitting the selection signal S1; transistor P26 is controlled by the selection signal S1. When transistor P26 is turned on by the selection signal S1 input to its gate from the scanning circuit 131, transistor P26 supplies the reset potential Vrst transmitted by the power supply line 442 to the anode of the OLED element E1.

[0127] Transistors P24, P25 and P26 are switch transistors for writing a voltage for applying threshold compensation to the driving transistor P21 into the storage capacitor C22. The transistor P24 controls whether to supply a reference potential Vref to the storage capacitor C22. The transistor P26 controls whether to supply a reset potential Vrst to the drain of the driving transistor P21. The transistor P25 switches the connection between the source of the driving transistor P21 and the intermediate node between the storage capacitors C21 and C22.

[0128] One end of the source / drain of the transistor P24 is connected to the power supply line 402 for transmitting the reference potential Vref, and the other end is connected to one end of the storage capacitor element C22. The gate of the transistor P24 is connected to the selection signal line 431 for transmitting the selection signal S1; the transistor P24 is controlled by the selection signal S1 input to its gate from the scanning circuit 131.

[0129] One end of the source / drain of transistor P25 is connected to the source of driving transistor P21, and the other end is connected to the intermediate node between storage capacitor elements C21 and C22. The gate of transistor P25 is connected to the selection signal line 431 for transmitting the selection signal S1; transistor P25 is controlled by the selection signal S1 input to its gate from the scanning circuit 131.

[0130] When transistors P24 and P25 are turned on, the driving transistor P21 is used as a source follower circuit so that its threshold voltage is written into the capacitor C22 located between the gate and source of the driving transistor P21. The voltage of the storage capacitor C21 is determined by the threshold voltage stored in the storage capacitor C22 and the voltage between the positive power supply potential VDD and the reference potential Vref. In this state, the gate potential of the driving transistor P21 is Vref, and the potential of the intermediate node between the storage capacitors C21 and C22 is (Vref-Vth).

[0131] The transistor P22 is a switching transistor for selecting a pixel circuit to be supplied with a data signal Vdata and writing the data signal Vdata into the storage capacitor elements C21 and C22. One end of the source / drain of the transistor P22 is connected to the data line 437 for transmitting the data signal Vdata, and the other end is connected to the intermediate node between the storage capacitor elements C21 and C22.

[0132] The gate of the transistor P22 is connected to a selection signal line 432 for transmitting a selection signal S2. The transistor P22 is controlled by the selection signal S2 supplied from the scanning circuit 131. When the transistor P22 is turned on, the transistor P22 supplies the data signal Vdata supplied from the driver IC 134 to the storage capacitor elements C21 and C22 through the data line 437; the potential of the intermediate node between the storage capacitor elements C21 and C22 becomes Vdata, and the potential of the gate of the driving transistor P21 becomes (Vdata+Vth).

[0133] At the beginning of the light emission period, the transistor P23 is turned on and supplies the positive power supply potential VDD to the source of the driving transistor P21. However, the gate potential of the driving transistor P21 is maintained at (Vdata+Vth) because the gate potential of the driving transistor P21 is maintained by the composite capacitor of the series storage capacitor elements C21 and C22.

[0134] Figure 8 The timing diagram of the signal used to control the pixel circuit 400 in one frame period is Figure 3 The timing diagram is the same as that of . During the light emitting period, transistor P25 is turned off and transistor P23 is turned on. The voltage stored in the storage capacitor elements C21 and C22 is supplied to the gate and source of the driving transistor P21, so that the driving transistor P21 supplies a driving current to the OLED element E1 according to the voltage.

[0135] As described above, the pixel circuit 400 resets the anode potential of the OLED element E1 with the reset potential Vrst. Therefore, the OLED element E1 is prevented from abnormally emitting light during a period when light emission is not expected, thereby achieving a high contrast ratio.

[0136] In addition, the pixel circuit 400 is adjustable during the Vth compensation period, regardless of the data writing period. Appropriate Vth compensation and the resulting reduction in image sticking are achieved by determining the appropriate length of the Vth compensation period. This feature produces a good effect, especially under high frame rate driving.

[0137] The gate potential of the driving transistor P21 after data writing does not depend on the capacitance of the capacitor elements C21 and C22. Therefore, the driving current of the OLED element is not affected by the manufacturing variation of the capacitor elements C21 and C22.

[0138] The pixel circuit 400 exhibits a steep change (slope) of the current Ioled in the OLED element relative to the data signal Vdata (large Ioled-Vdata characteristic). Therefore, low power consumption is achieved by narrowing the range of the data signal Vdata, because the potential of the data line changes little when the displayed image changes like a movie, so as to achieve less charge storage to and release from the capacitor connected to the data line. This is because the gate-source voltage of the driving transistor P21 is (Vdata+Vth-Vdata) and is not affected by the capacitance of the storage capacitor elements C21 and C22. From the opposite point of view, high brightness display is achieved by a narrow range of data signals Vdata.

[0139] The pixel circuit 400 supplies a reset potential Vrst or a low potential to the drain of the driving transistor P21 during the Vth compensation period. Therefore, the drain-source voltage of the driving transistor P21 is always large enough. Even if the driving transistor P21 has a normally-on characteristic, current flows through the driving transistor P21 to apply Vth compensation.

[0140] Next, still another example of the pixel circuit is described. Fig. 9 A pixel circuit 500 in another configuration example of one embodiment of the present specification is shown. Figure 2 The pixel circuit 500 includes six transistors N1 to N6 and two storage capacitor elements C31 and C32. Transistor N2, transistor N3, transistor N4, transistor N5 and transistor N6 are respectively a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor and a fifth switch transistor.

[0141] The transistors N1 to N6 are n-type TFTs. The n-type TFTs are, for example, oxide semiconductor TFTs. The pixel circuit 500 has a circuit configuration such that Figure 2The p-type transistor in the pixel circuit 200 is replaced by an n-type transistor. The storage capacitor elements C31 and C32 correspond to the storage capacitor elements C1 and C2, respectively. The storage capacitor elements C31 and C32 are the first capacitor element and the second capacitor element, respectively.

[0142] Fig.10 It is used to control the Fig. 9 The timing diagram of the signals of the pixel circuit 500 is shown in FIG. The control signals S11, S21 and Em1 are shown with Figure 3 The control signals S1, S2 and Em shown in FIG. 1 vary in opposite time. Therefore, transistors N1 to N6 are switched in the same manner as Figure 2 The pixel circuit 500 generates the above-mentioned Figure 2 The effect of the pixel circuit 200 in FIG.

[0143] Power lines 502, 504, 541 and 542 transmit reference potential Vref, negative power potential VEE, positive power potential VDD and reset potential Vrst respectively. Signal line 537 transmits data signal Vdata; control lines 531 and 532 transmit selection signals S11 and S21 respectively; control line 533 transmits light emission control signal Em1.

[0144] Fig.11A , Fig. 11B and Fig. 11C Turning on of transistors in the pixel circuit 500 and potentials at some nodes in the initialization period, the Vth compensation period, and the data writing period are respectively shown.

[0145] like Fig.11A As shown, transistors N3 to N6 are turned on during the initialization period. The drain and gate of the driving transistor N1 are at the positive power supply potential VDD. The intermediate node between the storage capacitor elements C31 and C32 is at the reference potential Vref, and the anode of the OLED element E1 is at the reset potential Vrst.

[0146] like Fig. 11B As shown, transistors N3, N4 and N6 are turned on during the Vth compensation period. The gate of the driving transistor N1 is at a potential (Vrst+Vth). The intermediate node between the storage capacitor elements C31 and C32 is at a reference potential Vref, and the anode of the OLED element E1 is at a reset potential Vrst.

[0147] like Fig. 11CAs shown, transistor N2 is turned on during the data writing period. The intermediate node between storage capacitor elements C31 and C32 is at the data signal (potential) Vdata, and the anode of OLED element E1 is at the reset potential Vrst. The gate of driving transistor N1 is at the potential (Vdata-Vref+Vrst+Vth). The gate potential of driving transistor N1 is maintained at (Vdata-Vref+Vrst+Vth) during the light emitting period.

[0148] Next, still another example of the pixel circuit is described. Fig. 12A FIG. 6 shows a configuration example of a pixel circuit 600 and its control signal in one embodiment of the present specification. Figure 2 Pixel circuit 600 is different from pixel circuit 200 in FIG. Pixel circuit 600 includes n-type transistors N12, N13, N14 and N16 instead of p-type transistors P2, P3, P4 and P6 in pixel circuit 200. Transistors N12, N13, N14 and N16 may be oxide semiconductor transistors. P-type transistors P1 and P5 may be low-temperature polysilicon thin film transistors. During the light emission period, the gate voltage Vgs of driving transistor P1 is (Vdata-Vref+Vth).

[0149] The source / drain regions of transistors N12, N13, and N14 are connected to storage capacitors. Oxide semiconductor transistors generate a small off-leakage current, so the voltage (charge) stored in the storage capacitor can be maintained for a long time. Low-frequency driving has a longer frame period or a longer light-emitting period. Therefore, before refreshing by writing a video signal, etc., the brightness changes greatly, which can cause flickering (flickering of light or brightness fluctuation) problems. This configuration of the pixel circuit reduces flickering in low-frequency driving.

[0150] exist Fig. 12A The transistor N16 in the circuit configuration example shown has the same conductivity type as the transistors N13 and N14, and therefore, the pixel circuit can be operated with fewer control signals ( Fig. 12A There are 3 types of control (for example, a single signal S1 is used to control three transistors N13, N14 and N16.

[0151] The control signals of the pixel circuit 600 include selection signals S31 and S32 and a light emission control signal Em. Fig. 12B It is used to control the Fig. 12A 2 is a timing diagram of signals of the pixel circuit 600 shown. Fig. 12B is a timing diagram for selecting the kth row and writing the data signal into the pixel circuit 600. Specifically, Fig. 12B The signals shown in are the selection signal S31, the selection signal S32, and the light emission control signal Em.

[0152] The period before time T11 is the light-emitting period. The selection signals S31 and S32 and the light-emitting control signal Em are at a low level. During this period, transistor P5 is turned on and the remaining transistors are turned off. Therefore, the voltage stored in the composite capacitor of the series-connected storage capacitor elements C1 and C2 causes the drive current to be supplied from the power line 241 through the drive transistor P1 and the transistor P5 to the OLED element E1, so that the OLED element E1 emits light.

[0153] The time period from time T11 to time T12 is the initialization time period. At time T11, the selection signal S31 changes from a low level to a high level. The selection signal S32 remains at a low level and the light emission control signal Em remains at a low level. Transistors N13, N14, and N16 are turned on at time T11. Transistor N12 remains turned off and transistor P5 remains turned on.

[0154] The light emitting control signal Em changes from a low level to a high level at time T12. The selection signal S31 maintains a high level and the selection signal S32 maintains a low level. In response to the change in the light emitting control signal Em, the transistor P5 is turned off. This state is maintained from time T12 to time T13. The period from time T12 to time T13 is a threshold voltage (Vth) compensation period of the driving transistor P1. Fig. 12B In the example of , the length of the Vth compensation period is 7H (7 horizontal periods). In the case where the frame frequency is 120 Hz, the length of 1H is 3 μs.

[0155] The selection signal S31 changes from a high level to a low level at time T13. The light emission control signal Em maintains a high level. In response to the change of the selection signal S31, the transistors N13, N14 and N16 are turned off.

[0156] In the several (in Fig. 12B At time T14 after the horizontal period (five in the example of FIG. 1 ), the selection signal S32 changes from a low level to a high level. The selection signal S31 remains at a low level and the light-emitting control signal Em remains at a high level. The transistor N12 is turned on in response to the change of the selection signal S32. Since the light-emitting control signal Em remains at a high level, the transistor P5 remains turned off. The period from time T14 to time T15 is a data writing period (1H) for writing data signals to the storage capacitor elements C1 and C2.

[0157] The selection signal S32 changes from a high level to a low level at time T15. The selection signal S31 maintains a low level and the light emission control signal Em maintains a high level. The transistor N12 is turned off in response to the change of the selection signal S32.

[0158] In the several (in Fig. 12BAt time T16 after the five horizontal periods in the example, the light emission control signal Em changes from a high level to a low level. The selection signals S31 and S32 remain at a low level. The transistor P5 is turned on in response to the change of the light emission control signal Em. The transistors N12, N13, N14, and N16 remain turned off.

[0159] The period after time T16 is a light emitting period. The driving transistor P1 supplies a driving current to the OLED element E1 through the transistor P5 according to the above voltage (Vdata-Vref+Vth). This state continues until time T11 of the next frame.

[0160] The relationship between pixel circuit 200 and pixel circuit 600 is applied to pixel circuit 300 or 400, and one or more p-type transistors in pixel circuit 300 or 400 can be replaced with n-type transistors. For example, transistors P12, P14, and P16 in pixel circuit 300 or transistors P22, P24, P25, and P26 in pixel circuit 400 can be replaced with n-type transistors.

[0161] Next, still another example of the pixel circuit is described. Fig.13A FIG. 7 shows a configuration example of a pixel circuit 700 and its control signal in one embodiment of the present specification. Figure 2 2. The pixel circuit 700 is different from the pixel circuit 200 in FIG. In addition to the configuration of the pixel circuit 200, the pixel circuit 700 further includes a p-type switching transistor P7. The transistor P7 is a sixteenth switching transistor. The transistor P7 is connected between the driving transistor P1 and the power supply line 241; its source is connected to the power supply line 241, and its drain is connected to the source of the driving transistor P1.

[0162] The transistor P7 is turned off during the initialization period to disconnect the pixel circuit 700 from the power supply line 241. This prevents a through current from flowing from the power supply VDD to the power supply Vrst. Fig. 13B This effect is described in more detail. In response to the transistor P7 being turned off, the stored charge flows to the reset power supply line 242, so that the current flowing through the driving transistor P1 gradually decreases. The reduced anode potential of the OLED element E1 reduces the brightness of black and prevents through current, thereby reducing power consumption.

[0163] Fig.14 It is used to control the Fig.13A The timing diagram of the signals of the pixel circuit 700 shown in FIG. Figure 3 In addition to the time changes of the selection signals S1 and S2 and the light control signal Em, Fig.14The second light emitting control signal Em2 to be supplied to the gate of the transistor P7 is also included. The second light emitting control signal Em2 is high during the initialization period (from T1 to T2) and low during the remaining periods. The transistor P7 is turned off during the initialization period and turned on during the remaining periods.

[0164] Fig.15 An example of a circuit layout for supplying control signals S1, S2, Em and Em2 to a pixel circuit 700 is schematically shown. Two scanning circuits 131A and 131B are arranged on the left side of a display area, and two scanning circuits 132A and 131B are arranged on the right side of the display area. Each scanning circuit includes a shift register. The scanning circuits 131A and 131B output selection signals S1 and S2, respectively. The scanning circuits 132A and 132B output light emission control signals Em and Em2, respectively.

[0165] Vth compensation period

[0166] Hereinafter, the Vth compensation period is described. Studies by the inventors have shown that image sticking can be reduced to a negligible level by determining the Vth compensation period within a specific range. First, an example of image sticking is described.

[0167] For example, when the image displayed on an OLED display device changes from a fixed black and white checkerboard pattern to a uniform intermediate luminous grayscale image, a ghost image affected by the fixed pattern will be displayed for a period of time. The intensity (brightness difference) and life span of the ghost image depend on the display period of the fixed pattern (stress time); the ghost image will disappear over time. Image sticking produces two types of ghost images: negative ghost images with opposite brightness (opposite polarity) to the fixed pattern and positive ghost images with the same brightness (same polarity) as the fixed pattern.

[0168] Fig.16 The figure shows the change of the driving current (transient current) of two pixels in the negative image sticking. The driving current is the current flowing in the OLED element. The larger the driving current, the higher the brightness of the OLED element. Fig.16 In FIG. 1 , the horizontal axis represents time and the vertical axis represents drive current. Current LB represents the drive current of a pixel that changes from black (lowest grayscale) to an intermediate grayscale. Current LA represents the drive current of a pixel that changes from white (highest grayscale) to an intermediate grayscale.

[0169] At time T0, the data signal of the pixel changes from the value of the initial image to the value of the expected image. The drive current LB of the pixel that has displayed black increases to be higher than (overshoots) the expected drive current L, and then gradually decreases toward the expected drive current L. On the contrary, the drive current LA of the pixel that has displayed white decreases to be lower than (undershoots) the expected drive current L, and then gradually increases toward the expected drive current L.

[0170] In positive image sticking, the drive current LB of the pixel that has displayed black increases sharply to a value lower than the expected drive current L, and then gradually increases toward the expected drive current L. Conversely, the drive current LA of the pixel that has displayed white decreases sharply to a value higher than the expected drive current L, and then gradually decreases toward the expected drive current L.

[0171] The current difference between the transient currents is defined as |ΔIR|=|LA–LB|. The current difference |ΔIR| is the absolute value of the difference between the current LA and the current LB at time T0.

[0172] The inventors studied the relationship between image sticking and the current difference between the transient current and found that image sticking is not perceived when the ratio (|ΔIR| / L) of the difference between the transient current and the expected current L is small. Specifically, when the ratio |ΔIR| / L of the difference between the transient current and the expected current L is not higher than 1% (0.01), the inventors were able to ignore the influence of image sticking.

[0173] Fig.17 It is a graph of measured values ​​indicating the relationship between the ratio of the difference between the transient current and the expected current L |ΔIR| / L and the Vth compensation period. The horizontal axis represents the length of the Vth compensation period, and the vertical axis represents the ratio of the difference between the transient current and the expected current L |ΔIR| / L. The measurement shows that when the Vth compensation period is in the range of 10 microseconds (μs) to 120μs, the ratio of the difference between the transient current and the expected current L |ΔIR| / L can be maintained at no more than 1%. Therefore, by determining the Vth compensation period in the range from 10μs to 120μs, image sticking can be effectively reduced.

[0174] Control Signal

[0175] Hereinafter, the control signal of the pixel circuit is described. One embodiment of the present specification specifies the phase difference θ between the selection signal (scanning signal) S2 and the data signal Vdata. The selection signal S2 is a control signal for turning on / off transistors P2, P12, P22, etc. to control writing of data signals to the pixel circuit.

[0176] In one embodiment of the present specification, the phase difference θ between the two signals is specified as follows:

[0177] –π / 3≤θ≤0 (when f=120Hz, -2μs≤t≤0),

[0178] Where f is the frame rate and t is the time interval between two signals.

[0179] Fig.18The phase relationship between the selection signal S2 and the data signal Vdata is schematically shown. The phase of each signal is defined as the midpoint between the rise and fall of the pulse (the center of the low-level pulse). When the phase of the selection signal S2 is ahead of the phase of the data signal Vdata, the phase difference is defined as positive, and when the phase of the selection signal S2 is delayed, the phase difference is defined as negative. Fig.18 From top to bottom, there are shown the selection signal S2 and the data signal Vdata having phase differences θ of −2π, −π / 3, and 0. The phase difference of −2π is the same as the phase difference of 0.

[0180] According to the above control sequence for the pixel circuit, Vth compensation and data writing are performed by time sharing. However, in the related example of a pixel circuit (7T1C pixel circuit) including seven transistors and one capacitor element, Vth compensation and data writing are performed simultaneously; the gate voltage Vg of the driving transistor P1 needs time to converge. In this embodiment, Vth compensation is completed at the beginning of data writing; writing the data voltage (video signal) is performed separately. Therefore, the gate voltage of the driving transistor P1 changes together with the decline of the S2 pulse.

[0181] As described above, the related examples and the present embodiment differ in the dependence of the gate voltage on the phase difference. This embodiment has a wider margin for the phase difference and Fig.18 In the embodiment of the present invention, the phase difference margin extends on the left side. Determining the phase difference within the above range prevents the data signals of adjacent rows from mixing and reduces display defects. The foregoing description of the phase difference is applicable to a pixel circuit including an n-type transistor.

[0182] Fig.19A Simulation results on time variation of gate voltage Vg, selection signal S2 and data signal Vdata of a driving transistor for a related example of a 7T1C pixel circuit are provided. Lines 601, 602 and 603 represent time variation of selection signal S2, data signal Vdata and gate voltage Vg, respectively.

[0183] Fig.19B The simulation results of the time variation of the gate voltage Vg, the selection signal S2 and the data signal Vdata of the driving transistor in this embodiment are provided. Lines 611, 612 and 613 respectively represent the time variation of the selection signal S2, the data signal Vdata and the gate voltage Vg. Fig.19B and Fig.19A , the gate voltage Vg in this embodiment changes along with the decrease of the S2 signal pulse.

[0184] Fig. 20A Simulation results on the dependence of gate voltage on phase difference are provided for a related example of a 7T1C pixel circuit. Fig. 20BThe simulation results of the present embodiment on the dependence of the gate voltage on the phase difference are provided. Fig. 20B and Fig. 20A , this embodiment has a larger phase difference margin.

[0185] Next, the potential of the control signal is described. In one embodiment of the present specification, the low potential of the selection signal S1 is determined to be a low value. The selection signal S1 is a control signal for turning on / off transistors P6, P16, P26, etc. to supply the reset potential Vrst to the anode of the OLED element E1. Although the following description takes transistor P6 as an example, the same description applies to transistors P16 and P26.

[0186] For example, the low potential Vgl of the selection signal S1 is determined to be not higher than (VEE-6.3) V. If the cathode power supply potential VEE is -2.7V, the low potential Vgl of the selection signal S1 is not higher than -9V.

[0187] Fig.21A The current flow in the pixel circuit 200 during the initialization period is shown. Some elements are excluded from the figure. Fig.21B Shows Fig.21A The equivalent circuit of the circuit in has been referred to Figure 4A The operation in the initialization period is described. During the initialization period, the current in transistor P6 is constant, so the gate-source voltage Vgs of transistor P6 is constant. Since the source of transistor P6 and the anode of OLED element E1 are at the same potential, reducing the low potential Vgl of the selection signal S1 will reduce the anode potential V anode The inventors' experiments show that by determining the low potential Vgl of the selection signal S1 to be within the above range, the abnormal light emission of the OLED element E1 is reduced and the brightness of black is reduced during the initialization period.

[0188] Instead of lowering the low potential Vgl of the selection signal S1, lowering the threshold voltage Vth of the transistor P6 is used to prevent abnormal light emission of the OLED element E1 and reduce the brightness of black. The threshold voltage Vth can be defined as Vth=Vgs@Id=1e–7A, where Id represents the current flowing through the transistor P6. The inventor's experiments show that by determining the threshold voltage Vth of the transistor P6 to be no higher than (VEE-1.3)V, the abnormal light emission of the OLED element E1 can be reduced and the brightness of black can be reduced. If the cathode power supply potential VEE is -2.7V, the threshold voltage Vth of the transistor P6 should be no higher than -4V.

[0189] Fig. 22An example of the potential of the selection signals S1 and S2 and the light emission control signal Em is shown. The high potential of the selection signals S1 and S2 and the light emission control signal Em is 8V, which is common to all signals. Although the low potential of the selection signal S2 and the light emission control signal Em is -7V, the low potential of the selection signal S1 is determined to be no higher than -9V.

[0190] As described above, the embodiments of the present invention have been described; however, the present invention is not limited to the above-described embodiments. Those skilled in the art can easily modify, add or convert each element in the aforementioned embodiments within the scope of the present invention. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A pixel circuit, the pixel circuit being configured to control light emission of a light emitting element, the pixel circuit comprising: Light emitting element; a driving transistor configured to control a driving current of the light emitting element; a first capacitive element and a second capacitive element, wherein the first capacitive element and the second capacitive element are connected in series between the gate and the source of the driving transistor; a first switch transistor configured to switch connection / disconnection between a data line and an intermediate node located between the first capacitive element and the second capacitive element; a second switch transistor configured to switch connection / disconnection between a gate and a drain of the drive transistor; a third switch transistor configured to switch connection / disconnection between the intermediate node and a reference power line; a fourth switching transistor configured to switch supply / non-supply of a driving current from the driving transistor to the light emitting element; as well as a fifth switching transistor configured to switch connection / disconnection between the anode of the light emitting element and a reset power supply line, wherein, during the initialization period, the first switch transistor is turned off, and the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor are turned on, wherein, during a threshold compensation period after the initialization period, the first switch transistor and the fourth switch transistor are turned off, and the second switch transistor, the third switch transistor and the fifth switch transistor are turned on, wherein, during a data writing period after the threshold compensation period, the first switch transistor is turned on, and the second switch transistor, the third switch transistor, the fourth switch transistor, and the fifth switch transistor are turned off, wherein, during a light emitting period after the data writing period, the fourth switch transistor is turned on, and the first switch transistor, the second switch transistor, the third switch transistor and the fifth switch transistor are turned off, Wherein, the fifth switch transistor is a p-type thin film transistor, and Among them, the following relationship is satisfied: Vgl≤VEE-6.3V, Among them, Vgl represents the low potential of the control signal of the fifth switch transistor, and VEE represents the cathode potential of the light emitting element.

2. The pixel circuit according to claim 1, in, The first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor are p-type thin film transistors, and The first capacitor and the second capacitor are connected in series between a positive power line of the light emitting element and a gate of the driving transistor.

3. The pixel circuit according to claim 1, in, The first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor are n-type thin film transistors, and The first capacitor and the second capacitor are connected in series between the anode of the light emitting element and the gate of the driving transistor.

4. The pixel circuit according to claim 1, wherein: In the initialization period, the phase difference θ of the control signal of the first switch transistor relative to the phase of the signal on the data line satisfies the following relationship: -π / 3≤θ≤0.

5. The pixel circuit according to claim 1, in, The first switch transistor, the second switch transistor, the third switch transistor and the fifth switch transistor are n-type oxide semiconductor thin film transistors, and Wherein, the driving transistor and the fourth switch transistor are p-type low-temperature polysilicon thin film transistors.

6. The pixel circuit according to claim 1, further comprising: A sixteenth switching transistor, The fourth switch transistor is connected between the driving transistor and the light emitting element. wherein the sixteenth switch transistor is connected between the drive transistor and a power line configured to transmit the drive current, wherein the sixteenth switch transistor is turned off during the initialization period, and The sixteenth switching transistor is turned on during the threshold compensation period, the data writing period and the light emitting period.

7. A pixel circuit, the pixel circuit being configured to control light emission of a light emitting element, the pixel circuit comprising: Light emitting element; a driving transistor configured to control a driving current of the light emitting element; a third capacitive element and a fourth capacitive element, the third capacitive element and the fourth capacitive element being connected in series between the gate and the source of the driving transistor; a sixth switch transistor configured to switch connection / disconnection between the gate of the driving transistor and a data line; a seventh switching transistor configured to switch supply / non-supply of current from the positive power line to the driving transistor; a connecting line connecting an intermediate node between the driving transistor and the seventh switch transistor and an intermediate node between the third capacitor and the fourth capacitor; an eighth switching transistor configured to switch connection / disconnection between the gate of the driving transistor and a reference power line; a ninth switching transistor configured to switch supply / non-supply of current from the driving transistor to the light emitting element; as well as a tenth switching transistor configured to switch connection / disconnection between a reset power supply line and an intermediate node between the driving transistor and the ninth switching transistor, wherein, during the initialization period, the sixth switch transistor is turned off, and the seventh switch transistor, the eighth switch transistor, the ninth switch transistor and the tenth switch transistor are turned on, wherein, during a threshold compensation period after the initialization period, the eighth switch transistor and the tenth switch transistor are turned on, and the sixth switch transistor, the seventh switch transistor and the ninth switch transistor are turned off, wherein, during a data writing period after the threshold compensation period, the sixth switch transistor is turned on, and the seventh switch transistor, the eighth switch transistor, the ninth switch transistor and the tenth switch transistor are turned off, wherein, during the light emitting period after the data writing period, the seventh switch transistor and the ninth switch transistor are turned on, and the sixth switch transistor, the eighth switch transistor and the tenth switch transistor are turned off, Wherein, the tenth switch transistor is a p-type thin film transistor, and Among them, the following relationship is satisfied: Vgl≤VEE-6.3V, Among them, Vgl represents the low potential of the control signal of the tenth switch transistor, and VEE represents the cathode potential of the light emitting element.

8. The pixel circuit according to claim 7, wherein: The sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the ninth switch transistor and the tenth switch transistor are p-type thin film transistors.

9. The pixel circuit according to claim 7, wherein: In the initialization period, the phase difference θ of the control signal of the sixth switch transistor relative to the phase of the signal transmitted by the data line satisfies the following relationship: -π / 3≤θ≤0.

10. The pixel circuit according to claim 7, in, The sixth switch transistor, the eighth switch transistor and the tenth switch transistor are n-type oxide semiconductor thin film transistors, and Wherein, the driving transistor, the seventh switching transistor and the ninth switching transistor are p-type low-temperature polysilicon thin film transistors.

11. A pixel circuit, the pixel circuit being configured to control light emission of a light emitting element, the pixel circuit comprising: Light emitting element; a driving transistor configured to control a driving current of the light emitting element; a fifth capacitor and a sixth capacitor, wherein the fifth capacitor and the sixth capacitor are connected in series between the gate and the source of the driving transistor; an eleventh switch transistor configured to switch connection / disconnection between the data line and an intermediate node between the fifth capacitor and the sixth capacitor; a twelfth switching transistor configured to switch supply / non-supply of current from the positive power line to the driving transistor; a thirteenth switching transistor configured to switch connection / disconnection between the gate of the driving transistor and a reference power line; a fourteenth switching transistor configured to switch connection / disconnection between an intermediate node between the driving transistor and the twelfth switching transistor and the intermediate node between the fifth capacitor and the sixth capacitor; as well as a fifteenth switching transistor configured to switch connection / disconnection between the anode of the light emitting element and a reset power supply line, wherein, during the initialization period, the eleventh switch transistor is turned off, and the twelfth switch transistor, the thirteenth switch transistor, the fourteenth switch transistor and the fifteenth switch transistor are turned on, wherein, during a threshold compensation period after the initialization period, the eleventh switching transistor and the twelfth switching transistor are turned off, and the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned on, wherein, during a data writing period after the threshold compensation period, the eleventh switching transistor is turned on, and the twelfth switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned off, wherein, during the light emitting period after the data writing period, the twelfth switching transistor is turned on, and the eleventh switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are turned off, Wherein, the fifteenth switch transistor is a p-type thin film transistor, and Among them, the following relationship is satisfied: Vgl≤VEE-6.3V, Among them, Vgl represents the low potential of the control signal of the fifteenth switching transistor, and VEE represents the cathode potential of the light-emitting element.

12. The pixel circuit according to claim 11, wherein: The eleventh switching transistor, the twelfth switching transistor, the thirteenth switching transistor, the fourteenth switching transistor and the fifteenth switching transistor are p-type thin film transistors.

13. The pixel circuit according to any one of claims 1, 7 and 11, wherein: The threshold compensation period is not shorter than 10 μs and not longer than 120 μs.

14. The pixel circuit according to any one of claims 1, 7 and 11, wherein: The threshold compensation period is not less than three times the data writing period and not more than forty times the data writing period.

15. The pixel circuit according to claim 11, wherein: In the initialization period, the phase difference θ of the control signal of the eleventh switch transistor relative to the phase of the signal transmitted by the data line satisfies the following relationship: -π / 3≤θ≤0.

16. The pixel circuit according to claim 11, in, The eleventh switch transistor, the thirteenth switch transistor, the fourteenth switch transistor and the fifteenth switch transistor are n-type oxide semiconductor thin film transistors, and Wherein, the driving transistor and the twelfth switch transistor are p-type low-temperature polysilicon thin film transistors.

Images