A junction gate enhancement mode GaN device based on pp heterojunction

Abstract

This invention belongs to the field of power semiconductor technology, specifically providing a junction-gate enhancement-mode GaN device based on a PP heterojunction to solve many problems existing in current devices, such as narrow gate voltage swing, large gate leakage current, high process requirements, and high cost. This invention utilizes a P-type wide bandgap semiconductor layer to deplete the high-concentration two-dimensional electron gas beneath it, obtaining an enhancement-mode device. Simultaneously, a P-type polysilicon layer is disposed on the P-type wide bandgap semiconductor layer; the PP heterojunction formed by these two layers can prevent current injection from the gate into the P-type wide bandgap semiconductor layer, thereby achieving extremely low gate leakage current. Furthermore, this novel junction gate can avoid the gate Schottky thermoelectric instability of p-GaNHEMTs and the influence of interface charge or traps between the dielectric and semiconductor layers in MIS structures on the reliability and stability of the threshold voltage. Ultimately, this invention has advantages such as large gate voltage swing, low gate leakage current, low channel-to-surface resistance, high threshold voltage consistency, and high stability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to high voltage longitudinal / lateral semiconductor devices, specifically providing a junction gate enhancement GaN device based on a PP heterojunction. Background Technology

[0002] As a third-generation semiconductor device, GaN devices are well-suited for high-frequency and high-power applications due to their inherent physical properties. Enhanced GaN devices can eliminate the need for protection circuits and improve system reliability in power electronics applications, making them a key research focus.

[0003] Traditional enhancement-mode lateral GaN devices mainly include p-GaN gate or p-AlGaN gate enhancement-mode HEMT devices, recess-gate HEMTs, and HEMTs using fluorine ion implantation. p-GaN gate or p-AlGaN gate enhancement-mode HEMT devices utilize p-GaN or p-AlGaN to deplete the two-dimensional electron gas at the channel, as described in the literature “Y. Uemoto et al., “Gateinjection transistor (GIT) — A normally-off AlGaN / GaN power transistor using conductivity modulation,” IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3393–3399, Dec. 2007.”, with the following structure: Figure 1As shown; however, the PN diode formed by p-GaN or p-AlGaN and the barrier layer will conduct at a gate voltage of ~3V, thereby introducing a large gate current and increasing drive losses. This characteristic limits the gate voltage swing, generally not exceeding 5V, thus increasing the difficulty of drive circuit design. Furthermore, the p-GaN gate and the metal gate electrode generally form a reverse-biased Schottky contact to reduce the gate current. However, the Schottky contact has low reliability and stability, which in turn leads to low reliability and stability of gate leakage. Recessed-gate HEMTs are constructed by etching away a portion of the barrier layer under the gate dielectric (remaining thickness d), as described in the literature "Y. Zhao, et al., "Effects of recess depths on performance of AlGaN / GaN power MIS-HEMTs on the Si substrates and threshold voltage model of different recess depths for the using HfO2 gate insulator," Solid-State Electronics, 2020, 163:107649.", and its structure is as follows. Figure 2 As shown, this structure can reduce the two-dimensional electron gas concentration at the channel, thereby realizing an enhancement-mode device. However, the reduction in channel polarization increases the specific on-resistance. Furthermore, the threshold voltage of this device increases with decreasing thickness of the barrier layer retained under the channel gate dielectric, typically around 1V-2V. Moreover, when the retained barrier layer is thinned to a few nm, the electron mobility within the channel decreases drastically due to channel disruption, leading to a multiple increase in specific on-resistance. Additionally, the thickness d retained through etching is very difficult to control precisely, significantly affecting the threshold voltage uniformity of the device on the wafer. An enhancement-mode device can also be realized using a MIS-HEMT structure implanted with fluorine ions under the gate channel. However, the scattering introduced by F ions reduces electron mobility and increases device resistance, while also presenting thermal stability issues. Furthermore, the interface charge between the dielectric I and semiconductor S in the MIS gate structure is typically very large, severely impacting threshold voltage stability and reliability.

[0004] Vertical GaN devices can be fabricated with higher breakdown voltages and lower specific on-resistances than lateral HEMTs. Traditional enhancement-mode vertical GaN devices mainly utilize CAVET structures and inversion layer channel MIS structures fabricated with p-GaN base regions. Compared to inversion layer channel MIS structures, CAVET structures utilize two-dimensional electron gas as a gate-controlled channel, and their extremely high electron mobility can significantly reduce the overall specific on-resistance of the device. For example, the literature "Ji, Dong, et al. Normally OFF trench CAVET with active Mg-doped GaN as current blocking layer." IEEE Transactions on Electron Devices 64.3, 805-808, 2016. discloses a CAVET structure formed by MIS gate. Figure 3 As shown, this structure suffers from many drawbacks similar to MIS-HEMT, such as difficulty in forming enhancement-mode devices, or the need to fabricate a recessed gate to form enhancement-mode devices, which increases the difficulty of the process, leads to poor process consistency, damages the channel, and causes the channel resistance to increase exponentially. Furthermore, traditional metal-gate CAVET structures can only form depletion-mode devices, as shown in the literature "Chowdhury, et al. Enhancement and depletion mode AlGaN / GaN CAVET with Mg-ion-implanted GaNas current blocking layer." IEEE Electron Device Letters 29.6, 543-545, 2008., which is not conducive to power electronic system applications. The p-GaN gate CAVET structure is shown in the literature "Nie, Hui, et al. 1.5-kV and 2.2-mΩcm". 2 As described in "Vertical GaN Transistors on Bulk-GaN Substrates" (IEEE ElectronDevice Letters, 35.9, 939-941, 2014), its structure is as follows: Figure 4 As shown, this structure has similar drawbacks to p-GaNHEMT, such as small gate voltage swing, significant increase in gate current when the gate voltage is higher than 3V, and high difficulty in driving circuit.

[0005] To overcome the above problems, the applicant disclosed a structure with a MIS gate in patent document application number 202210146339.7 entitled "An Enhanced MIS-GaN Device"; however, the introduction of this MIS structure will bring high dielectric (I) / semiconductor (S) interface charge or traps, thereby affecting the threshold voltage stability and reliability. Summary of the Invention

[0006] The purpose of this invention is to address the numerous problems existing in the above-mentioned enhancement-mode GaN devices, such as poor threshold voltage consistency, poor stability and reliability, channel damage, high channel resistance, narrow gate voltage swing, large gate leakage current, and complex driving design, by providing a junction-gate enhancement-mode GaN device based on a PP heterojunction. This invention has the advantages of large gate voltage swing, low gate leakage current, low channel resistance, low overall on-resistance, high threshold voltage consistency, high electrothermal stability and reliability, simple process, and low cost.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0008] A junction-gate enhancement-mode GaN device based on a PP heterojunction includes: a substrate 1-9, a buffer layer 1-8 disposed on the substrate, a channel layer 1-5 disposed on the buffer layer, a barrier layer 1-4 disposed on the channel layer, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, and a junction gate portion disposed on the barrier layer 1-4, and a first dielectric passivation layer 1-10 and a second dielectric passivation layer 1-11; characterized in that...

[0009] A metal source 1-12 is disposed on the source ohmic contact metal layer 1-6, and a metal drain 1-13 is disposed on the drain ohmic contact metal layer 1-7. The junction gate portion is located between the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7, and is disposed adjacent to the source ohmic contact metal layer 1-6. The junction gate portion is composed of a P-type wide bandgap semiconductor layer 1-1, a P-type polysilicon layer 1-3, and a metal gate 1-2 stacked sequentially from bottom to top, that is: the P-type wide bandgap semiconductor layer is disposed on the barrier layer 1-4, the P-type polysilicon layer is disposed on the P-type wide bandgap semiconductor layer, and the metal gate is disposed on the P-type polysilicon layer. The first dielectric passivation layer 1-10 is located on the upper surface of the barrier layer and partially covers both sides of the P-type polysilicon layer 1-3. The second dielectric passivation layer 1-11 is located on the upper surface of the first dielectric passivation layer and covers the metal gate 1-2.

[0010] Furthermore, the gate metal 1-2 extends to both sides of the P-type polysilicon layer 1-3 to form a gate field plate, which is located on the upper surface of the first dielectric passivation layer 1-10; the source metal 1-12 extends to the drain metal 1-13 to form a source field plate, which is located on the upper surface of the second dielectric passivation layer 1-11 and covers the junction gate portion; the drain metal 1-13 extends to the source metal 1-12 to form a drain field plate, which is located on the upper surface of the second dielectric passivation layer 1-11.

[0011] Furthermore, the P-type polysilicon layer forms a Schottky contact or an ohmic contact with the gate metal.

[0012] Furthermore, the P-type polysilicon layer adopts a two-layer structure consisting of a bottom lightly doped layer and a top heavily doped layer. The bottom lightly doped layer can prevent the reverse-biased PP junction from breaking down prematurely or the tunneling current from being too large, and the threshold voltage can be adjusted by setting different thicknesses. The top heavily doped layer is conducive to forming an ohmic contact with the gate metal, avoiding the impact of carrier accumulation on the stability of the threshold voltage.

[0013] Furthermore, the p-type wide bandgap semiconductor layer is p-type GaN, AlGaN, or NiO, with a doping concentration greater than 1e17cm⁻¹. -3 .

[0014] Furthermore, the substrate is made of Si, SiC, or sapphire; the buffer layer is made of C-doped or Fe-doped high-resistivity GaN or AlGaN; the channel layer is made of unintentionally doped GaN or InGaN; and the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN.

[0015] A junction-gate enhancement-mode GaN device based on a PP heterojunction includes: a substrate 2-12, a metal drain 2-13 disposed under the substrate, a breakdown layer 2-9 disposed on the substrate, two P-type electric field shielding regions 2-7 disposed on the breakdown layer and an N-type current path region 2-8 disposed between the two P-type electric field shielding regions, an unintentionally doped (UID) channel layer 2-5 disposed on the P-type electric field shielding region and the current path region, a barrier layer 2-4 disposed on the channel layer, a junction gate portion disposed on the barrier layer, a metal source 2-6, a first dielectric passivation layer 2-10, and a second dielectric passivation layer 2-11; characterized in that...

[0016] The junction gate portion is composed of a P-type wide bandgap semiconductor layer 2-1, a P-type polysilicon layer 2-3, and a metal gate 2-2 stacked sequentially from bottom to top. Specifically, the P-type wide bandgap semiconductor layer is disposed on the barrier layer 2-4, the P-type polysilicon layer is disposed on the P-type wide bandgap semiconductor layer, and the metal gate is disposed on the P-type polysilicon layer. The first dielectric passivation layer 2-10 covers the upper surface of the barrier layer (excluding the area of ​​the junction gate portion) and partially covers both sides of the P-type polysilicon layer 2-3. The second dielectric passivation layer 2-11 is located on the upper surface of the first dielectric passivation layer and covers the metal gate 2-2. The metal source 2-6 covers the second dielectric passivation layer and is in contact with the barrier layer 2-4, the channel layer 2-5, and the P-type electric field shielding region on both sides, respectively.

[0017] Furthermore, the P-type polysilicon layer forms a Schottky contact or an ohmic contact with the gate metal.

[0018] Furthermore, the P-type polysilicon layer adopts a two-layer structure consisting of a bottom lightly doped layer and a top heavily doped layer. The bottom lightly doped P-type semiconductor layer can prevent the reverse-biased PP junction from breaking down prematurely or the tunneling current from being too large, and the threshold voltage can be adjusted by changing the thickness. The top heavily doped P-type semiconductor layer is conducive to forming ohmic contacts, preventing carrier accumulation, and improving the stability of the threshold voltage.

[0019] Furthermore, the p-type wide bandgap semiconductor layer is p-type GaN, AlGaN, or NiO, with a doping concentration greater than 1e17cm⁻¹. -3 .

[0020] Furthermore, the substrate is made of heavily doped N-type GaN; the breakdown layer is made of lightly doped N-type GaN with a concentration between 1e14 and 1e17; the current path region is made of N-type GaN with a higher concentration than the breakdown layer; the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN; and the P-type electric field shielding layer and the channel layer are made of GaN.

[0021] The effective effects of this invention are as follows:

[0022] This invention provides a junction-gate enhancement-mode GaN device based on a PP heterojunction, comprising a lateral device and a vertical device. The enhancement-mode device is obtained by utilizing a P-type wide-bandgap semiconductor layer to deplete the high-concentration two-dimensional electron gas beneath it. Simultaneously, a P-type polysilicon layer is disposed on the P-type wide-bandgap semiconductor layer. The junction gate is formed by the P-type wide-bandgap semiconductor layer, the P-type polysilicon layer, and the gate metal. Since the PP heterojunction has almost no electron current, and the hole barrier formed by the P-type wide-bandgap semiconductor layer and the P-type polysilicon layer is very high, the holes within the P-type polysilicon require… A very high potential barrier is required to enter a P-type wide-bandgap semiconductor. Therefore, when a positive voltage is applied to the gate to open the channel in P-type polysilicon, holes on the P-type polysilicon side can hardly overcome the hole barrier to form a hole current. This results in extremely low gate current and extremely high gate voltage swing, reducing drive losses and the difficulty and complexity of drive circuit design. Furthermore, based on the above-mentioned novel junction gate, the influence of interface charge or traps between the dielectric layer (I) and semiconductor layer (S) in the MIS structure on the reliability and stability of the threshold voltage is avoided. Moreover, this invention can avoid the problems associated with traditional p-GaN. HEMTs use reverse-biased P-type Schottky junctions to prevent excessive gate leakage current from causing serious electrothermal stability problems. The PP heterojunction of this invention will also recover the gate leakage current after the electrothermal stress disappears, with no charge storage, thereby improving the reliability and stability of the device threshold voltage and gate leakage current. In summary, this invention, by introducing a novel junction gate structure, achieves an enhancement-mode device with extremely low gate drive current and extremely high gate voltage swing without using a recessed-gate structure or fluorine ion implantation. It has lower on-resistance, simpler process, higher consistency, lower cost, and higher stability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a cell in an existing p-GaN gate HEMT device.

[0024] Figure 2 This is a schematic diagram of a cell in an existing recessed-gate HEMT device.

[0025] Figure 3 This is a schematic diagram of an existing MIS gate CAVET structure cell.

[0026] Figure 4 This is a schematic diagram of the existing p-GaN gate CAVET structure cell.

[0027] Figure 5 This is a schematic diagram of the cell of the enhanced lateral GaN device in Embodiment 1 of the present invention;

[0028] Among them, 1-1 is a P-type wide bandgap semiconductor layer, 1-2 is a metal gate, 1-3 is a P-type polysilicon layer, 1-4 is a barrier layer, 1-5 is a channel layer, 1-6 is a source ohmic contact metal layer, 1-7 is a drain ohmic contact metal layer, 1-8 is a buffer layer, 1-9 is a substrate, 1-10 is a first dielectric passivation layer, 1-11 is a second dielectric passivation layer, 1-12 is a metal source, and 1-13 is a metal drain.

[0029] Figure 6 The diagram shows the transfer characteristic curve and gate current waveform of the enhanced lateral GaN device in Embodiment 1 of the present invention.

[0030] Figure 7 This is a schematic diagram of the energy band of the junction gate portion in the enhanced lateral GaN device of Embodiment 1 of the present invention.

[0031] Figure 8 This is a schematic diagram of the cell of the enhanced vertical GaN device in Embodiment 2 of the present invention;

[0032] Among them, 2-1 is a P-type wide bandgap semiconductor layer, 2-2 is a metal gate, 2-3 is a P-type polysilicon layer, 2-4 is a barrier layer, 2-5 is a UID channel layer, 2-6 is a metal source, 2-7 is a P-type electric field shielding region, 2-8 is an N-type current path region, 2-9 is a withstand voltage layer, 2-10 is a first dielectric passivation layer, 2-11 is a second dielectric passivation layer, 2-12 is a substrate, and 2-13 is a metal drain. Detailed Implementation

[0033] To make the objectives, technical solutions, and technical effects of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0034] Example 1

[0035] This embodiment provides a junction-gate enhancement-mode lateral GaN device with the following cell structure: Figure 5 As shown, it specifically includes:

[0036] Substrate 1-9, buffer layer 1-8 disposed on the substrate, channel layer 1-5 disposed on the buffer layer, barrier layer 1-4 disposed on the channel layer, source ohmic contact metal layer 1-6, drain ohmic contact metal layer 1-7 and junction gate portion disposed on barrier layer 1-4, and first dielectric passivation layer 1-10 and second dielectric passivation layer 1-11;

[0037] A metal source 1-12 is disposed on the source ohmic contact metal layer 1-6, and a metal drain 1-13 is disposed on the drain ohmic contact metal layer 1-7. The junction gate portion is located between the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7, and is disposed adjacent to the source ohmic contact metal layer 1-6. The junction gate portion is composed of a P-type wide bandgap semiconductor layer 1-1, a P-type polysilicon layer 1-3, and a metal gate 1-2 stacked sequentially from bottom to top, i.e., P-type wide bandgap semiconductor layer 1-1, P-type polysilicon layer 1-3, and metal gate 1-2. A bandgap semiconductor layer is disposed on the barrier layer 1-4, a P-type polysilicon layer is disposed on the P-type wide bandgap semiconductor layer, and a metal gate is disposed on the P-type polysilicon layer; the first dielectric passivation layer 1-10 is located on the upper surface of the barrier layer (excluding the area of ​​the source ohmic contact layer 1-6, the drain ohmic contact layer 1-7 and the junction gate portion) and partially covers both sides of the P-type polysilicon layer 1-3; the second dielectric passivation layer 1-11 is located on the upper surface of the first passivation layer and covers the metal gate 1-2.

[0038] Furthermore, the gate metal 1-2 extends to both sides of the P-type polysilicon layer 1-3 to form a gate field plate, which is located on the upper surface of the first dielectric passivation layer 1-10; the source metal 1-12 extends to the drain metal 1-13 to form a source field plate, which is located on the upper surface of the second dielectric passivation layer 1-11 and covers the junction gate portion; the drain metal 1-13 extends to the source metal 1-12 to form a drain field plate, which is located on the upper surface of the second dielectric passivation layer 1-11.

[0039] Furthermore, in this embodiment, the substrate is P-type Si, the buffer layer is C-doped GaN, the channel layer is 400nm UID-GaN, the barrier layer is AlGaN with a molar composition of 0.2 and a thickness of 10nm, and the P-type wide bandgap semiconductor layer has an effective hole concentration of approximately 1×10⁻⁶. 18 cm -3 The p-GaN has a 50 nm thick p-type polysilicon layer with a doping concentration of 5e17 cm⁻¹. -3 The gate-source spacing and gate-drain spacing are 1.5um and 13.5um, respectively. The gate length is 2um. The metal gate and the P-type polysilicon layer are set as Schottky contacts. The first passivation layer is 100nm SiN and the second passivation layer is 50nm SiO2.

[0040] Based on the above parameters, the transfer characteristic curve and gate current waveform of the junction-gate enhancement-mode lateral GaN device in this embodiment are as follows: Figure 6 As shown in the figure, the device first achieves enhancement-mode characteristics with a threshold voltage of approximately 1.5V. More importantly, the device V GSAt 10V, the gate current density is only on the order of nA / mm², compared to traditional p-GaN HEMTs (Jiang, Huaxing, et al. "High-voltage p-GaN HEMTs with off-state blocking capability after gate breakdown." IEEE Electron Device Letters, vol.40, no.4, 2019, pp.530-533). GS =6V, the mA / mm level decreased by ~10 5 The gate current is orders of magnitude higher than that of conventional p-GaN HEMTs. Because the gate current of traditional p-GaN HEMTs is too large, their gate voltage generally needs to be limited to below 6V. This invention, however, can maintain an extremely low gate current even when the gate voltage is increased to 10V or higher. This reduces the design complexity of the drive circuit, lowers the requirements for gate overvoltage protection, and reduces the power consumption of the drive circuit.

[0041] In terms of working principle: such as Figure 7 The diagram shows the energy band structure of the junction gate in this embodiment. As can be seen from the figure, although all doping is P-type, the very high hole barrier formed at the P-type polysilicon / p-GaN heterojunction interface prevents holes in the P-type polysilicon from entering the p-GaN when the gate is forward biased. This results in extremely low current and extremely high gate voltage swing when a positive voltage is applied to the gate metal on the P-type polysilicon to open the gate channel. The simulation test results also confirm this principle. Furthermore, the device exhibits similar effects when the p-GaN in the P-type wide bandgap semiconductor layer 1-1 is replaced with p-AlGaN or p-NiO. The first dielectric passivation layer is used to passivate the device surface. The traps between it and the barrier layer provide a two-dimensional electron gas source and are used to form a gate field plate with the gate metal, increasing the breakdown voltage and suppressing current collapse. The second dielectric passivation layer is used to passivate the device surface and forms a source-drain field plate with the source-drain metal, increasing the breakdown voltage and suppressing current collapse.

[0042] Additionally, it should be noted that in all the above embodiments, when the substrate is replaced with SiC or sapphire, the buffer layer is replaced with high-resistivity AlGaN, the channel layer is replaced with InGaN, and the barrier layer is replaced with GaN / AlGaN, AlGaN / AlN, or InAlN, the same effects are achieved.

[0043] Example 2

[0044] This embodiment provides a junction-gate enhancement-mode vertical GaN device, the structure of which is as follows: Figure 8 As shown, it specifically includes:

[0045] Substrate 2-12, metal drain 2-13 disposed under the substrate, voltage withstand layer 2-9 disposed on the substrate, two P-type electric field shielding regions 2-7 disposed on the voltage withstand layer and an N-type current path region 2-8 disposed between the two P-type electric field shielding regions, unintentionally doped (UID) channel layer 2-5 disposed on the P-type electric field shielding region and the current path region, barrier layer 2-4 disposed on the channel layer, junction gate portion disposed on the barrier layer, metal source 2-6, first dielectric passivation layer 2-10 and second dielectric passivation layer 2-11;

[0046] The junction gate portion is composed of a P-type wide bandgap semiconductor layer 2-1, a P-type polysilicon layer 2-3, and a metal gate 2-2 stacked sequentially from bottom to top. Specifically, the P-type wide bandgap semiconductor layer is disposed on the barrier layer 2-4, the P-type polysilicon layer is disposed on the P-type wide bandgap semiconductor layer, and the metal gate is disposed on the P-type polysilicon layer. The first passivation layer 2-10 covers the upper surface of the barrier layer (excluding the area of ​​the junction gate portion) and partially covers both sides of the P-type polysilicon layer 2-3. The second dielectric passivation layer 2-11 is located on the upper surface of the first dielectric passivation layer and covers the metal gate 2-2. The metal source 2-6 covers the second dielectric passivation layer and is in contact with the barrier layer 2-4, the channel layer 2-5, and the P-type electric field shielding region on both sides, respectively.

[0047] Furthermore, in this embodiment, the substrate is made of heavily doped N-type GaN, and the breakdown layer is made of lightly doped N-type GaN, typically with a concentration of 1e14 to 1e17 cm⁻¹. -3 Between these layers, the current path region is made of N-type GaN with a higher concentration than the breakdown voltage layer; the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN, and the molar composition of Al in AlGaN or the molar composition of InAlN should be adaptively designed according to application requirements; the P-type wide bandgap semiconductor layer is made of P-type GaN, AlGaN, or NiO with a concentration greater than 1e17cm⁻¹. -3 The molar composition of Al in P-type AlGaN is generally between 0 and 0.35 depending on different requirements. The thickness of the P-type wide bandgap semiconductor layer should be adaptively designed according to the application requirements.

[0048] In terms of working principle: the junction gate section in this embodiment is the same as that in embodiment 1, the gate control principle is similar to that in embodiment 1, and its transfer characteristic curve, gate current, and energy band diagram are also similar to those in embodiment 1, with the same characteristics and beneficial effects.

[0049] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A junction-gate enhancement-mode GaN device based on a PP heterojunction, comprising: The substrate (1-9), a buffer layer (1-8) disposed on the substrate, an unintentionally doped channel layer (1-5) disposed on the buffer layer, a barrier layer (1-4) disposed on the channel layer, a source ohmic contact metal layer (1-6), a drain ohmic contact metal layer (1-7), and a junction gate portion disposed on the barrier layer, and a first dielectric passivation layer (1-10) and a second dielectric passivation layer (1-11); characterized in that, A metal source is disposed on the source ohmic contact metal layer, a metal drain is disposed on the drain ohmic contact metal layer, and a junction gate is disposed between the source ohmic contact metal layer and the drain ohmic contact metal layer and adjacent to the source ohmic contact metal layer; the junction gate is composed of a P-type wide bandgap semiconductor layer (1-1), a P-type polysilicon layer (1-3), and a metal gate (1-2) stacked sequentially from bottom to top, and the P-type wide bandgap semiconductor layer and the P-type polysilicon layer form a PP heterojunction hole barrier; the first dielectric passivation layer is located on the upper surface of the barrier layer and partially covers both sides of the P-type polysilicon layer, and the second dielectric passivation layer is located on the upper surface of the first dielectric passivation layer and covers the metal gate.

2. The junction-gate enhancement-mode GaN device based on a PP heterojunction as described in claim 1, characterized in that, The gate metal extends to both sides of the P-type polysilicon layer to form a gate field plate, which is located on the upper surface of the first dielectric passivation layer; the source metal extends to the drain metal side to form a source field plate, which is located on the upper surface of the second dielectric passivation layer and covers the junction gate portion; the drain metal extends to the source metal side to form a drain field plate, which is located on the upper surface of the second dielectric passivation layer.

3. A junction-gate enhancement-mode GaN device based on a PP heterojunction, comprising: The substrate (2-12), the metal drain (2-13) disposed under the substrate, the voltage withstand layer (2-9) disposed on the substrate, the two P-type electric field shielding regions (2-7) disposed on the voltage withstand layer and the N-type current path region (2-8) disposed between the two P-type electric field shielding regions, the unintentionally doped channel layer (2-5) disposed on the P-type electric field shielding region and the current path region, the barrier layer (2-4) disposed on the channel layer, the junction gate portion disposed on the barrier layer, and the metal source (2-6), the first dielectric passivation layer (2-10) and the second dielectric passivation layer (2-11); characterized in that, The junction gate portion is composed of a P-type wide bandgap semiconductor layer (2-1), a P-type polysilicon layer (2-3), and a metal gate (2-2) stacked sequentially from bottom to top. The P-type wide bandgap semiconductor layer and the P-type polysilicon layer form a PP heterojunction hole barrier. The first dielectric passivation layer covers the upper surface of the barrier layer and partially covers both sides of the P-type polysilicon layer. The second dielectric passivation layer is located on the upper surface of the first dielectric passivation layer and covers the metal gate. The metal source electrode covers the second dielectric passivation layer and is in contact with the barrier layer, the channel layer, and the P-type electric field shielding region on both sides, respectively.

4. The junction-gate enhancement-mode GaN device based on a PP heterojunction as described in claim 1 or 3, characterized in that, The P-type polysilicon layer forms a Schottky contact or an ohmic contact with the gate metal.

5. The junction-gate enhancement-mode GaN device based on a PP heterojunction as described in claim 1 or 3, characterized in that, The P-type polycrystalline silicon layer adopts a two-layer structure consisting of a bottom lightly doped layer and a top heavily doped layer.

6. The junction-gate enhancement-mode GaN device based on a PP heterojunction as described in claim 1 or 3, characterized in that, The p-type wide bandgap semiconductor layer is p-type GaN, AlGaN, or NiO, with a doping concentration greater than 1e17 cm⁻¹. -3 .

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