A pn-junction based junction gate enhancement-mode gan device

Abstract

This invention belongs to the field of power semiconductor technology and provides a junction-gate enhancement-mode GaN device based on a PN junction to solve many problems existing in current devices, such as narrow gate voltage swing, large gate leakage current, high process requirements, high specific on-resistance, high cost, and poor electrothermal stability. This invention utilizes a wide-bandgap P-type semiconductor to deplete the high-concentration two-dimensional electron gas beneath it to obtain an enhancement-mode device. Simultaneously, a reverse-biased N-type semiconductor is placed on the wide-bandgap P-type semiconductor to form a junction gate, preventing current injection from the gate into the wide-bandgap P-type semiconductor layer, thereby achieving extremely low gate leakage current. Furthermore, by simultaneously introducing N-type semiconductors into the source and drain channel regions to form a double-layer barrier structure, the two-dimensional electron gas density in the source and drain channel regions is increased. Ultimately, the enhancement-mode GaN device of this invention possesses advantages such as large gate voltage swing, low gate leakage current, low channel specific on-resistance, high threshold voltage consistency, simple process, low cost, and high stability.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to high voltage semiconductor devices, specifically providing a junction gate enhancement GaN device based on a PN junction. Background Technology

[0002] As a third-generation semiconductor device, GaN devices are well-suited for high-frequency and high-power applications due to their inherent physical properties. Enhanced GaN devices can eliminate the need for protection circuits and improve system reliability in power electronics applications, making them a key research focus.

[0003] Traditional enhancement-mode lateral GaN devices mainly include p-GaN gate or p-AlGaN gate enhancement-mode HEMT devices, recess-gate HEMTs, and HEMTs using fluorine ion implantation. Among them, p-GaN gate or p-AlGaN gate enhancement-mode HEMT devices utilize p-GaN or p-AlGaN to deplete the two-dimensional electron gas at the channel, as described in the literature "Y. Uemoto et al., "Gate injection transistor (GIT) — A normally-off AlGaN / GaN power transistor using conductivity modulation," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3393–3399, Dec. 2007.", with the following structure... Figure 1As shown; however, the PN diode formed by p-GaN or p-AlGaN and the barrier layer will conduct at a gate voltage of ~3V, thereby introducing a large gate current and increasing drive losses. The above characteristics limit the gate voltage swing, generally not exceeding 5V, thus increasing the difficulty of drive circuit design; and the p-GaN gate and metal gate electrode generally form a reverse-biased Schottky contact to reduce the gate current, but the Schottky contact has low reliability and stability, resulting in low reliability and stability of gate leakage. Recessed-gate HEMT is constructed by etching away a portion of the barrier layer under the gate dielectric (remaining thickness d), as described in the literature "Y. Zhao, et al., "Effects of recess depths on performance of AlGaN / GaN power MIS-HEMTs on the Si substrates and threshold voltage model of different recess depths for the using HfO2 gate insulator," Solid-State Electronics, 2020, 163:107649.", its structure is as follows. Figure 2 As shown, this structure can reduce the two-dimensional electron gas concentration at the channel, thereby realizing an enhancement-mode device. However, the reduction in channel polarization increases the specific on-resistance. Furthermore, the threshold voltage of this device increases with decreasing thickness of the barrier layer retained under the channel gate dielectric, typically around 1V-2V. Moreover, when the retained barrier layer is thinned to a few nm, the electron mobility within the channel decreases drastically due to channel disruption, leading to a multiple increase in specific on-resistance. Additionally, the thickness d retained through etching is very difficult to control precisely, significantly affecting the uniformity of the threshold voltage on the wafer. An enhancement-mode device can also be realized using a MIS-HEMT structure implanted with fluorine ions under the gate channel, but the scattering introduced by F ions reduces electron mobility, increases device resistance, and also presents thermal stability issues.

[0004] To overcome the above problems, the applicant disclosed a structure with a MIS gate in patent document application number 202210146339.7 entitled "An Enhanced MIS-GaN Device"; however, the introduction of this MIS structure will bring high dielectric (I) / semiconductor (S) interface charge or traps, thereby affecting the threshold voltage stability and reliability. Summary of the Invention

[0005] The purpose of this invention is to address the numerous problems existing in the above-mentioned enhancement-mode GaN devices, such as poor threshold voltage consistency, poor stability and reliability, channel damage, low two-dimensional electron gas concentration, high channel resistance, narrow gate voltage swing, large gate leakage current, high process difficulty, and complex drive design, and to provide a junction-gate enhancement-mode GaN device based on a PN junction. This invention has the advantages of large gate voltage swing, low gate leakage current, low channel resistance, high two-dimensional electron gas concentration in the source-drain channel region, low overall on-resistance, high threshold voltage consistency, high electrothermal stability, high reliability, and simple process.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] 1. A junction-gate enhancement GaN device based on a PN junction, comprising: a P-type wide bandgap semiconductor layer 1-1, a metal gate 1-2, a first N-type semiconductor layer 1-3, a barrier layer 1-4, a channel layer 1-5, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, a buffer layer 1-8, a substrate 1-9, a first dielectric passivation layer 1-10, a second dielectric passivation layer 1-11, a metal source 1-12, and a metal drain 1-13, wherein the buffer layer 1-8 is disposed on the substrate, the channel layer 1-5 is disposed on the buffer layer, the barrier layer 1-4 is disposed on the channel layer, the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7 are disposed on the barrier layer 1-4 and are respectively located at both ends, the metal source 1-12 is disposed on the source ohmic contact metal layer 1-6, and the metal drain 1-13 is disposed on the drain ohmic contact metal layer 1-7;

[0008] The key feature is that a P-type wide bandgap semiconductor layer 1-1, a first N-type semiconductor layer 1-3, and a metal gate 1-2 are stacked sequentially from bottom to top to form a junction gate portion. The junction gate portion is located between the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7, and adjacent to the side of the source ohmic contact layer. A first dielectric passivation layer 1-10 covers the upper surface of the barrier layer and a portion of both sides of the first N-type semiconductor layer 1-3, and a second dielectric passivation layer 1-11 covers the first dielectric passivation layer and the upper surface of the metal gate 1-2.

[0009] 2. A junction-gate enhancement GaN device based on a PN junction, comprising: a P-type wide bandgap semiconductor layer 1-1, a metal gate 1-2, a first N-type semiconductor layer 1-3, a barrier layer 1-4, a channel layer 1-5, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, a buffer layer 1-8, a substrate 1-9, a first dielectric passivation layer 1-10, a second dielectric passivation layer 1-11, a metal source 1-12, a metal drain 1-13, a second N-type semiconductor layer 1-14, and a third N-type semiconductor layer 1-15, wherein the buffer layer 1-8 is disposed on the substrate, the channel layer 1-5 is disposed on the buffer layer, and the barrier layer 1-4 is disposed on the channel layer;

[0010] The key feature is that a P-type wide bandgap semiconductor layer 1-1, a first N-type semiconductor layer 1-3, and a metal gate 1-2 are stacked sequentially from bottom to top to form a junction gate portion; a second N-type semiconductor layer 1-14, the junction gate portion, and a third N-type semiconductor layer 1-15 are disposed on a barrier layer 1-4; a source ohmic contact metal layer 1-6 is disposed on the second N-type semiconductor layer 1-14, and a drain ohmic contact metal layer 1-7 is disposed on the third N-type semiconductor layer 1-15; the junction gate portion is located between the second N-type semiconductor layer and the third N-type semiconductor layer and adjacent to the source ohmic contact metal layer. On one side of 1-6; a metal source electrode 1-12 is disposed on the source ohmic contact layer 1-6, and a metal drain electrode 1-13 is disposed on the drain ohmic contact layer 1-7; a first dielectric passivation layer 1-10 covers the upper surfaces of the second N-type semiconductor layer and the third N-type semiconductor layer, the barrier layer between the second N-type semiconductor layer and the junction gate portion, the barrier layer between the third N-type semiconductor layer and the junction gate portion, and the two side portions of the P-type wide bandgap semiconductor layer 1-1 and the first N-type semiconductor layer 1-3; a second dielectric passivation layer 1-11 covers the first dielectric passivation layer and the upper surface of the metal gate 1-2.

[0011] 3. A junction-gate enhancement GaN device based on a PN junction, comprising: a P-type wide bandgap semiconductor layer 2-1, a metal gate 2-2, an N-type semiconductor layer 2-3, a barrier layer 2-4, a channel layer 2-5, a metal source 2-6, a P-type electric field shielding region 2-7, an N-type current path region 2-8, a voltage withstand layer 2-9, a first dielectric passivation layer 2-10, a second dielectric passivation layer 2-11, a substrate 2-12, and a metal drain 2-13, wherein the metal drain 2-13 is disposed under the substrate, the voltage withstand layer 2-9 is disposed on the substrate, two P-type electric field shielding regions 2-7 and a current path region 2-8 located between the two P-type electric field shielding regions are disposed on the voltage withstand layer, an unintentionally doped (UID) channel layer 2-5 is disposed on the P-type electric field shielding region and the current path region, and the barrier layer 2-4 is disposed on the channel layer;

[0012] The key feature is that a P-type wide bandgap semiconductor layer 2-1, an N-type semiconductor layer 2-3, and a metal gate 2-2 are stacked sequentially from bottom to top to form a junction gate portion, which is disposed on a barrier layer; a first dielectric passivation layer 2-10 covers the upper surface of the barrier layer and the two side regions of the N-type semiconductor layer 2-3; a second dielectric passivation layer 2-11 covers the first dielectric passivation layer and the upper surface of the metal gate 2-2; and a metal source 2-6 covers the upper surface of the second dielectric passivation layer and is in contact with the barrier layer 2-4, the channel layer 2-5, and the P-type electric field shielding region on both sides, respectively.

[0013] Furthermore, in the first and second types of GaN devices described above, the gate metal 1-2 extends to both sides of the first N-type semiconductor layer 1-3 to form a gate field plate, and the gate field plate covers the upper surface of the first dielectric passivation layer 1-10; the source metal 1-12 and the drain metal 1-13 extend to the channel region between the gate and drain to form a source field plate and a drain field plate, respectively, and the source field plate and the drain field plate cover the upper surface of the second dielectric passivation layer 1-11.

[0014] Furthermore, in the first, second, and third types of GaN devices described above, the first N-type semiconductor layer forms a Schottky contact or an ohmic contact with the gate metal.

[0015] Furthermore, in the first and third types of GaN devices mentioned above, the N-type semiconductor layer (including: the first N-type semiconductor layer in the first type of GaN device and the N-type semiconductor layer in the third type of GaN device) is made of N-type GaN, AlGaN, InGaN, InAlN, AlN, or polycrystalline silicon, and the molar composition of Al in AlGaN or InAlN and InGaN in InGaN is adaptively adjusted according to design requirements.

[0016] Furthermore, in the second type of GaN device described above, the first to third N-type semiconductor layers are made of N-type AlGaN, InAlN, or AlN with high polarization intensity.

[0017] Furthermore, in the aforementioned GaN devices of types 1, 2, and 3, the N-type semiconductor layer (including: the first N-type semiconductor layer in the first GaN device, the first to third N-type semiconductor layers in the second GaN device, and the N-type semiconductor layer in the third GaN device) consists of a lightly doped or undoped N-type semiconductor layer at the bottom (doping concentration less than 1e18 cm⁻¹). -3 A heavily doped N-type semiconductor layer of the same material as the top layer (doping concentration higher than 1e18 cm⁻¹) -3The structure consists of a bottom lightly doped N-type semiconductor layer, which can prevent the reverse-biased PN junction from breaking down prematurely or the tunneling current from being too large, and the threshold voltage can be adjusted by changing the thickness. The top heavily doped N-type semiconductor layer is conducive to forming ohmic contacts, preventing carrier accumulation, and improving the stability of the threshold voltage.

[0018] Furthermore, in the aforementioned GaN devices of types 1, 2, and 3, the N-type semiconductor layer (including: the first N-type semiconductor layer in the first GaN device, the first to third N-type semiconductor layers in the second GaN device, and the N-type semiconductor layer in the third GaN device) consists of a lightly doped or undoped N-type semiconductor layer at the bottom (doping concentration less than 1e18 cm⁻¹). -3 ) with another lightly doped material on top (doping concentration less than 1e18 cm⁻¹) -3 or heavily doped N-type semiconductor layer (doping concentration higher than 1e18 cm⁻¹) -3 The structure consists of a bottom lightly doped N-type semiconductor layer that can prevent premature breakdown of the reverse-biased PN junction or excessive tunneling current, and the threshold voltage can be adjusted by changing the thickness. The top lightly doped layer forms a Schottky contact with the metal gate, while the heavily doped N-type semiconductor layer is conducive to forming an ohmic contact, preventing carrier accumulation, and improving threshold voltage stability.

[0019] Furthermore, in the first and second types of GaN devices described above, the substrate is made of Si, SiC, or sapphire; the buffer layer is made of C-doped or Fe-doped high-resistivity GaN or AlGaN; the channel layer is made of unintentionally doped GaN or InGaN; the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN; and the P-type wide bandgap semiconductor layer is made of P-type GaN, AlGaN, or NiO, with a doping concentration greater than 1e17 cm⁻¹. -3 .

[0020] Furthermore, in the third type of GaN device described above, the substrate is made of heavily doped N-type GaN; the breakdown layer is made of lightly doped N-type GaN with a concentration between 1e14 and 1e17; the current path region is made of N-type GaN with a higher concentration than the breakdown layer; the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN; the P-type electric field shielding layer and the channel layer are made of GaN; and the P-type wide bandgap semiconductor layer is P-type GaN, AlGaN, or NiO with a doping concentration greater than 1e17 cm⁻¹. -3 .

[0021] In addition, the present invention also provides a method for fabricating the second type of GaN device, comprising the following steps:

[0022] Step 1. Grow a buffer layer, a channel layer, and a barrier layer sequentially on the substrate;

[0023] Step 2. A P-type wide bandgap semiconductor thin film is grown on the barrier layer using an epitaxial growth process. After photolithography, the P-type wide bandgap semiconductor layer is formed by dry etching using ICP, IRE, or ICP-RIE.

[0024] Step 3. An N-type semiconductor thin film is grown using epitaxial growth technology to cover the entire device surface. After photolithography, patterned first, second, and third N-type semiconductor layers are formed by dry etching using ICP, IRE, or ICP-RIE. The first N-type semiconductor layer is located on the P-type wide bandgap semiconductor layer, and its two end boundaries are located within the boundaries of the P-type wide bandgap semiconductor layer. The second and third N-type semiconductor layers are located on both sides of the P-type wide bandgap semiconductor layer and are not in contact with it.

[0025] Step 4. After photolithography, a metal layer is formed on the device surface using evaporation or magnetron sputtering. Then, a lift-off process is used to form the source ohmic contact layer and the drain ohmic contact layer, respectively. Finally, rapid thermal annealing is performed in N2.

[0026] Step 5. Use ALD or CVD process to grow a first dielectric passivation layer covering the entire device surface. After photolithography, use ICP, RIE, ICP-RIE dry etching or wet etching of the first dielectric passivation layer to form a gate metal contact hole above the first N-type semiconductor layer.

[0027] Step 6. After photolithography, a metal layer is formed on the device surface using evaporation or sputtering processes, and then a lift-off process is used to form the gate metal and the gate field plate.

[0028] Step 7. Use ALD or CVD process to grow a second dielectric passivation layer to cover the entire device surface. After photolithography, use ICP, RIE or ICP-RIE dry etching to form source metal contact holes and drain metal contact holes above the source ohmic contact layer and drain ohmic contact layer, respectively.

[0029] Step 8. After photolithography, an evaporation or sputtering process is used to form a metal layer covering the entire device surface. Then, a lift-off process is used to form the source metal and source field plate, and the drain metal and drain field plate. Alternatively, ICP, RIE, ICP-RIE dry etching or wet etching is used to form the source metal and source field plate, and the drain metal and drain field plate.

[0030] The effective effects of this invention are as follows:

[0031] This invention provides a junction-gate enhancement-mode GaN device based on a PN junction, comprising a lateral device and a vertical device. It utilizes a P-type wide-bandgap semiconductor layer to deplete the high-concentration two-dimensional electron gas beneath it, thus obtaining an enhancement-mode device. Simultaneously, a first N-type semiconductor layer is disposed on the P-type wide-bandgap semiconductor layer. The P-type wide-bandgap semiconductor layer, the first N-type semiconductor layer, and the gate metal together constitute a junction gate. When a positive voltage is applied to the gate metal on the N-type semiconductor layer to open the gate channel, the PN junction formed by the P-type wide-bandgap semiconductor layer and the N-type semiconductor layer is reverse-biased, and the gate current is determined by the reverse-biased PN junction. Therefore, regardless of whether the N-type semiconductor layer and the gate metal form a forward-biased N-type Schottky diode or an ohmic contact, the current generated when a positive voltage is applied to the gate metal on the N-type semiconductor layer to open the gate channel is extremely low, and the gate voltage swing is extremely high, which can reduce drive losses and the difficulty and complexity of drive circuit design.

[0032] Furthermore, this invention introduces a second N-type semiconductor layer and a third N-type semiconductor layer formed synchronously with the first N-type semiconductor layer. The second and third N-type semiconductor layers form a double-layer barrier structure in the channel region between the gate-source and gate-drain regions, respectively. That is, barrier layers 1-4 serve as the first barrier layer, and the second and third N-type semiconductor layers serve as the second barrier layer. Without increasing the process difficulty and cost, the total thickness of the barrier layer is effectively increased. At the same time, adjusting the molar composition of AlGaN or InAlN in the second barrier layer can enhance its polarization intensity, or a higher two-dimensional electron gas concentration can be obtained by utilizing a strongly polarized AlN layer. Furthermore, the barrier layer at the gate remains unchanged, without affecting the two-dimensional electron gas concentration below the gate. While ensuring normal gate depletion, the specific on-resistance of the source-drain channel region is greatly reduced.

[0033] Furthermore, the novel junction gate of this invention can avoid the influence of interface charge or traps between the dielectric layer (I) and semiconductor layer (S) in the MIS structure on the reliability and stability of the threshold voltage, and avoid the problems of serious electrothermal stability (including threshold voltage drift, increased gate leakage, etc.) caused by the use of reverse-biased P-type Schottky junctions in traditional p-GaN HEMTs to prevent excessive gate leakage. After the electrothermal stress disappears, the gate leakage current of the reverse-biased PN junction of this invention will also recover, and no charge will be stored in the junction gate, thereby improving the reliability and stability of the device threshold voltage and gate leakage.

[0034] In summary, this invention introduces a novel junction gate structure, achieving an enhancement-mode device with extremely low gate drive current and extremely high gate voltage swing without employing a recessed-gate structure or fluorine ion implantation. It features low on-resistance, simple fabrication process, high consistency, low cost, and high stability. Attached Figure Description

[0035] Figure 1This is a schematic diagram of a cell in an existing p-GaN gate HEMT device.

[0036] Figure 2 This is a schematic diagram of a cell in an existing recessed-gate HEMT device.

[0037] Figure 3 This is a schematic diagram of the cell of the enhanced lateral GaN device in Embodiment 1 of the present invention; wherein, 1-1 is a P-type wide bandgap semiconductor layer, 1-2 is a metal gate, 1-3 is a first N-type semiconductor layer, 1-4 is a barrier layer, 1-5 is a channel layer, 1-6 is a source ohmic contact metal layer, 1-7 is a drain ohmic contact metal layer, 1-8 is a buffer layer, 1-9 is a substrate, 1-10 is a first dielectric passivation layer, 1-11 is a second dielectric passivation layer; 1-12 is a metal source, and 1-13 is a metal drain.

[0038] Figures 4-9 The diagram shows the transfer characteristic curve and gate current waveform of the enhanced lateral GaN device in Embodiment 1 of the present invention.

[0039] Figure 10 This is a schematic diagram of the cell of the enhanced lateral GaN device in Embodiment 2 of the present invention; wherein, 1-14 are the second N-type semiconductor layer and 1-15 are the third N-type semiconductor layer.

[0040] Figure 11 , Figure 12 This is a comparison chart of the transfer characteristic curves and gate current waveforms of the enhanced lateral GaN device in Embodiment 2 of the present invention and the comparative example.

[0041] Figure 13 This is a comparison chart of the transfer characteristic curves and gate current waveforms of the enhanced lateral GaN device in Embodiment 3 of the present invention and the comparative example.

[0042] Figure 14 This is a process flow diagram of the fabrication of the enhanced lateral GaN device in Embodiment 4 of the present invention.

[0043] Figure 15 This is a schematic diagram of the cell of the enhanced vertical GaN device in Embodiment 5 of the present invention; wherein, 2-1 is a P-type wide bandgap semiconductor layer, 2-2 is a metal gate, 2-3 is a first N-type semiconductor layer, 2-4 is a barrier layer, 2-5 is a UID channel layer, 2-6 is a metal source, 2-7 is a P-type electric field shielding region, 2-8 is an N-type current path region, 2-9 is a withstand voltage layer, 2-10 is a first dielectric passivation layer, 2-11 is a second dielectric passivation layer, 2-12 is a substrate, and 2-13 is a metal drain. Detailed Implementation

[0044] To make the objectives, technical solutions, and technical effects of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0045] Example 1

[0046] This embodiment provides a junction-gate enhancement-mode lateral GaN device, the structure of which is as follows: Figure 3 As shown, it includes: a P-type wide bandgap semiconductor layer 1-1, a metal gate 1-2, a first N-type semiconductor layer 1-3, a barrier layer 1-4, a channel layer 1-5, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, a buffer layer 1-8, a substrate 1-9, a first dielectric passivation layer 1-10, a second dielectric passivation layer 1-11, a metal source 1-12, and a metal drain 1-13. The buffer layer 1-8 is disposed on the substrate, the channel layer 1-5 is disposed on the buffer layer, the barrier layer 1-4 is disposed on the channel layer, the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7 are disposed on the barrier layer 1-4 and located at opposite ends, the metal source 1-12 is disposed on the source ohmic contact metal layer 1-6, and the metal drain 1-13 is disposed on the drain ohmic contact metal layer 1-7.

[0047] The P-type wide bandgap semiconductor layer 1-1, the first N-type semiconductor layer 1-3, and the metal gate 1-2 are stacked sequentially from bottom to top to form a junction gate portion. The junction gate portion is located between the source ohmic contact metal layer 1-6 and the drain ohmic contact metal layer 1-7, and adjacent to the side of the source ohmic contact metal layer. The first dielectric passivation layer 1-10 covers the upper surface of the barrier layer (excluding the area of ​​the source ohmic contact layer 1-6, the drain ohmic contact layer 1-7, and the junction gate portion) and part of the area on both sides of the first N-type semiconductor layer 1-3. The second dielectric passivation layer 1-11 covers the first dielectric passivation layer and the upper surface of the metal gate 1-2.

[0048] Furthermore, the gate metal 1-2 extends to both sides of the first N-type semiconductor layer 1-3 to form a gate field plate, and the gate field plate covers the upper surface of the first dielectric passivation layer 1-10; the source metal 1-12 and the drain metal 1-13 extend to the channel region between the gate and drain to form a source field plate and a drain field plate respectively, and the source field plate and the drain field plate cover the upper surface of the second dielectric passivation layer 1-11.

[0049] Furthermore, in this embodiment, the substrate is P-type Si, the buffer layer is C-doped GaN, the channel layer is 400nm UID-GaN, the barrier layer is AlGaN with a molar composition of 0.2 and a thickness of 10nm, and the P-type wide bandgap semiconductor layer has an effective hole concentration of approximately 1×10⁻⁶. 18 cm -3The p-GaN has an N-type semiconductor layer with a thickness of 25 nm and is doped with 1×10⁻⁶ N-type GaN. 17 cm -3 The gate-source pitch and gate-drain pitch are 1.5µm and 13.5µm, respectively. The gate length is 2µm. The contact between the gate metal and the N-type GaN layer is set as a Schottky contact. The first dielectric passivation layer is 100nm SiN and the second dielectric passivation layer is 50nm SiO2.

[0050] Based on the above parameters, the transfer characteristic curve and gate current waveform of the junction-gate enhancement-mode lateral GaN device in this embodiment are as follows: Figure 4 As shown in the figure, the device first achieves enhancement-mode characteristics with a threshold voltage of approximately 1.5V; more importantly, the device V GS At 10V, the gate current density is only on the order of nA / mm², compared to traditional p-GaN HEMTs (Jiang, Huaxing, et al. "High-voltage p-GaN HEMTs with off-state blocking capability after gate breakdown." IEEE Electron Device Letters, vol.40, no.4, 2019, pp.530-533). GS =6V, the mA / mm level decreased by ~10 5 The gate current of traditional p-GaN HEMT is too large, so its gate voltage generally needs to be limited to below 6V. However, this invention can obviously maintain an extremely low gate current even when the gate voltage is increased to 10V or even higher, thereby reducing the design difficulty of the drive circuit, reducing the gate voltage overvoltage protection requirements, and reducing the power consumption of the drive circuit.

[0051] In terms of working principle: In the aforementioned novel junction gate structure, when a positive voltage is applied to the gate metal on the N-type semiconductor layer to open the gate channel, the PN junction formed by the P-type wide-bandgap semiconductor layer and the N-type semiconductor layer is reverse-biased. The gate leakage current is determined only by the leakage current of the reverse-biased PN junction. Therefore, regardless of whether the N-type semiconductor layer and the gate metal form a forward-biased N-type Schottky diode or an ohmic contact, the current formed when a positive voltage is applied to the gate metal on the N-type semiconductor layer to open the gate channel is extremely low, and the gate voltage swing is extremely high. The simulation test results also confirm this principle, thereby effectively reducing drive losses and the difficulty and complexity of drive circuit design. The first dielectric passivation layer is used to passivate the device surface. The traps between it and the barrier layer provide a two-dimensional electron gas source and are used to form a gate field plate with the gate metal, improving the breakdown voltage and suppressing current collapse. The second dielectric passivation layer is used to passivate the device surface and forms a source-drain field plate with the source-drain metal, improving the breakdown voltage and suppressing current collapse.

[0052] Additionally, when N-type semiconductor layers 1-3 are sequentially replaced with 25nm n-Al... 0.25 Ga 0.75 For N, 50nm N-type polysilicon, 25nm N-type AlN, and 25nm N-type InGaN, the device transfer characteristic curves and gate current waveforms are as follows: Figures 5-8 As shown in the figure, the devices all possess the aforementioned characteristics and beneficial effects. Furthermore, when the p-GaN in the p-type wide bandgap semiconductor layer 1-1 is replaced with p-AlGaN, specifically, the effective hole concentration of the p-type wide bandgap semiconductor layer is approximately 1 × 10⁻⁶. 18 cm -3 p-Al 0.05 Ga 0.95 N, the transfer characteristic curve and gate current waveform of the device are as follows Figure 9 As shown in the figure, all devices possess the aforementioned characteristics and beneficial effects. It should be further noted that all the aforementioned devices exhibit the same characteristics and beneficial effects when the substrate is replaced with SiC or sapphire, the buffer layer is replaced with high-resistivity AlGaN, the P-type wide bandgap semiconductor layer is replaced with p-NiO, the channel layer is replaced with InGaN, and the barrier layer is replaced with GaN / AlGaN, AlGaN / AlN, or InAlN.

[0053] It should be noted that the materials, molar composition, doping concentration, length, and thickness exemplified in this embodiment do not limit the scope of protection of this invention. These parameters can be adaptively optimized according to the needs of the application.

[0054] Example 2

[0055] This embodiment provides a junction-gate enhancement-mode lateral GaN device, the structure of which is as follows: Figure 10 As shown, it includes: a P-type wide bandgap semiconductor layer 1-1, a metal gate 1-2, a first N-type semiconductor layer 1-3, a barrier layer 1-4, a channel layer 1-5, a source ohmic contact metal layer 1-6, a drain ohmic contact metal layer 1-7, a buffer layer 1-8, a substrate 1-9, a first dielectric passivation layer 1-10, a second dielectric passivation layer 1-11, a metal source 1-12, a metal drain 1-13, a second N-type semiconductor layer 1-14, and a third N-type semiconductor layer 1-15, wherein the buffer layer 1-8 is disposed on the substrate, the channel layer 1-5 is disposed on the buffer layer, and the barrier layer 1-4 is disposed on the channel layer;

[0056] A P-type wide bandgap semiconductor layer 1-1, a first N-type semiconductor layer 1-3, and a metal gate 1-2 are stacked sequentially from bottom to top to form a junction gate portion. A second N-type semiconductor layer 1-14, the junction gate portion, and a third N-type semiconductor layer 1-15 are disposed on a barrier layer 1-4. A source ohmic contact metal layer 1-6 is disposed on the second N-type semiconductor layer 1-14, and a drain ohmic contact metal layer 1-7 is disposed on the third N-type semiconductor layer 1-15. The junction gate portion is located between the second N-type semiconductor layer and the third N-type semiconductor layer, and is adjacent to the source ohmic contact metal layer 1-6. A metal source 1-12 is disposed on the source ohmic contact metal layer 1-6, and a metal drain 1-13 is disposed on the drain ohmic contact metal layer 1-7.

[0057] The first dielectric passivation layer 1-10 covers the upper surfaces of the second N-type semiconductor layer and the third N-type semiconductor layer, the barrier layer between the second N-type semiconductor layer and the junction gate portion, the barrier layer between the third N-type semiconductor layer and the junction gate portion, and the two side portions of the P-type wide bandgap semiconductor layer 1-1 and the first N-type semiconductor layer 1-3. The second dielectric passivation layer 1-11 covers the first dielectric passivation layer and the upper surface of the metal gate 1-2.

[0058] Furthermore, the gate metal 1-2 extends to both sides of the first N-type semiconductor layer 1-3 to form a gate field plate, and the gate field plate covers the upper surface of the first dielectric passivation layer 1-10; the source metal 1-12 and the drain metal 1-13 extend to the channel region between the gate and drain to form a source field plate and a drain field plate respectively, and the source field plate and the drain field plate cover the upper surface of the second dielectric passivation layer 1-11.

[0059] Furthermore, in this embodiment, the substrate is P-type Si, the buffer layer is C-doped GaN, the channel layer is 400nm UID-GaN, the barrier layer is AlGaN with a molar composition of 0.2 and a thickness of 10nm, and the P-type wide bandgap semiconductor layer has an effective hole concentration of approximately 1×10⁻⁶. 18 cm -3 In the p-GaN, the first, second, and third N-semiconductor layers are all 25nm thick N-type Al. 0.25 Ga 0.75 N, its doping is 1×10 17 cm -3 The gate-source pitch and gate-drain pitch are 1.5µm and 13.5µm, respectively, the gate length is 2µm, and it uses a metal gate and an N-type Al. 0.25 Ga 0.75 N is set as a Schottky contact, the first dielectric passivation layer is 100nm thick SiN, and the second dielectric passivation layer is 50nm thick SiO2.

[0060] Based on the above parameters, simulation tests were performed on the junction-gate enhancement-mode lateral GaN device in this embodiment. A conventional p-GaN gate HEMT with the same epitaxial layer configuration, the same first dielectric passivation layer and barrier layer interface trap configuration, and the same P-type wide bandgap semiconductor layer was used as a comparative example. The transfer characteristic curves and gate current waveforms of the two devices were compared. Figure 11 As shown, the tested V DS =1V; As shown in the figure, firstly, the device achieves enhancement-mode characteristics, with a threshold voltage of approximately 2V, which is higher than that of traditional p-GaN HEMTs; more importantly, the device V GS At 10V, the gate current density is only on the order of nA / mm², compared to the V² of traditional p-GaN HEMTs. GS The gate current is reduced by several orders of magnitude from the ~300μA / mm at 6V. Because traditional p-GaN HEMTs have excessively high gate currents, their gate voltage is generally limited to below 6V. This invention, however, maintains extremely low gate currents even when the gate voltage is increased to 10V or even 15V, thus reducing the difficulty of driver circuit design, lowering gate overvoltage protection requirements, and reducing driver circuit power consumption. Furthermore, this invention exhibits higher current density, i.e., lower specific on-resistance. The lower specific on-resistance is due to the simultaneous formation of a second barrier layer (a second N-type semiconductor layer and a third N-type semiconductor layer) while fabricating the first N-type semiconductor layer in the junction gate region. This arrangement increases the total barrier layer thickness, and the second barrier layer has a higher Al molar composition than the first barrier layer, resulting in higher polarization intensity. Consequently, the two-dimensional electron gas concentration in the source / drain channel region is significantly higher than the traditional 7.4e12cm³. -3 Increased to 9.9e12cm -3 This results in a lower specific on-resistance, which helps reduce conduction losses, switching losses, and improve system power density.

[0061] Furthermore, when the first, second, and third N-semiconductor layers are all replaced with 25nm thick N-type AlN, doped with 1×10⁻⁶... 17 cm -3 At the same time, the transfer characteristic curves and gate current waveforms of this embodiment are compared with those of the comparative examples. Figure 12 As shown, it is obvious. Figure 12 and Figure 11 It exhibits similar properties and beneficial effects; moreover, the AlN polarization intensity of the second barrier layer is high, resulting in a higher two-dimensional electron gas concentration in the source / drain channel region compared to the conventional 7.4e12cm⁻¹. -3 Increased to 5.4e13cm -3This results in a lower specific on-resistance, which helps reduce conduction losses, switching losses, and improve system power density. It should be further noted that in this embodiment, the device exhibits similar characteristics and beneficial effects when the p-GaN of the P-type wide bandgap semiconductor layer 1-1 is replaced with p-AlGaN or p-NiO, and similar characteristics and beneficial effects are achieved when the first, second, and third N-type semiconductor layers are replaced with N-type InAlN.

[0062] Example 3

[0063] This embodiment provides a junction-gate enhancement-mode lateral GaN device, which differs from Embodiment 2 in that: the first, second, and third N-semiconductor layers consist of undoped AlN with a bottom thickness of 5 nm and N-type GaN (doped with 1e17cm) with a top thickness of 25 nm. -3 The transfer characteristic curves and gate current waveforms of this embodiment are compared with those of the comparative examples. Figure 13 As shown, it is obvious. Figure 13 It exhibits similar characteristics and beneficial effects to Example 2.

[0064] All the above embodiments exhibit similar effects when the substrate is replaced with SiC or sapphire, the buffer layer is replaced with high-resistivity AlGaN, the channel layer is replaced with InGaN, and the barrier layer is replaced with GaN / AlGaN, AlGaN / AlN, or InAlN.

[0065] Example 4

[0066] This embodiment provides a method for fabricating the junction-gate enhancement-mode GaN device as described in Embodiment 2, specifically including the following steps:

[0067] Step 1. Epitaxially grow a buffer layer Al on a p-type Si substrate. 0.1 Ga 0.9 N, Undoped channel layer GaN and barrier layer Al 0.2 Ga 0.8 N, It should be noted that the epitaxial processes for the buffer layer, channel layer and barrier layer are all existing technologies and will not be described in detail here;

[0068] Step 2. An epitaxial growth process is used to grow a p-GaN layer on the barrier layer. After photolithography, ICP, IRE, or ICP-RIE etching is used to form a p-type wide-bandgap semiconductor p-GaN layer. Figure 14 As shown in (a);

[0069] Step 3. Grow N-type Al with a thickness of 25 nm using epitaxial growth technology. 0.25 Ga 0.75 The N-layer covers the entire device surface, and after photolithography, patterned first, second, and third N-type Al layers are formed by ICP, IRE, or ICP-RIE etching.0.25 Ga 0.75 N layers; among which, the first N-type Al 0.25 Ga 0.75 The N-layer is located on the p-type wide-bandgap semiconductor p-GaN layer, and its two end boundaries are located within the two end boundaries of the p-GaN layer. The second and third N-type Al... 0.25 Ga 0.75 The N-layers are located on both sides of the p-GaN layer and are not in contact with it, such as Figure 14 As shown in (b);

[0070] Step 4. After photolithography, a composite metal layer Ti / Al / Ni / Au is grown on the device surface using evaporation or sputtering processes. Then, a lift-off process is used to form the source and drain ohmic contact layers, respectively. Finally, a rapid thermal annealing treatment is performed at 800–900°C under a N2 atmosphere. Figure 14 As shown in (c);

[0071] Step 5. Grow the first dielectric passivation layer SiN covering the entire device surface using ALD or CVD processes. After photolithography, etch the first dielectric passivation layer using ICP, RIE, or ICP-RIE dry etching on the N-type Al 0.25 Ga 0.75 A gate metal contact hole is formed above the N layer, such as Figure 14 As shown in (d);

[0072] Step 6. After photolithography, a composite metal layer Ni / Au is grown on the device surface using evaporation or sputtering processes. Then, a lift-off process is used to form the gate metal and gate field plate, as shown below. Figure 14 As shown in (e);

[0073] Step 7. A second dielectric passivation layer (SiO2) is grown using ALD or CVD processes to cover the entire device surface. After photolithography, the first and second dielectric passivation layers are etched using ICP, RIE, or ICP-RIE dry etching to form source and drain metal contact holes above the source and drain ohmic contact layers, respectively. Figure 14 As shown in (f);

[0074] Step 8. After photolithography, a second metal layer Al is grown using evaporation or sputtering to cover the entire device surface. A lift-off process is then used to form the source metal and source field plate, and the drain metal and drain field plate, as shown below. Figure 14 As shown in (g).

[0075] As can be seen from the above process, an N-type wide bandgap semiconductor layer covering the device surface is produced in one step by epitaxy, and then the first N-type semiconductor layer 1-3, the second N-type semiconductor layer 1-14, and the third N-type semiconductor layer 1-15 are formed simultaneously by etching. The first N-type semiconductor layer 1-3 forms a reverse bias PN junction with the P-type wide bandgap semiconductor region 1-1, which prevents the gate current from increasing when the device is turned on and has high electrothermal stability. The second N-type semiconductor layer 1-14 and the third N-type semiconductor layer 1-15 form a double barrier with the barrier layer 1-4, which helps to increase the two-dimensional electron gas concentration in the source-drain channel region, thereby reducing the specific on-resistance of the device.

[0076] Example 5

[0077] Based on the same junction gate structure as in Embodiment 1, this embodiment provides a junction gate enhancement-mode vertical GaN device, the structure of which is as follows: Figure 15 As shown, it specifically includes: a P-type wide bandgap semiconductor layer 2-1, a metal gate 2-2, an N-type semiconductor layer 2-3, a barrier layer 2-4, a channel layer 2-5, a metal source 2-6, a P-type electric field shielding region 2-7, an N-type current path region 2-8, a voltage withstand layer 2-9, a first dielectric passivation layer 2-10, a second dielectric passivation layer 2-11, a substrate 2-12, and a metal drain 2-13. The metal drain 2-13 is disposed under the substrate, the voltage withstand layer 2-9 is disposed on the substrate, two P-type electric field shielding regions 2-7 and a current path region 2-8 located between the two P-type electric field shielding regions are disposed on the voltage withstand layer, an unintentionally doped (UID) channel layer 2-5 is disposed on the P-type electric field shielding region and the current path region, and a barrier layer 2-4 is disposed on the channel layer.

[0078] A P-type wide bandgap semiconductor layer 2-1, an N-type semiconductor layer 2-3, and a metal gate 2-2 are stacked sequentially from bottom to top to form a junction gate portion, which is disposed on a barrier layer. A first dielectric passivation layer 2-10 covers the upper surface of the barrier layer and part of both sides of the N-type semiconductor layer 2-3. A second dielectric passivation layer 2-11 covers the upper surface of the first dielectric passivation layer and the metal gate 2-2. A metal source 2-6 covers the upper surface of the second dielectric passivation layer and is in contact with the barrier layer 2-4, the channel layer 2-5, and the P-type electric field shielding region on both sides, respectively.

[0079] Furthermore, in this embodiment, the substrate is made of heavily doped N-type GaN, and the breakdown layer is made of lightly doped N-type GaN, typically with a concentration of 1e14 to 1e17 cm⁻¹. -3Between these layers, the current path region is made of N-type GaN with a higher concentration than the breakdown voltage layer; the barrier layer is made of AlGaN, GaN / AlGaN, AlGaN / AlN, or InAlN, and the molar composition of Al in AlGaN or the molar composition of InAlN should be adaptively designed according to application requirements; the P-type wide bandgap semiconductor layer is made of P-type GaN, AlGaN, or NiO with a concentration greater than 1e17cm⁻¹. -3 The molar composition of Al in P-type AlGaN is generally between 0 and 0.35 depending on different requirements. The thickness of the P-type wide bandgap semiconductor layer should be adaptively designed according to the application requirements.

[0080] In terms of working principle: the junction gate section in this embodiment is the same as that in embodiment 1, the gate control principle is similar to that in embodiment 1, and its transfer characteristic curve and gate current are also similar to those in embodiment 1, with the same characteristics and beneficial effects.

[0081] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A junction-gate enhancement-mode GaN device based on a PN junction, comprising: The structure comprises a P-type wide bandgap semiconductor layer (1-1), a metal gate (1-2), a first N-type semiconductor layer (1-3), a barrier layer (1-4), an unintentionally doped channel layer (1-5), a source ohmic contact metal layer (1-6), a drain ohmic contact metal layer (1-7), a buffer layer (1-8), a substrate (1-9), a first dielectric passivation layer (1-10), a second dielectric passivation layer (1-11), a metal source (1-12), a metal drain (1-13), a second N-type semiconductor layer (1-14), and a third N-type semiconductor layer (1-15), wherein the buffer layer is disposed on the substrate, the channel layer is disposed on the buffer layer, and the barrier layer is disposed on the channel layer; The key feature is that a P-type wide bandgap semiconductor layer, a first N-type semiconductor layer, and a metal gate are stacked sequentially from bottom to top to form a junction gate portion; a second N-type semiconductor layer, the junction gate portion, and a third N-type semiconductor layer are disposed on a barrier layer, with the junction gate portion located between the second N-type semiconductor layer and the third N-type semiconductor layer; a source ohmic contact metal layer is disposed on the second N-type semiconductor layer, a drain ohmic contact metal layer is disposed on the third N-type semiconductor layer, a metal source is disposed on the source ohmic contact metal layer, and a metal drain is disposed on the drain ohmic contact metal layer; a first dielectric passivation layer covers the upper surfaces of the second N-type semiconductor layer and the third N-type semiconductor layer, the barrier layer between the second N-type semiconductor layer and the junction gate portion, the barrier layer between the third N-type semiconductor layer and the junction gate portion, and the two side regions of the P-type wide bandgap semiconductor layer and the first N-type semiconductor layer; and a second dielectric passivation layer covers the first dielectric passivation layer and the upper surface of the metal gate.

2. The junction-gate enhancement-mode GaN device based on a PN junction as described in claim 1, characterized in that, The gate metal extends to both sides of the first N-type semiconductor layer to form a gate field plate, and the gate field plate covers the upper surface of the first dielectric passivation layer; The source metal and drain metal extend into the channel region between the gate and drain to form the source field plate and drain field plate, respectively, which cover the upper surface of the second dielectric passivation layer.

3. The junction-gate enhancement-mode GaN device based on a PN junction as described in claim 1, characterized in that, The first N-type semiconductor layer, the second N-type semiconductor layer, and the third N-type semiconductor layer are made of N-type AlGaN, InAlN, or AlN.

4. The method for fabricating a junction-gate enhancement-mode GaN device based on a PN junction as described in claim 1, comprising the following steps: Step 1. Grow a buffer layer, a channel layer, and a barrier layer sequentially on the substrate; Step 2. A P-type wide bandgap semiconductor thin film is grown on the barrier layer using an epitaxial growth process. After photolithography, the P-type wide bandgap semiconductor layer is formed by dry etching using ICP, IRE, or ICP-RIE. Step 3. An N-type semiconductor thin film is grown using epitaxial growth technology to cover the entire device surface. After photolithography, patterned first, second, and third N-type semiconductor layers are formed by dry etching using ICP, IRE, or ICP-RIE. The first N-type semiconductor layer is located on the P-type wide bandgap semiconductor layer, and its two end boundaries are located within the boundaries of the P-type wide bandgap semiconductor layer. The second and third N-type semiconductor layers are located on both sides of the P-type wide bandgap semiconductor layer and are not in contact with it. Step 4. After photolithography, a metal layer is formed on the device surface using evaporation or magnetron sputtering. Then, a lift-off process is used to form the source ohmic contact layer and the drain ohmic contact layer, respectively. Finally, rapid thermal annealing is performed in N2. Step 5. Grow a first dielectric passivation layer covering the entire device surface using ALD or CVD processes. After photolithography, use ICP, RIE, ICP-RIE dry etching or wet etching to form a gate metal contact hole above the first N-type semiconductor layer. Step 6. After photolithography, a metal layer is formed on the device surface using evaporation or sputtering processes, and then a lift-off process is used to form the gate metal and gate field plate; Step 7. Use ALD or CVD process to grow a second dielectric passivation layer to cover the entire device surface. After photolithography, use ICP, RIE or ICP-RIE dry etching to form source metal contact holes and drain metal contact holes above the source ohmic contact layer and drain ohmic contact layer, respectively. Step 8. After photolithography, an evaporation or sputtering process is used to form a metal layer covering the entire device surface. Then, a lift-off process is used to form the source metal and source field plate, and the drain metal and drain field plate. Alternatively, ICP, RIE, ICP-RIE dry etching or wet etching is used to form the source metal and source field plate, and the drain metal and drain field plate.

5. A junction-gate enhancement-mode GaN device based on a PN junction, comprising: The structure comprises a P-type wide bandgap semiconductor layer (2-1), a metal gate (2-2), an N-type semiconductor layer (2-3), a barrier layer (2-4), an unintentionally doped channel layer (2-5), a metal source (2-6), a P-type electric field shielding region (2-7), an N-type current path region (2-8), a voltage withstand layer (2-9), a first dielectric passivation layer (2-10), a second dielectric passivation layer (2-11), a substrate (2-12), and a metal drain (2-13). The metal drain is disposed under the substrate, the voltage withstand layer is disposed on the substrate, two P-type electric field shielding regions and an N-type current path region located between the two P-type electric field shielding regions are disposed on the voltage withstand layer, the unintentionally doped channel layer is disposed on the P-type electric field shielding region and the current path region, and the barrier layer is disposed on the channel layer. The key feature is that a P-type wide bandgap semiconductor layer, an N-type semiconductor layer, and a metal gate are stacked sequentially from bottom to top to form a junction gate portion, which is disposed on a barrier layer; a first dielectric passivation layer covers the upper surface of the barrier layer and a portion of both sides of the N-type semiconductor layer; a second dielectric passivation layer covers the first dielectric passivation layer and the upper surface of the metal gate; and a metal source covers the upper surface of the second dielectric passivation layer, with its two sides respectively in contact with the barrier layer, the channel layer, and the P-type electric field shielding region.

6. The junction-gate enhancement-mode GaN device based on a PN junction as described in claim 5, characterized in that, The N-type semiconductor layer is made of N-type GaN, AlGaN, InGaN, InAlN, AlN, or polycrystalline silicon.

7. The junction-gate enhancement-mode GaN device based on a PN junction as described in claim 5, characterized in that, The N-type semiconductor layer forms a Schottky contact or an ohmic contact with the gate metal.

8. The junction-gate enhancement-mode GaN device based on a PN junction as described in claim 5, characterized in that, The N-type semiconductor layer adopts a two-layer structure, with the bottom and top layers made of the same material. The bottom layer is made of lightly doped or undoped semiconductor material, and the top layer is made of heavily doped semiconductor material.

9. The junction-gate enhancement-mode GaN device based on a PN junction according to claim 5, characterized in that, The N-type semiconductor layer adopts a two-layer structure, with the bottom and top layers made of different materials. The bottom layer is made of lightly doped or undoped semiconductor material, and the top layer is made of lightly doped or heavily doped semiconductor material.

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