A pn-junction based junction gate enhancement-mode gan device

By using a junction gate structure based on a PN junction and a double-layer barrier layer design, the problems of poor threshold voltage consistency and stability in existing enhancement-mode GaN devices are solved. This achieves large gate voltage swing, low gate leakage current and low specific on-resistance, simplifies the process flow and reduces drive losses.

CN115172452BActive Publication Date: 2026-06-19UNIV OF ELECTRONICS SCI & TECH OF CHINA
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
UNIV OF ELECTRONICS SCI & TECH OF CHINA
Filing Date
2022-06-20
Publication Date
2026-06-19

AI Technical Summary

Technical Problem

Existing enhancement-mode GaN devices suffer from problems such as poor threshold voltage consistency, poor stability and reliability, channel damage, low two-dimensional electron gas concentration, high channel resistance, narrow gate voltage swing, large gate leakage current, high process difficulty, and complex drive design.

Method used

It adopts a junction gate structure based on a PN junction, and forms a reverse-biased depletion channel through a PN junction formed by a P-type wide bandgap semiconductor layer and an N-type semiconductor layer. Combined with a double-layer barrier layer design, it increases the positive voltage of the gate metal to open the gate channel, reduces the gate leakage current, and forms a field plate through a dielectric passivation layer to improve the breakdown voltage and suppress current collapse.

Benefits of technology

It achieves large gate voltage swing, low gate leakage current, low specific on-resistance, improved threshold voltage consistency and electrothermal stability, simplifies the process flow, and reduces drive losses and circuit design difficulty.

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Abstract

This invention belongs to the field of power semiconductor technology and provides a junction-gate enhancement-mode GaN device based on a PN junction to solve many problems existing in current devices, such as narrow gate voltage swing, large gate leakage current, high process requirements, high specific on-resistance, high cost, and poor electrothermal stability. This invention utilizes a wide-bandgap P-type semiconductor to deplete the high-concentration two-dimensional electron gas beneath it to obtain an enhancement-mode device. Simultaneously, a reverse-biased N-type semiconductor is placed on the wide-bandgap P-type semiconductor to form a junction gate, preventing current injection from the gate into the wide-bandgap P-type semiconductor layer, thereby achieving extremely low gate leakage current. Furthermore, by simultaneously introducing N-type semiconductors into the source and drain channel regions to form a double-layer barrier structure, the two-dimensional electron gas density in the source and drain channel regions is increased. Ultimately, the enhancement-mode GaN device of this invention possesses advantages such as large gate voltage swing, low gate leakage current, low channel specific on-resistance, high threshold voltage consistency, simple process, low cost, and high stability.
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