An enhanced MIS structure gallium nitride-based p-channel field effect transistor and a method for manufacturing the same

Abstract

This invention belongs to the field of semiconductor devices and provides an enhancement-mode MIS structure gallium nitride-based p-channel field-effect transistor and its fabrication method. The device structure includes: a substrate layer; a GaN buffer layer; a UID-GaN layer; and an Al layer. x Ga 1‑x An N-type barrier layer; a p-type semiconductor layer with a groove corresponding to the gate region; a source electrode and a gate electrode, disposed on both sides of the p-type semiconductor layer; a hexagonal boron nitride (h-BN) insertion layer covering the bottom of the groove; an aluminum oxide (Al2O3) dielectric layer covering the h-BN layer, the sidewalls of the groove, and extending to both sides along the surface of the p-type semiconductor; and a gate electrode disposed above the dielectric layer. This invention employs an h-BN insertion layer, which, together with Al2O3, forms a composite dielectric layer, reducing surface defects and improving surface quality, thereby reducing the device's gate leakage current and on-resistance. The h-BN / GaN polarization induces additional negative charges, increasing the carrier surface density in the channel and improving the device's saturation output current. Furthermore, the grooved gate structure effectively suppresses the formation of the on-channel in the off-state, enabling the device to achieve enhancement mode.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and particularly relates to an enhancement-mode MIS structure gallium nitride-based p-channel field-effect transistor and its fabrication method. Background Technology

[0002] Gallium nitride (GaN), a wide-bandgap semiconductor material, possesses characteristics such as high electron saturation velocity, high electron mobility, and high thermal conductivity, making it widely used in high-frequency, high-power, and high-voltage electronic devices. To effectively reduce parasitic loop inductance and improve system performance, monolithic integration technology based on GaN power devices has become a key focus in the industry. GaN monolithic integration is gradually becoming the main development trend in the design of power modules based on GaN devices. Among these, the gallium nitride-based p-channel field-effect transistor (p-FET), as one of the key devices, has attracted significant attention from the industry.

[0003] Gate leakage current is one of the key factors affecting the performance of gallium nitride-based p-channel field-effect transistors (GaN-based P-channel MOSFETs). Higher gate leakage current not only increases power consumption but also reduces device reliability and lifespan. Furthermore, the presence of surface states on the semiconductor surface not only provides a path for gate leakage current but also exacerbates hole scattering in the channel, reducing carrier mobility and impacting device output characteristics. To suppress gate leakage current, existing technologies often employ metal-insulator-semiconductor (MIS) structures, which introduce a dielectric layer in the gate region to block the leakage path. This structure is considered one of the effective ways to improve device performance.

[0004] However, in existing MIS structures, dielectric layer materials (such as oxides) often introduce interface traps (such as Ga-O related defects) when forming heterojunctions with GaN, leading to a decrease in interface quality and making it difficult to balance low gate-drain current and high channel current density. In addition, the surface morphology and interface polarization characteristics of traditional dielectric layers make it difficult to effectively control the channel hole concentration, limiting further improvements in the performance of p-channel devices.

[0005] Therefore, how to effectively reduce the scattering of channel holes by surface states and increase the channel carrier concentration while suppressing gate leakage current, and achieve synergistic optimization of gate control capability and conduction characteristics, has become an urgent technical problem to be solved in the field of gallium nitride-based p-channel field-effect transistors. Summary of the Invention

[0006] The present invention aims to provide an enhanced MIS structure gallium nitride-based p-channel field-effect transistor and its fabrication method. This enhanced MIS structure gallium nitride-based p-channel field-effect transistor can reduce gate leakage current, increase saturated output current density, and reduce on-resistance.

[0007] A first aspect of the present invention provides an enhanced MIS structure gallium nitride-based p-channel field-effect transistor, the enhanced MIS structure gallium nitride-based p-channel field-effect transistor comprising:

[0008] Substrate layer;

[0009] A buffer layer, a UID-GaN layer, a barrier layer, and a p-type semiconductor layer are sequentially located on the substrate layer;

[0010] The source electrode and the drain electrode are respectively disposed on two laterally opposite sides of the upper surface of the p-type semiconductor layer;

[0011] A gate groove is formed in the p-type semiconductor layer and located between the source electrode and the drain electrode.

[0012] h-BN insertion layer is disposed at the bottom of the gate groove;

[0013] A dielectric layer covers the h-BN insertion layer and extends to both ends until it covers the entire surface of the p-type semiconductor layer between the source and drain electrodes.

[0014] The gate electrode is disposed above the dielectric layer and corresponds to the position of the gate groove.

[0015] In some embodiments of the present invention, the substrate layer is made of silicon, sapphire, or silicon carbide.

[0016] In some embodiments of the present invention, the thickness of the GaN buffer layer is 3μm-5μm;

[0017] The thickness of the UID-GaN layer is 100-500nm;

[0018] The depth of the gate groove is 35-75 nm.

[0019] In some embodiments of the present invention, the barrier layer material is AlGaN with a thickness of 10nm-50nm; wherein the proportion of Al component is between 10-30%.

[0020] In some embodiments of the present invention, the p-type semiconductor layer is made of any one of Mg-doped GaN, AlGaN, InGaN, and InN, and has a thickness of 40-80 nm; wherein the Mg doping concentration is 1×10⁻⁶. 19 cm -3 ~3×10 19 cm -3 .

[0021] In some embodiments of the present invention, the ohmic contact between the source electrode and the drain electrode is made of a Ti / Al / Ni / Au metal stack.

[0022] In some embodiments of the present invention, the thickness of Ti metal in the Ti / Al / Ni / Au metal stack is 20-40 nm, the thickness of Al metal is 120-180 nm, the thickness of Ni metal is 20-50 nm, and the thickness of Au metal is 40-60 nm.

[0023] In some embodiments of the present invention, the thickness of the h-BN insertion layer is 2nm-5nm; the dielectric layer material is aluminum oxide (Al2O3) with a thickness of 5nm-20nm.

[0024] In some embodiments of the present invention, the gate electrode is made of Ti / Au multilayer metal, wherein the thickness of Ti metal is 15-25 nm and the thickness of Au metal is 80-120 nm.

[0025] A second aspect of the present invention provides a method for fabricating the above-described enhanced MIS structure gallium nitride-based p-channel field-effect transistor, the method comprising:

[0026] Step S1: Provide a substrate layer;

[0027] Step S2: Using metal-organic chemical vapor deposition, GaN buffer layer, UID-GaN layer, barrier layer and p-type semiconductor layer are epitaxially grown sequentially on the substrate.

[0028] Step S3: A gate trench with a depth of 35-75 nm is formed in the middle of the p-type semiconductor layer using inductively coupled plasma etching technology;

[0029] Step S4: Using electron beam evaporation, metal is deposited on both sides of the p-type semiconductor layer, and after rapid thermal annealing, ohmic contact source and drain electrodes are formed.

[0030] Step S5: Using chemical vapor deposition (CVD) technology, cover the gate groove with an h-BN insertion layer;

[0031] Step S6: Using atomic layer deposition technology, a dielectric layer is applied above the h-BN insertion layer and to the sidewalls of the gate recess, and the dielectric layer extends to both sides along the upper surface of the p-type semiconductor layer.

[0032] Step S7: Deposit metal over the dielectric layer to form a gate electrode.

[0033] Step S8: Etch the dielectric layer and open windows at the corresponding source and drain regions.

[0034] The enhanced MIS structure gallium nitride-based p-channel field-effect transistor and its fabrication method according to embodiments of the present invention have at least one of the following advantages:

[0035] (1) Reducing gate leakage current: The present invention introduces an h-BN insertion layer into the grooved gate structure, which can form a composite dielectric layer with Al2O3 to form a double-layer gate barrier structure with targeted interface optimization and overall dielectric coverage. On the one hand: the bottom h-BN precisely adheres to the semiconductor surface at the bottom of the groove, and h-BN / p-GaN forms a high conduction band step, increasing the width of the electron tunneling barrier and effectively suppressing Fowler-Nordheim tunneling. Its chemical inertness blocks the formation of surface oxides, reduces the interface state density, and reduces the trap-assisted tunneling leakage path. At the same time, the atomic-level flatness of h-BN eliminates the local electric field concentration effect of traditional rough interfaces, avoids the generation of local high field regions, and achieves an exponential decrease in gate leakage current. On the other hand: the upper Al2O3 completely covers the h-BN surface, the sidewall of the gate groove and extends to the upper surface of the p-type semiconductor layer, realizing the overall dielectric coverage of the gate region and the active region, further passivating the dangling bonds and defect states on the device surface.

[0036] (2) Improve saturated output current density and reduce on-resistance: On the one hand, the heterogeneous interface structure between the h-BN insertion layer and p-GaN significantly reduces the gate dielectric-channel interface state density, reduces interface scattering during carrier transport, and improves the channel hole mobility; on the other hand, the h-BN / GaN interface polarization effect can directionally induce polarized negative charges in the channel region under the gate, significantly improve the surface density of hole carriers in the channel, and enhance the carrier conduction ability, thereby achieving higher output current density and lower on-resistance.

[0037] (3) Achieving enhancement mode: By using the grooved gate structure, the two-dimensional hole gas in the channel region directly below the gate is exhausted, so that the device cannot form a conductive channel in the off state, thereby increasing the output current and achieving enhancement mode. Attached Figure Description

[0038] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0039] Figure 1 The diagram shown is a schematic representation of an enhanced MIS structure gallium nitride-based p-channel field-effect transistor provided in an embodiment of the present invention.

[0040] Figure 2 The figure shown is V D At -0.5V, a comparison chart (linear coordinates) of the transfer curves of the enhanced MIS structure gallium nitride p-channel field-effect transistor with h-BN insertion layer in Embodiment 1 of the present invention and the conventional gallium nitride p-channel field-effect transistor using Al2O3 gate dielectric.

[0041] Figure 3 The figure shown is V G= -5V, comparison of the output curves of the enhanced MIS structure gallium nitride p-channel field-effect transistor with h-BN insertion layer in Embodiment 1 of the present invention and the conventional gallium nitride p-channel field-effect transistor using Al2O3 gate dielectric.

[0042] Figure 4 The figure shown is V D = 0V, comparison diagram (semi-logarithmic coordinates) of gate leakage of the enhanced MIS structure gallium nitride p-channel field-effect transistor with h-BN insertion layer of Embodiment 1 of the present invention and the conventional gallium nitride p-channel field-effect transistor using Al2O3 gate dielectric. Detailed Implementation

[0043] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0044] In this invention, the term "etching" refers to the process of selectively removing unwanted material from the surface of a substrate using chemical or physical methods.

[0045] In this invention, the term "inductively coupled plasma etching" refers to the process where reactive gases undergo glow discharge via inductive coupling, generating highly chemically active plasma ions that, under the acceleration of an electric field, move to the sample surface. This plasma ions both chemically react to generate volatile gases and physically etch the sample surface. Because the plasma source and the radio frequency acceleration source are separated, the plasma density can be higher, and the acceleration capability can be enhanced, resulting in a higher etching rate and better anisotropic etching.

[0046] In this invention, the term "chemical vapor deposition (CVD)" refers to a method that uses high temperature or specific energy to excite gaseous precursors to undergo pyrolysis, decomposition, and chemical reactions in a reaction chamber to generate active groups containing target thin film elements. These active groups migrate, adsorb, nucleate, and grow on the substrate surface, thereby forming a uniform, dense, high-quality thin film.

[0047] In this invention, the term "atomic layer deposition (ALD)" refers to a method that uses alternating pulses to introduce different gaseous precursors, causing the precursors to undergo self-limiting chemisorption and surface reactions on the substrate surface in sequence. The reaction products are removed by purging with an inert gas, and then the above pulse cycle process is repeated to achieve atomic-scale layer-by-layer deposition, thereby forming an ultrathin, uniform, dense, and high-quality thin film.

[0048] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

[0049] Boron nitride (h-BN) possesses an ultra-wide bandgap of 6 eV, excellent chemical inertness, high thermal conductivity, and strong mechanical strength. Its atomically flat surface, free of dangling bonds and charged impurities, makes it highly promising as a dielectric layer and surface passivation layer in power electronic devices. Particularly for gallium nitride-based devices, BN eliminates Ga-O-related interface traps in oxide media, providing a strong guarantee for constructing high-quality heterojunction interfaces and thus reducing gate leakage current. Simultaneously, the atomically flat surface of h-BN ensures ideal flatness of the heterojunction interface, and its passivation layer effect effectively suppresses surface states and interface defects, reducing interface scattering of hole carriers. The h-BN / GaN interface polarization effect can introduce additional negative charges, increasing channel carrier concentration and further improving the device's electrical performance.

[0050] To reduce the gate leakage current of gallium nitride-based p-channel field-effect transistors (GaN-based P-channel MOSFETs), thereby decreasing power consumption and improving device reliability and lifespan, this invention proposes an enhancement-mode MIS structure GaN-based P-channel MOSFET, the structure of which can be found in [reference needed]. Figure 1 As shown, it includes: a substrate layer 01; a buffer layer 02, a UID-GaN layer 03, a barrier layer 04, and a p-type semiconductor layer 05 sequentially located on the substrate layer 01; a source electrode 06 and a drain electrode 07, respectively disposed on opposite sides of the upper surface of the p-type semiconductor layer 05; a gate groove; formed in the p-type semiconductor layer 05 and located between the source electrode 06 and the drain electrode 07; an h-BN insertion layer 08 disposed at the bottom of the gate groove; a dielectric layer 09 covering the h-BN insertion layer 08 and extending to both ends until it covers the entire surface of the p-type semiconductor layer 05 located between the source electrode 06 and the drain electrode 07; and a gate electrode 10 disposed above the dielectric layer 09 and corresponding to the position of the gate groove.

[0051] In some embodiments of the present invention, the substrate layer 01 is made of silicon, sapphire, or silicon carbide.

[0052] In some embodiments of the present invention, the thickness of the GaN buffer layer 02 is 3μm-5μm; the thickness of the UID-GaN layer 03 is 100-500nm; and the depth of the gate trench is 35-75nm.

[0053] In some embodiments of the present invention, the material of the barrier layer 04 is AlGaN, and the thickness is 10nm-50nm; wherein the proportion of Al component is between 10-30%.

[0054] In some embodiments of the present invention, the material of the p-type semiconductor layer 05 is any one of Mg-doped GaN, AlGaN, InGaN, and InN, and the thickness is 40-80 nm; wherein the Mg doping concentration is 1 × 10⁻⁶. 19 cm -3 ~3×10 19 cm -3 .

[0055] In some embodiments of the present invention, the ohmic contact between the source electrode 06 and the drain electrode 07 is made of a Ti / Al / Ni / Au metal stack. Preferably, the thickness of the Ti metal in the Ti / Al / Ni / Au metal stack is 20-40 nm, the thickness of the Al metal is 120-180 nm, the thickness of the Ni metal is 20-50 nm, and the thickness of the Au metal is 40-60 nm.

[0056] In some embodiments of the present invention, the thickness of the h-BN insertion layer 08 is 2nm-5nm; the dielectric layer 09 is made of aluminum oxide (Al2O3) and has a thickness of 5nm-20nm.

[0057] In some embodiments of the present invention, the gate electrode 10 is made of Ti / Au multilayer metal, wherein the thickness of Ti metal is 15-25 nm and the thickness of Au metal is 80-120 nm.

[0058] To facilitate understanding of the enhanced MIS structure gallium nitride-based p-channel field-effect transistor proposed in this embodiment, its detailed fabrication steps are given below:

[0059] The first step is to grow the epitaxial structure.

[0060] 1.1: A GaN buffer layer, a UID-GaN layer, a barrier layer, and a p-type semiconductor layer are sequentially grown on the substrate using metal-organic chemical vapor deposition (MOCVD).

[0061] 1.2: After epitaxy, the sample was treated in heated KOH for about 20 minutes, washed with deionized water and dried with nitrogen to remove any contaminants or residues that may have been generated during the growth process.

[0062] Step 2: Etching to form the grid grooves.

[0063] 2.1: For the samples after step one, low-damage inductively coupled plasma (ICP) reactive ion etching (RIE) technology is used to etch gate trenches in the gate region corresponding to the p-type semiconductor layer. A BCl3 / Cl2 mixed gas is used as the etching gas, with BCl3 as the primary etching gas, and photoresist as the etching mask. By pre-calibrating the etching time, the etching depth is precisely controlled to ensure that a p-type semiconductor layer of approximately 5–15 nm thickness is retained at the bottom of the gate trench, thus avoiding over-etching and damage to the underlying structure.

[0064] 2.2: After etching, the sample was placed in a nitrogen (N2) atmosphere and subjected to thermal annealing (RTA) at 750°C for 30 minutes. This step aims to activate magnesium (Mg) doping in the p-GaN layer, increase carrier concentration, and improve the electrical performance of the device.

[0065] 2.3: After thermal annealing, the sample is immersed in a heated tetramethylammonium hydroxide (TMAH) solution for approximately 15 minutes. TMAH treatment can not only effectively remove residual photoresist mask, but also repair surface damage introduced during etching, reduce surface roughness, improve interface quality, and provide good surface conditions for subsequent gate dielectric or metal electrode deposition.

[0066] Step 3: Create ohmic contacts between the source and drain.

[0067] 3.1: The sample is pre-baked on a hot plate, followed by spin coating with photoresist (such as S1813 or AZ5214) and spin-coating to obtain a uniform resist layer. Next, the source and drain regions are exposed using a photolithography machine, and after development, the desired ohmic contact pattern is formed on the sample surface. To enhance the adhesion and etch resistance of the photoresist, the sample is immersed in buffered oxide etchant (BOE) for approximately 3 minutes to remove the surface oxide layer. It is then rinsed with deionized water to remove residual photoresist and developer, and dried at 90°C for 4 minutes to harden the photoresist mask.

[0068] 3.2: After completing the pattern definition, a metal stack of Ti / Al / Ni / Au was deposited in the source region using electron beam evaporation (EBE). Subsequently, the photoresist and its overlying metal in the non-electrode regions were removed by a lift-off process, retaining only the ohmic metal in the source region. After lift-off, the sample was washed with deionized water and dried with nitrogen. Finally, it was rapidly thermally annealed at 550°C for 5 min in an oxygen (O2) atmosphere to form a low-resistance, highly stable p-type ohmic contact.

[0069] Step 4: Insertion layer deposition.

[0070] 4.1: Using ammonia borane as a precursor, a hexagonal boron nitride (h-BN) film with a thickness of approximately 2-5 nm was deposited on the surface of the above samples as an insertion layer using chemical vapor deposition (CVD). During the deposition process, hydrogen (H2) and nitrogen (N2) were continuously introduced as carrier gas and reactant gas, respectively, at flow rates of 20 sccm and 120 sccm, to maintain the total pressure in the reaction chamber at approximately 1 Torr.

[0071] 4.2: The sample was heated to 950°C and held until the temperature stabilized. Then, the ammonia borane precursor was introduced into the reaction chamber via a carrier gas. The precursor underwent pyrolysis and chemical reactions at high temperature, generating boron- and nitrogen-containing active groups. These active groups migrated, adsorbed, and grew orderly on the sample surface, forming an h-BN film with excellent crystal quality. To ensure the uniformity of the film and the crystal orientation required for the polarization effect, the entire growth process lasted 15 minutes.

[0072] 4.3: After growth is complete, stop the introduction of precursor and reaction gas, and only keep the carrier gas H2 continuously introduced for 5 min to remove the residual reaction byproducts in the chamber; then turn off the heating device and let the sample cool naturally to room temperature in the reaction chamber to complete the preparation of the h-BN insertion layer.

[0073] Step 5: Deposition of the medium layer.

[0074] 5.1: Trimethylaluminum (TMA) and deionized water (H2O) were used as alternating precursors. Aluminum oxide (Al2O3) films with a thickness of approximately 5-20 nm were deposited on the surface of the samples using atomic layer deposition (ALD) as the dielectric layer. During deposition, argon (Ar) gas was continuously introduced as the carrier gas at a flow rate of 50 sccm to maintain a stable total pressure of approximately 5 Torr within the reaction chamber.

[0075] 5.2: Heat the sample to 250℃ and maintain the temperature. After ensuring the reaction temperature stabilizes, start the ALD pulsed cycling program: First, introduce a trimethylaluminum (TMA) precursor pulse for 0.1 s to induce self-limiting chemisorption of TMA on the precursor surface; then purge with argon gas for 10 s to remove unadsorbed TMA precursor and reaction byproducts; next, introduce a deionized water precursor pulse for 0.1 s to allow H2O to react with the surface-adsorbed TMA to generate Al2O3; purge with argon gas again for 10 s to complete a single ALD deposition cycle. Repeat the above pulsed cycling process until an Al2O3 film of a certain thickness is deposited.

[0076] 5.3: After growth is complete, stop the flow of various precursors, keep the carrier gas argon flowing continuously for 5 minutes, then turn off the heating device and allow the sample to cool naturally to room temperature in the reaction chamber.

[0077] Step 6: Fabrication of the gate electrode.

[0078] 6.1: Spin-coat photoresist (such as S1813 or AZ5214) onto the sample surface and pre-bake it; use a mask for ultraviolet exposure, and after development, form a gate opening above the dielectric layer;

[0079] 6.2: Electron beam evaporation or magnetron sputtering techniques are used to deposit metal stacks in the gate opening region, with Ti / Au being a commonly used structure;

[0080] 6.3: The photoresist and excess metal above it are removed by a stripping process, leaving only the metal in the gate groove area to form the gate electrode.

[0081] Step 7: Open windows in the source and drain regions.

[0082] To form metal contacts between the source and drain, window etching is required on the dielectric layer corresponding to the source and drain regions.

[0083] 7.1: Using standard photolithography, define the contact window patterns for the source and drain electrodes above the dielectric layer;

[0084] 7.2: Selectively etch the dielectric layer using dry etching techniques (such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP)) or wet etching (such as buffered oxide etchant (BOE)) to expose the underlying semiconductor contact layer;

[0085] 7.3: After etching, the sample is rinsed with deionized water to remove residual photoresist and etching byproducts, and then dried with nitrogen (N2). The device fabrication is now complete.

[0086] Example 1

[0087] Substrate 01 is made of sapphire.

[0088] Buffer layer 02 is made of GaN, unintentionally doped, and has a thickness of 4.2 μm.

[0089] UID-GaN layer 03, unintentionally doped, with a thickness of 420nm;

[0090] Barrier layer 04 is made of AlGaN with an Al content of 0.2 and a thickness of 15 nm.

[0091] p-type semiconductor layer 05, material is GaN, Mg doping concentration is 1×10⁵ 19 cm -3 The thickness is 50nm;

[0092] The insertion layer is hexagonal boron nitride (h-BN) with a thickness of 2 nm.

[0093] The dielectric layer is made of aluminum oxide (Al2O3) and has a thickness of 10 nm.

[0094] Comparative Example 1: Traditional gallium nitride-based p-channel field-effect transistors using Al2O3 gate dielectric.

[0095] The structure is as follows:

[0096] Silicon substrate;

[0097] GaN buffer layer, unintentionally doped, with a thickness of 4.2 μm;

[0098] The UID-GaN layer, unintentionally doped, has a thickness of 420nm;

[0099] The barrier layer is made of AlGaN with an Al content of 0.2 and a thickness of 15 nm.

[0100] p-GaN layer, Mg doping concentration 1×10 19 cm -3 The thickness is 50nm;

[0101] A gate groove structure is etched on the p-GaN layer, with the groove facing the p-GaN channel layer. The bottom and sidewalls of the groove are covered with a gate dielectric layer Al2O3, and the gate dielectric extends to both sides along the upper surface of the p-GaN layer with a thickness of 10 nm. The source electrode and drain electrode are respectively disposed on both sides of the upper surface of the p-GaN layer, and the gate electrode is disposed above the gate dielectric layer of the gate groove.

[0102] Numerical simulations of this enhanced MIS structure gallium nitride-based p-channel field-effect transistor (FET) were performed using Silvaco TCAD. The main physical models employed included recombination, carrier statistics, mobility, polarization, and interface states. Shockley-Read-Hall and Auger recombination models were used to accurately describe trapping behavior. The Albrecht model was used to describe low-field transport characteristics, while a field-dependent mobility model suitable for nitrides was used for high-field transport. A polarization model was introduced to address the strong spontaneous and piezoelectric polarization effects in GaN materials, and Fermi-Dirac statistics were used as the basis for carrier distribution. The gate was configured as a Schottky contact with a metal work function of 4.8 eV. The specific contact resistance between the drain and source electrodes was set to 10 Ω. -4 Ω·cm 2 .

[0103] V D V represents the voltage between the drain and the source. In a p-channel field-effect transistor, since the charge carriers are holes, Vdrain D It is usually a negative value. In numerical simulation, V DIt is often used as one of the bias conditions to simulate the electrical characteristics of devices.

[0104] Figure 2 For V D At -0.5V, comparing the transfer curves (linear coordinates) of the gallium nitride-based p-channel field-effect transistor (GaN-based P-channel FET) of Example 1 with that of the conventional GaN-based P-channel FET using Al2O3 gate dielectric, it can be seen from the figure that the threshold voltages of the enhancement-mode MIS structure GaN-based P-channel FET with h-BN insertion layer in this example and the conventional GaN-based P-channel FET using Al2O3 gate dielectric are -0.5V and -3.1V, respectively, both achieving enhancement mode. The grooved gate structure depletes the two-dimensional hole gas in the gate region. By adjusting the depth of the groove, the threshold voltage of the device can be controlled to achieve enhancement mode.

[0105] Figure 3 For V G At -5V, comparing the output curves of the enhanced MIS structure gallium nitride-based p-channel field-effect transistor with an h-BN insertion layer in Embodiment 1 of the present invention with those of a conventional gallium nitride-based p-channel field-effect transistor using an Al2O3 gate dielectric, it can be seen from the figures that the saturated output currents of the enhanced MIS structure gallium nitride-based p-channel field-effect transistor with an h-BN insertion layer and the gallium nitride-based p-channel field-effect transistor using an Al2O3 gate dielectric are 0.56 mA / mm and 0.08 mA / mm, respectively; the on-resistances are 6.54 kΩ / mm and 10.47 kΩ / mm, respectively. In comparison, the enhanced MIS structure gallium nitride-based p-channel field-effect transistor with an h-BN insertion layer shows an approximately 3-fold increase in saturated output current and a decrease in on-resistance. This significant performance improvement can be attributed to the negative charge density induced by the h-BN / GaN interface polarization effect in the gate region, which increases the areal density of hole carriers in the channel and enhances the carrier conduction capability. Furthermore, the atomically smooth surface of h-BN, free of dangling bonds and charged impurities, enables the formation of high-quality heterojunction interfaces. This high-quality interface characteristic leads to a reduced interface state density, decreasing interface scattering of charge carriers at the channel, thereby achieving higher output current and lower on-resistance, significantly improving the overall performance of the device.

[0106] Figure 4 For V D At 0V, comparing the gate leakage diagrams (semi-logarithmic coordinates) of the GaN-based p-channel field-effect transistor with Al2O3 gate dielectric in Example 1 and the conventional GaN-based p-channel field-effect transistor with Al2O3 gate dielectric, it can be seen from the figure that the gate leakage current of the enhancement-mode MIS structure GaN-based p-channel field-effect transistor with h-BN insertion layer in this example and the conventional GaN-based p-channel field-effect transistor with Al2O3 gate dielectric are 1.2 × 10⁻⁶ and 1.2 × 10⁻⁶, respectively. -14 mA / mm and 3.5×10-9 mA / mm. The gate leakage current was reduced by approximately five orders of magnitude. This significant reduction is primarily attributed to the unique physical properties of h-BN and the characteristics of the h-BN / GaN interface. h-BN possesses an ultra-wide bandgap (approximately 6 eV), effectively blocking leakage current penetration. The wide bandgap of h-BN, combined with p-GaN, forms a higher conduction band level, increasing the electron tunneling barrier width and effectively suppressing Fowler-Nordheim tunneling. The chemical inertness of h-BN blocks surface oxide formation, eliminating deep-level trap states (such as traps related to Ga-O and NO bonds), reducing interface state density, and decreasing trap-assisted tunneling leakage paths. Simultaneously, the atomic-level flatness of h-BN eliminates the local electric field concentration effect of traditional rough interfaces, avoiding the generation of local high-field regions and achieving an exponential decrease in gate leakage current. In contrast, traditional single Al2O3 gate dielectrics, due to the presence of numerous interface traps and high leakage current density, struggle to achieve such low gate leakage current levels.

[0107] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A gallium nitride-based p-channel field-effect transistor with an enhanced MIS structure, characterized in that, The enhanced MIS structure gallium nitride-based p-channel field-effect transistor includes: Substrate (01); A buffer layer (02), a UID-GaN layer (03), a barrier layer (04), and a p-type semiconductor layer (05) are sequentially located on the substrate layer (01). The source electrode (06) and the drain electrode (07) are respectively disposed on opposite sides of the upper surface of the p-type semiconductor layer (05); A gate groove is formed in the p-type semiconductor layer (05) and located between the source electrode (06) and the drain electrode (07). h-BN insertion layer (08) is disposed at the bottom of the gate groove; A dielectric layer (09) covers the h-BN insertion layer (08) and extends to both ends until it covers the entire surface of the p-type semiconductor layer (05) between the source electrode (06) and the drain electrode (07); The gate electrode (10) is disposed above the dielectric layer (09) and corresponds to the position of the gate groove.

2. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The substrate (01) is made of silicon, sapphire or silicon carbide.

3. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The thickness of the GaN buffer layer (02) is 3μm-5μm; The thickness of the UID-GaN layer (03) is 100-500 nm; The depth of the gate groove is 35-75 nm.

4. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The barrier layer (04) is made of AlGaN and has a thickness of 10nm-50nm; the proportion of Al components is between 10-30%.

5. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The p-type semiconductor layer (05) is made of any one of Mg-doped GaN, AlGaN, InGaN, and InN, with a thickness of 40-80 nm; wherein the Mg doping concentration is 1×10⁻⁶. 19 cm -3 ~3×10 19 cm -3 .

6. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The ohmic contact between the source electrode (06) and the drain electrode (07) is made of a Ti / Al / Ni / Au metal stack.

7. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 6, characterized in that: In the Ti / Al / Ni / Au metal stack, the thickness of Ti metal is 20-40 nm, the thickness of Al metal is 120-180 nm, the thickness of Ni metal is 20-50 nm, and the thickness of Au metal is 40-60 nm.

8. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The thickness of the h-BN insertion layer (08) is 2nm-5nm; The dielectric layer (09) is made of aluminum oxide (Al2O3) and has a thickness of 5nm-20nm.

9. The enhanced MIS structure gallium nitride-based p-channel field-effect transistor according to claim 1, characterized in that: The gate electrode (10) is made of Ti / Au multilayer metal, wherein the thickness of Ti metal is 15-25nm and the thickness of Au metal is 80-120nm.

10. A method for fabricating a gallium nitride-based p-channel field-effect transistor with an enhancement-mode MIS structure as described in any one of claims 1-9, the method comprising: Step S1: Provide a substrate layer (01); Step S2: Using metal-organic chemical vapor deposition, GaN buffer layer (02), UID-GaN layer (03), barrier layer (04), and p-type semiconductor layer (05) are epitaxially grown sequentially on substrate layer (01). Step S3: A gate trench with a depth of 35-75 nm is formed in the middle of the p-type semiconductor layer (05) using inductively coupled plasma etching technology; Step S4: Using electron beam evaporation, metal is deposited on both sides of the p-type semiconductor layer (05), and after rapid thermal annealing, ohmic contact source electrode (06) and drain electrode (07) are formed. Step S5: Using chemical vapor deposition, an h-BN insertion layer (08) is applied to the gate groove. Step S6: Using atomic layer deposition technology, a dielectric layer (09) is applied above the h-BN insertion layer (08) and the sidewall of the gate groove, and the dielectric layer extends to both sides along the upper surface of the p-type semiconductor layer (05); Step S7: Deposit metal over the dielectric layer (09) to form a gate electrode (10). Step S8: Etch the dielectric layer (09) and open windows at the corresponding source and drain regions.

Images