A Machine Learning-Based Method and System for Gate Leakage Current Identification in GaN Chips

Abstract

This invention relates to the field of semiconductor device testing technology, and discloses a method and system for identifying gate leakage current in GaN chips based on machine learning. The method includes: applying a test signal to the chip test pads to obtain the physical contact impedance, and calculating the transient time constant by combining it with parasitic capacitance; applying a stepped voltage to the gate of the chip under test to record the leakage current, generating a discrete leakage current sequence; determining the sliding window size based on the transient time constant, fitting and differentiating the leakage current sequence within the window to establish an initial phase space composed of the leakage current and its derivative; performing an affine transformation on the initial phase space using the transient time constant to generate a calibration phase space trajectory; converting the trajectory into a two-dimensional feature matrix and inputting it into a pre-trained machine learning classification model, outputting a predicted probability to trigger sorting. This invention effectively identifies transient charge trapping anomalies caused by deep-level traps by eliminating interference from probe contact impedance fluctuations, reducing the risk of missed detection of potentially faulty chips and misjudgment of normal chips.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, specifically to a method and system for identifying gate leakage current in GaN chips based on machine learning. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, has wide applications in power and radio frequency (RF) devices. Gate leakage current is a key indicator for evaluating the reliability of the gate dielectric and the overall performance of GaN chips. Currently, the industry mainly relies on the static leakage current threshold method for wafer-level chip testing. This method involves applying a constant bias voltage to the gate and measuring whether the steady-state leakage current exceeds a preset standard to screen for defective chips. This static testing method focuses on steady-state response and cannot reflect the dynamic characteristics of the device during switching. It cannot identify transient charge trapping anomalies caused by deep-level traps, which can easily lead to chips with potential reliability issues being missed and flowing into the downstream packaging stage.

[0003] To acquire the dynamic characteristics of devices, the industry has gradually introduced high-frequency transient testing technology. However, in actual wafer mass production testing environments, the repeated piercing action of the probe causes mechanical wear on the probe tip, resulting in random fluctuations in the physical contact impedance between the probe and the chip test pads. This change in contact impedance directly alters the RC time constant of the test link, causing hysteresis and distortion in the transient waveform of leakage current acquired at high frequencies. In subsequent data processing, when extracting transient features such as leakage current derivatives using these waveforms affected by impedance fluctuations, waveform distortion caused by external hardware is treated as a physical characteristic of the chip itself, leading to normal chips being incorrectly identified as defective. Existing testing methods face a technical contradiction between overcoming deep-level trap missed detections and eliminating interference from probe contact impedance fluctuations, making it difficult to balance defect detection rate and yield control. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a GaN chip gate leakage current identification method and system based on machine learning. This solves the problem that existing gallium nitride chip testing methods rely on static leakage current thresholds and cannot identify transient charge trapping anomalies caused by deep level traps, which can easily lead to missed detections of potentially problematic chips.

[0005] The first aspect of this invention provides a machine learning-based method for identifying gate leakage current in GaN chips, comprising the following steps: The wafer probe card is driven to contact the chip test pads, a low-voltage test signal is applied to the chip test pads, the physical contact impedance is extracted, and the transient time constant is calculated by combining the preset test link parasitic capacitance parameters. Segmented electrical stress is applied to the gate of the chip under test according to the set step voltage sequence. During the duration of each voltage step, the gate leakage current is recorded synchronously to generate a time-domain discrete sequence of leakage current. The size parameters of the adaptive sliding window are calculated based on the transient time constant. Within the adaptive sliding window, a polynomial function is fitted to the time-domain discrete sequence of the leakage flow, and the first-order analytical derivative of the fitted function is obtained to acquire the smoothed leakage flow sequence and its corresponding derivative sequence. A two-dimensional initial phase space is established using a smoothed leakage sequence and a derivative sequence. Affine transformation parameters are constructed based on the transient time constant. The coordinate points of the two-dimensional initial phase space are transformed through matrix multiplication mapping operations to generate a calibration phase space trajectory. The calibration phase space trajectory is preprocessed by gridding to generate a two-dimensional feature matrix characterizing the trajectory dwell density. This two-dimensional feature matrix is ​​then input into a pre-trained machine learning classification model to output the predicted probability vector of the chip under test corresponding to different gate dielectric states. The final evaluation result of the chip under test is determined based on the predicted probability vector, and the corresponding physical sorting code is generated based on the final evaluation result to trigger the wafer sorting action.

[0006] In one embodiment of the present invention, the process of extracting physical contact impedance includes: establishing a test loop using Kelvin four-wire measurement logic; controlling the current excitation channel to output a constant current signal in the microamp to milliamp range; forming a local conduction loop between the excitation probe and the monitoring probe residing on the same test pad; during the synchronization of the output constant current signal, acquiring the voltage drop measurement value across the local conduction loop; using the voltage drop measurement value and the constant current signal value for division to obtain the physical contact impedance; and multiplying the physical contact impedance by the pre-determined parasitic capacitance parameter of the test link to obtain the transient time constant. By establishing a local loop on the same test pad, the interference of the system's global parasitic resistance is eliminated, and the transient physical contact state of the probe is obtained.

[0007] In one embodiment of the present invention, the size parameters of the adaptive sliding window are calculated based on the transient time constant, including: calculating a basic smoothing span based on a reference window size constant, a set adjustment coefficient, and the transient time constant; and rounding and oddizing the basic smoothing span to generate a dynamic sliding window length that is always an odd number. Introducing hardware hysteresis into the window size calculation process allows the smoothing span to be dynamically adjusted with the time constant, preventing the fixed window from losing high-frequency characteristics at low impedance or from being insufficiently smoothed at high impedance.

[0008] In one embodiment of the present invention, polynomial function fitting and differentiation are performed on the time-domain discrete sequence of leakage current within an adaptive sliding window. This includes: constructing a polynomial fitting function by performing least squares within a dynamically calculated sliding window, centered on the discrete data point at the current time; obtaining the first-order analytical derivative of the polynomial fitting function; and substituting the discrete time-series nodes into the polynomial fitting function and the first-order analytical derivative function respectively to obtain the smoothed leakage current sequence and the corresponding discrete analytical derivative sequence. Using the analytical derivative instead of direct difference between discrete points reduces the interference of thermal noise from the measurement substrate on the calculation of the rate of change.

[0009] In one embodiment of the present invention, constructing affine transformation parameters and forming a calibration phase space trajectory using transient time constants includes: reading a pre-set non-destructive state reference time constant, calculating the ratio between the two in conjunction with the transient time constant, and limiting the ratio within a preset upper and lower threshold range to obtain a ordinate scaling factor; constructing a two-dimensional affine transformation matrix in diagonal matrix form using the ordinate scaling factor; and multiplying the discrete coordinate point vectors in the initial two-dimensional phase space with the two-dimensional affine transformation matrix to generate a calibration phase space trajectory that compensates for the probe contact impedance hysteresis effect. Matrix operations are used to stretch and compensate the compressed phase space ordinate, eliminating the influence of external test fixture contact impedance fluctuations on the transient rate of change characteristics.

[0010] In one embodiment of the present invention, the calibration phase space trajectory is subjected to gridding preprocessing, including: dividing the coordinate system into proportionally discrete parts according to a preset phase space physical boundary to construct a grid with a fixed resolution; when a single test includes multiple voltage steps, the calibration phase space coordinate points corresponding to each voltage step are sequentially aggregated into the same phase space physical boundary; the number of coordinate point vectors falling into each grid region is counted, and the statistical values ​​are linearly mapped to the interval between 0 and 1 using a maximum-minimum normalization algorithm to generate a fixed-dimensional two-dimensional feature matrix.

[0011] In one embodiment of the present invention, the pre-trained machine learning classification model is a convolutional neural network model. The training process of the convolutional neural network model includes: acquiring historical test data of GaN devices in the same batch and generating a two-dimensional feature matrix set as training samples, and assigning a true label representing a specific physical state to each sample; inputting the training samples into the convolutional neural network model, using the cross-entropy loss function to calculate the error between the predicted probability distribution and the true label, the error calculation being based on the summation of the logarithmic product of the one-hot encoded value of the true label and the predicted probability value output by the model; and iteratively updating the weight parameters using the backpropagation algorithm until the loss value on the validation set converges to within a preset tolerance threshold.

[0012] In one embodiment of the present invention, the process of generating a corresponding physical sorting code based on the final evaluation result includes: selecting the category corresponding to the maximum probability value in the predicted probability vector as the final evaluation result of the chip under test; if the maximum probability value is higher than a preset confidence threshold, then mapping the final evaluation result to a physical sorting code representing a qualified product, a downgraded product, or a failed product; if the maximum probability value is lower than a preset confidence threshold, then assigning a physical sorting code representing a pending re-inspection status.

[0013] In one embodiment of the present invention, after triggering the wafer sorting action, a probe status monitoring action based on transient time constant is further included: recording the transient time constants corresponding to the tested chips according to the chip testing order; removing samples with abnormal open / short circuit failures or those pre-marked as abnormal extreme values; and extracting a fixed number of valid chips to calculate a moving average of the transient time constants; when the moving average exceeds the tolerance upper limit threshold within a preset number of consecutive tests, a hardware interrupt is triggered, the step test sequence is paused, and a probe maintenance warning is issued. Removing abnormal extreme value samples and calculating the moving average avoids interference from single failed chips, achieving preventative monitoring of the probe's mechanical degradation trend.

[0014] A second aspect of the present invention provides a machine learning-based GaN chip gate leakage current identification system, which applies the machine learning-based GaN chip gate leakage current identification method described in the first aspect. The system includes: The test host is equipped with a low-voltage source measurement module, a pulse generation module, and a high-frequency acquisition module. The low-voltage source measurement module is used to perform weak current injection and acquire local loop voltage drop, the pulse generation module is used to output a stepped voltage sequence, and the high-frequency acquisition module is used to capture analog current waveforms at equal intervals. The hardware execution unit includes an automatic card changing device and a wafer probe station, which is used to drive the wafer probe card to align and contact with the chip under test and execute the stepping action of the probe according to the control command. The main control computer communicates with the test host and hardware execution unit via the system bus. The main control computer is equipped with an impedance extraction module, a control acquisition module, an analytical derivative module, a feature extraction module, a defect classification module, and a result sorting module. The impedance extraction module is used to calculate the transient time constant, the analytical derivative module is used for polynomial derivative reconstruction of the adaptive sliding window, the feature extraction module is used for phase space construction and affine transformation calibration, and the defect classification module is equipped with a pre-trained convolutional neural network model.

[0015] This invention provides a method and system for identifying gate leakage current in GaN chips based on machine learning. It has the following beneficial effects: 1. This invention obtains the physical contact impedance by applying a test signal to the chip test pads and calculates the transient time constant. This transient time constant is then used to perform an affine transformation on the initial phase space established by the smoothed leakage current sequence and the derivative sequence to generate a calibration phase space trajectory. This scheme directly performs dynamic calibration and compensation on the leakage current and its rate of change characteristics based on the actual physical contact state of the probe, eliminating the interference of probe mechanical wear and external contact impedance fluctuations on transient characteristics. This effectively avoids misclassifying normal chips as defective products due to changes in test link parameters, thus improving the reliability of test results.

[0016] 2. This invention determines a sliding window based on the acquired transient time constant, and fits and differentiates the discrete leakage current sequence within this sliding window to obtain a smoothed leakage current sequence and derivative sequence. This processing method incorporates the hardware contact state during testing into the data smoothing and differentiation process, enabling the sliding window to adapt to different transient impedance conditions and preventing the loss of high-frequency leakage current characteristics or insufficient smoothing. Simultaneously, by obtaining the rate of change through fitting and differentiation, the interference of measurement thermal noise on transient data extraction is suppressed, providing an accurate data foundation for subsequent phase space construction.

[0017] 3. This invention transforms the calibration phase space trajectory after affine transformation into a feature matrix, which is then input into a machine learning classification model for identification. This model outputs prediction results and triggers physical sorting. This scheme converts the conventional time-domain leakage current waveform into a spatial feature matrix containing the dynamic relationship between leakage current and derivative changes. It effectively captures and exposes transient charge trapping anomalies caused by deep-level traps, solving the problem of existing testing methods relying solely on static leakage current thresholds, which leads to missed detections of potentially defective chips. This reduces the risk of potentially defective gallium nitride chips being shipped out of the factory. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the system architecture of an embodiment of the present invention; Figure 2 This is a flowchart of a leakage current identification method according to an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the physical parameter extraction principle of an embodiment of the present invention. Figure 4 This is a timing diagram of electrical stress application and data acquisition according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the data reconstruction and analytical differentiation principle of an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating the phase space construction and calibration principle of an embodiment of the present invention; Figure 7 This is a structural diagram of defect diagnosis and model reasoning in an embodiment of the present invention; Figure 8This is a flowchart illustrating the test result sorting and system closed-loop feedback of an embodiment of the present invention. Figure 9 This is a comparison diagram of the phase space trajectory before and after calibration according to an embodiment of the present invention; Figure 10 This is a prediction confusion matrix diagram of the model in an embodiment of the present invention; Figure 11 This is a bar chart comparing the test results of embodiments of the present invention.

[0019] Among them, 10 is the test host; 11 is the pulse generation module; 12 is the high-frequency acquisition module; 20 is the automatic card changing device; 30 is the wafer probe card; 40 is the main control computer; 41 is the impedance extraction module; 42 is the control acquisition module; 43 is the analytical differentiation module; 44 is the feature extraction module; 45 is the defect classification module; 46 is the result sorting module; and 50 is the wafer probe station. Detailed Implementation

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] See attached document Figure 1 , Figure 1 This is a schematic diagram of a system architecture according to an embodiment of the present invention. The present invention provides a machine learning-based GaN chip gate leakage current identification system, which may include: Test host 10; Test host 10 includes a hardware body with parameter configuration and test execution capabilities. Test host 10 is equipped with a pulse generation module 11, a high frequency acquisition module 12 and a low voltage source measurement module 13. The low voltage source measurement module 13 is used to output a safe low stress current or voltage signal before strong electrical stress is applied, and to acquire the corresponding voltage or current response so that the impedance extraction module 41 can calculate the actual physical contact impedance.

[0022] Automatic card changing device 20, wafer probe card 30, and wafer probe station 50; Automatic card changing device 20 provides loading, locking, and positioning calibration of wafer probe card 30. Wafer probe station 50 includes a support platform, a Z-axis lifting mechanism, and an XY stepping mechanism, used to support the wafer and drive the chip under test to align and contact with the wafer probe card 30, and to perform lifting, stepping, pausing, or maintenance alarm actions according to the control instructions of result sorting module 46.

[0023] The main control computer 40 is connected to the test host 10 via a system bus. The main control computer 40 is equipped with an impedance extraction module 41, a control acquisition module 42, an analytical derivative module 43, a feature extraction module 44, a defect classification module 45, and a result sorting module 46. Each logic processing module calls the underlying computing resources to complete data processing according to the test timing. Among them, the feature extraction module 44 is used to convert the calibrated phase space trajectory into feature data suitable for model input, and the defect classification module 45 is used to output the dielectric state classification result of the chip under test based on the pre-trained machine learning model.

[0024] See attached document Figure 2 , Figure 2 This is a flowchart of a leakage current identification method according to an embodiment of the present invention. The present invention provides a machine learning-based method for identifying gate leakage current in GaN chips, comprising the following steps: S100, the automatic card changing device 20 drives the wafer probe card 30 to contact the chip test pads, the impedance extraction module 41 calls the low voltage source measurement module 13 to apply a low stress impedance test signal within the chip safe working area to the chip test pads, extracts the actual physical contact impedance, and uses the physical contact impedance and the preset test link parasitic capacitance parameters to calculate the transient time constant. S200, the control acquisition module 42 calls the pulse generation module 11 to apply segmented electrical stress to the gate of the chip under test according to the set step voltage sequence. During each voltage step duration period, the control acquisition module 42 calls the high-frequency acquisition module 12 to synchronously record the gate leakage current and generate the original leakage current time-domain discrete sequence. S300, the analytical derivative module 43 calculates the size parameters of the adaptive sliding window based on the transient time constant, performs polynomial function fitting on the original leakage time-domain discrete sequence within the adaptive sliding window, and obtains the first-order analytical derivative of the fitting function to get the smooth leakage sequence and its corresponding derivative sequence. S400, the feature extraction module 44 establishes a two-dimensional initial phase space by utilizing the numerical correspondence between the smooth leakage current sequence and the derivative sequence, and constructs affine transformation parameters using the transient time constant, performing matrix multiplication mapping operation on the coordinate points of the two-dimensional initial phase space to form calibration phase space trajectories under different voltage steps. S500, the defect classification module 45 performs gridding preprocessing on the calibration phase space trajectory output by the feature extraction module 44 to generate a two-dimensional feature matrix characterizing the trajectory space residence density, and inputs the two-dimensional feature matrix into a pre-trained machine learning classification model to output the predicted probability vector of the chip under test corresponding to different gate dielectric states. S600, the defect classification module 45 determines the gate dielectric state of the chip under test based on the predicted probability vector, and the result sorting module 46 generates the corresponding sorting code based on the gate dielectric state, updates the wafer test pattern, and triggers the wafer probe station 50 to perform a lift-up, step-up, or maintenance alarm action.

[0025] See attached document Figure 3 , Figure 3 This is a schematic diagram of physical parameter extraction according to an embodiment of the present invention. Before applying the high electrical stress for leakage current testing, the system performs a test environment initialization operation to establish the basic physical parameters for data processing. In this embodiment, the execution process of step S100 can be specifically divided into the following sub-steps: S110, the main control computer 40 issues an alignment contact command to the wafer probe station 50 through the device control interface. The wafer probe station 50 drives the carrier stage or Z-axis lifting mechanism to move according to the configured stroke parameters, so that the test pad of the chip under test establishes physical electrical contact with the probe array at the bottom of the wafer probe card 30. The automatic card changing device 20 is used to provide mechanical support and positioning reference when changing, locking or calibrating the wafer probe card 30.

[0026] During probe pressing, the inherent clearance of the mechanical transmission structure of the automatic card changing device 20 often introduces a certain degree of mechanical stress deviation. From a physical perspective, this deviation causes a change in the metal contact area between the probe tip and the test pad, resulting in random fluctuations in the electrical connection state of the test link. Based on this objectively existing hardware characteristic, the aforementioned step of extracting the actual physical contact impedance, in the specific embodiment of this invention, is specifically manifested as extracting the actual physical contact impedance value directly affected by the mechanical stress deviation.

[0027] S120, the impedance extraction module 41 injects a low-voltage test signal into the chip test pad and extracts the actual physical contact impedance based on the feedback electrical response.

[0028] As a preferred method, the impedance extraction module 41 calls the low-voltage source measurement module 13 inside the test host 10 and establishes a test loop using Kelvin four-wire measurement logic. The Kelvin four-wire loop separates the current excitation channel and the voltage monitoring channel. The impedance extraction module 41 controls the current excitation channel to output a small current signal with an amplitude within the chip's safe operating area as a low-voltage test signal. To avoid electrical stress damage to the fragile GaN gate during the impedance test phase, the value of this current signal is typically set to the microamplitude to milliamp range, forming a local conductive loop between the excitation probe and the monitoring probe residing on the same test pad. During the synchronization of the constant output current, the voltage monitoring channel collects the voltage drop across this local loop. The impedance extraction module 41 uses the voltage drop measurement value and the constant output current value to perform a division operation to obtain the actual physical contact impedance under the current bonding state. The specific hardware topology of the Kelvin four-wire test circuit and the digital-to-analog conversion sampling process for the small voltage drop can be implemented by those skilled in the art using existing high-precision semiconductor parameter testing hardware architectures. This is a well-known technology in the field and will not be elaborated here.

[0029] S130, the impedance extraction module 41 reads the preset test link parasitic capacitance parameters from the local system configuration file of the main control computer.

[0030] The parasitic capacitance parameter of the test link is the equivalent sum of the inherent stray capacitances of the internal switch matrix of the test host, the external coaxial connection cables, and the internal wiring of the wafer probe card 30 substrate. Without changing the main hardware of the device, this equivalent sum is a fixed constant value, denoted as […]. To ensure the accuracy of this parameter, during the routine calibration phase of the system, those skilled in the art typically use a capacitance tester or network analyzer to perform AC impedance measurement or open-circuit capacitance test on the entire test link under no-load conditions without connecting to the wafer, and pre-write the measured equivalent stray capacitance value into the system configuration file.

[0031] S140, to further quantify the waveform distortion effect caused by contact impedance fluctuations on the transmission of weak high-frequency signals, the impedance extraction module 41 uses the actual physical contact impedance obtained in step S120 and the parasitic capacitance parameters of the test link read in step S130 to perform a product operation, and calculates the transient time constant characterizing the charging and discharging hysteresis characteristics of the current physical link. The specific calculation formula is as follows: ; In the formula, The transient time constant is a measure of the time required for a circuit to transition from a transient, drastic change phase to a steady-state phase when it encounters a step electrical stress. The actual physical contact impedance is extracted online using the Kelvin four-wire system; To test the parasitic capacitance parameters of the link, the impedance extraction module 41 converts the uncertain physical impedance fluctuations introduced by the mechanical joint components into mathematical constants characterizing the sluggishness of the system's high-frequency electromagnetic response through the above calculations, thus establishing the hardware state reference variables required for subsequent data reconstruction and spatial mapping algorithms.

[0032] See attached document Figure 4 , Figure 4 This is a timing diagram of electrical stress application and data acquisition according to an embodiment of the present invention. After completing the initialization of the test environment and the extraction of physical parameters, the system enters the dynamic electrical stress testing phase. In this embodiment, the execution process of step S200 can be specifically divided into the following sub-steps: S210, the control acquisition module 42 reads the test program configuration file inside the main control computer and generates a stepped voltage sequence for driving the test hardware. The aforementioned step of applying segmented electrical stress, in the specific technical solution of this embodiment, is specifically manifested as establishing the starting voltage, ending voltage, voltage step size, and holding time of a single step period.

[0033] To avoid irreversible breakdown damage to the dielectric layer of the test terminals of the chip under test caused by directly applying extreme high voltage, the control acquisition module 42 constructs the electrical stress curve in a step-by-step increasing manner. As a preferred method, the configured stepped voltage sequence is represented in discrete set form as follows: ; In the formula, It is a set of stepped voltage sequences; This is the initial step voltage; To terminate the stepped voltage; This represents the total number of stages in the voltage ladder. Representing the The target voltage amplitude for each step. In typical test scenarios for identifying gate leakage current in GaN devices, the voltage difference between adjacent steps (i.e., the step size) is usually set between a few volts and tens of volts, depending on the required test accuracy. More importantly, the duration of each step voltage is configured to be greater than the charge-discharge settling time caused by parasitic parameters in the test link, to ensure that the steady-state leakage current characteristics of the device can be extracted at each stress stage.

[0034] S220, after establishing a reasonable voltage distribution boundary, the control acquisition module 42 calls the pulse generation module 11 to output the corresponding voltage excitation to the corresponding test terminal of the chip under test according to the generated step voltage sequence.

[0035] The pulse generation module 11 converts the digital sequence into an actual analog square wave level, and transmits the segmented electrical stress to the chip under test area through the physical link between the switch matrix of the test host and the wafer probe card. In this test topology, the non-excitation terminals of the chip under test are preferably kept grounded or connected to a preset reference level, thereby establishing a directional electric field at both ends of the dielectric layer under test.

[0036] S230, at the instant when the pulse generation module 11 outputs each voltage step for synchronization, the control acquisition module 42 sends a hardware trigger command to the high-frequency acquisition module 12 through the backplane bus.

[0037] Upon receiving the trigger command, the high-frequency acquisition module 12 activates its internal analog-to-digital conversion channel. Through the current-to-voltage conversion unit, transimpedance amplifier unit, or sampling resistor link built into the test host 10, it converts the weak gate leakage current in the test circuit into a sampleable voltage signal and then captures data at equal intervals according to a fixed high-frequency sampling rate. To effectively capture the transient charging and discharging process containing the nonlinear characteristics of the device, this high-frequency sampling rate is typically set to the range of 1MSPS to 10MSPS. During this process, due to the transient response of stray capacitance in the test link and environmental electromagnetic interference, the actual captured electrical signal often contains background high-frequency noise from the system. The high-frequency acquisition module 12 converts the captured analog current waveform into a digital quantity, forming the second... The original time-domain discrete sequence of leakage current corresponding to each voltage step. The mathematical expression of this sequence is: ; In the formula, Indicates the first Leakage current sequence acquired under voltage step excitation; The first on the sampling time axis A discrete time node; The range of values ​​is , The total number of sampling points within a single voltage step cycle is equal to the product of the hold time and the sampling rate. For the selection of the high-resolution analog-to-digital converter circuit and the clock synchronization trigger routing control within the high-frequency acquisition module 12, those skilled in the art can implement it using readily available commercial high-speed semiconductor test instrument boards based on the test bandwidth requirements. The underlying hardware topology is well-known in the field and will not be elaborated upon here. After a single step cycle, the high-frequency acquisition module 12 temporarily stores the original leakage current time-domain discrete sequence in system memory, providing the basic raw data source for subsequent polynomial smoothing and denoising.

[0038] See attached document Figure 5 , Figure 5This is a schematic diagram illustrating the data reconstruction and analytical differentiation principle according to an embodiment of the present invention. After obtaining the original leakage current sequence containing high-frequency background noise of the system, the system needs to extract the rate of change features of the signal to construct a multi-dimensional phase space. Since conventional adjacent-point difference operations tend to amplify high-frequency noise, thereby affecting the extraction of transient features of the device, this embodiment uses a method combining dynamic reconstruction and analytical operations to process the data. The execution process of step S300 can be specifically divided into the following sub-steps: S310, the analytical derivative module 43 establishes the mathematical mapping relationship of the dynamic sliding window based on the transient time constant obtained in step S100.

[0039] In calculating the size parameters of the adaptive sliding window, this embodiment constructs a window scaling calculation logic that is controlled by the physical link hysteresis state. The specific algebraic equation is as follows: ; In the formula, The sliding window length is dynamically calculated based on the number of sampled data points, and after processing by the above formula, it is always an odd number to ensure the symmetry of window truncation. This is a baseline window size constant used to ensure the basic smoothness of the algorithm under ideal conditions; its value is usually set between 5 and 15 sampling points. The adjustment coefficient characterizes the influence weight of the time constant on the window size. Its value, together with the sampling rate Fs, determines the conversion ratio of the time constant to the number of sampling points. Those skilled in the art can obtain this constant through the previous standard resistor array calibration test. The transient time constant is calculated in the preceding steps; This indicates a rounding down operation. When the probe contact impedance increases, causing the transient response of the test link to become sluggish, the calculated window size is increased accordingly to enhance the suppression of low-frequency random disturbances; when the contact condition is good, the system automatically shrinks the window to retain high-frequency transient change characteristics.

[0040] S320, after establishing the local data extraction range, the analytical differentiation module 43, centered on the discrete data point at the current moment, extracts data within a length of... A polynomial function is fitted to the original leaky time-domain discrete sequence within a sliding window.

[0041] The polynomial function aims to construct a continuous mathematical model that approximates the actual physical change trend within a local discrete time interval. To address the potential data boundary overflow issue that may occur when the sliding window traverses to the beginning and end of the sequence, the analytical differentiation module 43 employs a boundary filling method using edge data mirroring to avoid processing dead zones at the ends of the sequence. The constructed continuous fitting function is expressed as: ; In the formula, For the first A locally continuous polynomial fitting function constructed under each voltage step; It is a continuous-time variable; Let the order be the order of the polynomial. Let represent the coefficients of the polynomial to be solved. To balance data reconstruction accuracy with processor overhead, and to avoid data divergence at the window edges caused by high-order polynomials, the order of the polynomial is chosen as a preferred approach. The value is usually set to 2 or 3. The analytical derivative module 43 uses the least squares method to perform matrix operations on the original discrete sampled data within the window, calculating the coefficients of each term. The specific derivation process of the least squares method for solving local data can be implemented by those skilled in the art with reference to standard numerical analysis theory. It is a well-known technique in this field and will not be elaborated here.

[0042] S330, after completing the reconstruction of the continuous function in the local interval, the analytical derivative module 43 directly calculates the first-order analytical derivative of the continuous fitting function of the polynomial.

[0043] When obtaining the first-order analytic derivative, this is specifically manifested in extracting the rate of change expression of the polynomial according to the rules of calculus. The mathematical formula for this operation is: ; In the formula, This is the first-order analytical derivative function generated after differentiating the locally continuous fitting function. Analytical differentiation module 43 converts the discrete time series nodes... Substituting the values ​​into the continuous fitting function and the first-order analytic derivative function respectively, the denoised discrete smoothed leakage sequence is calculated. and the corresponding discrete analytic derivative sequence This reconstruction step utilizes the analytical derivative properties of continuous functions to extract the rate of change, replacing discrete difference operations at the underlying algorithm level. This maintains the signal's inherent characteristics while suppressing high-frequency noise amplification in weak current testing environments, providing a two-dimensional discrete data source with a high signal-to-noise ratio for subsequent phase space construction.

[0044] See attached document Figure 6 , Figure 6 This is a schematic diagram of phase space construction and calibration according to an embodiment of the present invention. After smoothing and analytically differentiating the data, the system transforms the one-dimensional time-domain signal into a two-dimensional phase space to extract topological features that reflect the nonlinear dynamic evolution of leakage current. To address the trajectory distortion problem that may be caused by probe contact impedance fluctuations, this embodiment introduces an adaptive affine transformation mechanism. The execution process of step S400 can be specifically divided into the following sub-steps: S410, the feature extraction module 44 constructs an initial two-dimensional phase space mapping based on the time series data obtained from the previous processing.

[0045] In practical implementation, the feature extraction module 44 uses the smoothed leakage current value corresponding to each discrete time point as the abscissa and the corresponding analytical derivative value as the ordinate, thereby converting the traditional time-domain rectangular coordinate system into a phase-space coordinate system. The mathematical expression of this mapping process is as follows: ; In the formula, For the first The initial coordinate vectors of discrete time points in two-dimensional phase space; This represents the value of the discrete smoothed leaky sequence at the corresponding time point; This represents the value of the discrete analytic derivative sequence at the corresponding time point; This represents the matrix transpose. Through the above mapping, the discrete sequence originally unfolded on the time axis is transformed into a set of discrete coordinate points arranged in time order in phase space, forming the initial phase space trajectory.

[0046] In S420, the random fluctuations in probe contact impedance will change the total RC time constant of the test link. This physical charging and discharging hysteresis will cause nonlinear scaling distortion on the derivative axis, resulting in chips in the same state exhibiting different phase space trajectories under different contact conditions.

[0047] To eliminate this interference, the feature extraction module 44 calculates the impedance-driven scaling factor of the ordinate and constructs a two-dimensional affine transformation matrix accordingly. When calculating the scaling factor, the system calls the preset lossless state reference time constant in the configuration file. This reference time constant is typically the stable hardware response time constant obtained during routine maintenance of the test system using a standard low-resistivity calibration chip or a reference wafer pad in good contact condition, denoted as... ,and The value should be greater than the preset minimum effective threshold to avoid abnormal amplification in subsequent ratio calculations. Specifically, technicians apply a standard step voltage signal to the short-circuit calibration chip, record the charge-discharge response curve of the system's inherent test link, and then extract the time constant representing the pure hardware parasitic effect through exponential decay fitting. As a preferred method, to avoid the calculated compensation coefficient diverging due to abnormal contact conditions (such as probe contamination or suspension), a reasonable engineering limiting boundary is usually set for this factor. The feature extraction module 44 performs a ratio calculation between the transient time constant obtained in step S100 and the non-destructive state reference time constant, and combines it with the limiting logic to obtain the scaling factor. : ; In the formula, The scaling factor for the ordinate; This represents the transient time constant of the current test link; and These are the lower and upper limits of the scaling factor for the vertical axis, respectively. Those skilled in the art can set these limits based on the typical wear patterns of the probe card and the system's tolerable impedance fluctuations. For example, this range is typically set between 0.5 and 5.0. Under test conditions where the gate leakage current is small and the output internal resistance and series voltage drop of the test source are negligible relative to the gate excitation voltage, it can be approximated that the contact impedance mainly affects the rate of change of transient charge and discharge, i.e., the vertical axis of the phase space, while having a smaller impact on the final steady-state amplitude of the leakage current, i.e., the horizontal axis of the phase space. Based on this physical characteristic, the feature extraction module 44 constructs a two-dimensional affine transformation matrix in the form of a diagonal matrix: ; In the formula, This is a two-dimensional affine transformation matrix. This matrix configuration ensures that, in subsequent spatial transformations, the leakage magnitude dimension maintains an identical mapping, while the rate of change dimension receives adaptive compensation.

[0048] S430, after obtaining the affine transformation matrix, the feature extraction module 44 performs a calibration trajectory generation operation to eliminate hardware hysteresis.

[0049] In this embodiment, the feature extraction module 44 multiplies the discrete coordinate point vectors in the initial two-dimensional phase space with the two-dimensional affine transformation matrix to complete the linear mapping of spatial coordinates. The specific calculation formula is as follows: ; In the formula, This is the calibrated phase space coordinate vector. After this matrix transformation, the rate of change attenuation due to increased contact impedance is scaled by a scaling factor. Corresponding compensation was performed. The feature extraction module 44 connects the calibrated coordinate point vectors in chronological order to generate the calibrated phase space trajectory. This underlying compensation mechanism based on physical parameters eliminates the interference of mechanical stress fluctuations on electrical signal characteristics from the source, ensuring that the finally extracted phase space topology can more objectively characterize the leakage current characteristics of the dielectric layer of the chip under test.

[0050] See attached document Figure 7 , Figure 7 This is a structural diagram of defect diagnosis and model inference according to an embodiment of the present invention. Through preliminary steps, a calibration phase space trajectory to eliminate hardware hysteresis is generated. The system further performs pattern recognition on the topological features implicit in this trajectory to evaluate the physical state of the gate dielectric layer of the chip under test. To achieve the extraction and classification of nonlinear trajectory features, this embodiment introduces a deep learning evaluation mechanism based on convolutional neural networks. The execution process of step S500 can be specifically divided into the following sub-steps: S510, the defect classification module 45 performs a gridding preprocessing operation on the calibration phase space trajectory output in step S400. When a test contains multiple voltage steps, the calibration phase space coordinate points corresponding to each voltage step are summarized into the same preset phase space physical boundary for statistical analysis according to the voltage step order, or the weighted merging is performed step by step according to the preset synthesis rules in the training stage, thereby generating a two-dimensional feature matrix consistent with the input format of the training samples.

[0051] Since the original calibration coordinate point set exhibits a continuous yet irregular distribution in phase space, it cannot be directly used as input to a deep learning model. Therefore, the defect classification module 45 proportionally discretizes the coordinate system based on a preset phase space physical boundary. The phase space physical boundary can be determined by the upper and lower statistical limits of the smoothed leakage current values ​​and analytical derivative values ​​in the training sample set. Alternatively, it can be pre-written into a configuration file based on the current range, sampling bandwidth, and allowable derivative variation range set in the test program. For coordinate points exceeding the phase space physical boundary during online testing, the defect classification module 45 performs boundary clipping, anomaly counting, or mapping to edge grids according to preset rules to ensure that all test samples can form a fixed-size two-dimensional feature matrix, thereby ensuring that online test samples and training samples use the same coordinate mapping scale. Specifically, the system divides the horizontal and vertical coordinate axes of the phase space into grids with fixed resolution and statistically analyzes the discrete coordinate point vectors falling within each grid region. The number of elements is used to construct a two-dimensional feature matrix representing the stationary density in the trajectory space. As a preferred approach, the dimension of this matrix is ​​set to [value missing]. G, typically taken as 64×64 in engineering, represents the number of columns in the two-dimensional feature matrix, distinguishing it from the aforementioned sliding window length. To avoid excessively large data volume spans due to differences in the total sampling volume across different test cycles, the defect classification module 45 further employs a max-min normalization algorithm to linearly map the values ​​of each element within the matrix to the range of 0 to 1. In this normalized matrix, the value of each pixel element corresponds to the residence time ratio of the trajectory under specific leakage current amplitude and rate of change, quantitatively characterizing the dynamic balance state of charge trapping and release within the device. For example, when there are many deep-level trap defects within the dielectric layer, the delayed release effect of charge will form specific distortion hysteresis loops in the phase space. These loops will form high-density clusters in specific coordinate regions of the two-dimensional matrix, thus providing intuitive morphological features for the model.

[0052] S520, after obtaining the standardized two-dimensional feature matrix, the defect classification module 45 inputs it into the pre-built convolutional neural network model for feature forward propagation.

[0053] The convolutional neural network model in this embodiment mainly includes an input layer, alternating cascaded convolutional and pooling layers, a fully connected layer, and a classification output layer in its internal hierarchical structure. As one possible implementation, the input layer receives a 64×64 single-channel two-dimensional feature matrix. The first convolutional layer uses a 3×3 convolutional kernel to extract local trajectory density features. The first pooling layer uses 2×2 max pooling to reduce the feature dimension. The second convolutional layer continues to extract higher-order topographic features such as hysteresis loops, divergent branches, and local density abrupt changes. These features are then mapped to a one-dimensional feature vector by the fully connected layer, and the Softmax classification output layer generates probability values ​​for each gate dielectric state category. In terms of module connectivity and data flow, after the two-dimensional feature matrix enters the input layer, it flows through a convolutional layer composed of multiple sets of two-dimensional convolutional kernels. Nonlinear activation functions such as ReLU are used to abstract the geometric topological features in the matrix, such as trajectory closures and divergent branches, generating a high-dimensional feature map. The pooling layer (usually using max pooling) immediately follows the convolutional layer to perform a downsampling operation to reduce the feature dimension while retaining the main texture information. After multiple feature extractions and dimensionality reductions, the data stream enters the fully connected layer and unfolds into a one-dimensional feature vector, which is then mapped to the classification output layer through the Softmax activation function.

[0054] S530, In response to the technical requirements of model construction and parameter optimization, this embodiment discloses the specific training steps of the convolutional neural network.

[0055] Before model deployment, technicians collected a large amount of historical test data from GaN devices of the same batch with known health conditions. Following the same impedance extraction, data reconstruction, and phase space calibration steps as described above, a two-dimensional feature matrix set was generated as training samples. The sampling rate, sliding window calculation rules, phase space physical boundaries, grid resolution, normalization methods, and multi-voltage step trajectory merging rules used in the training phase were ensured to remain consistent with those used in the online testing phase. Simultaneously, based on destructive physics analysis or long-term aging test results, each sample was assigned a true physical state label representing specific business implications. These labels are represented in one-hot encoded form, covering categories such as normal state, dielectric layer micro-trap defects, and critical breakdown precursors. During training, the model uses the cross-entropy loss function to calculate the error between the predicted probability distribution and the true labels. The formula for calculating the cross-entropy loss function is: ; In the formula, This represents the cross-entropy loss value. The total number of physical state categories is preset, and its value is usually set to 3 to 5 categories according to the specific needs of the actual business scenario. For the real label in the first The one-hot encoding value for a class is set to 1 if the sample belongs to that class, and 0 otherwise. (Or marked as predicted value parameters) represents the sample output by the model that belongs to the first... The predicted probability value for the class. The model uses the Adam optimizer or stochastic gradient descent optimizer, and uses the backpropagation algorithm to iteratively update the weight parameters of the convolutional kernel and fully connected layer using this loss value. When the loss value converges to within a preset tolerance threshold (typically between 0.01 and 0.05) on the validation set, the iteration stops and the model parameters are frozen, completing the model training.

[0056] S540, in a real online testing environment, the defect classification module 45 uses the convolutional neural network model trained and converged through the above steps to generate a prediction probability vector for the current chip under test.

[0057] The predicted probability vector output by the classification output layer contains Each element corresponds to the probability of occurrence of each physical state category. The defect classification module 45 selects the category corresponding to the maximum probability as the final evaluation result of the chip under test. When the maximum probability is lower than the preset confidence threshold, the defect classification module 45 marks the chip under test as a retest or manual review state and sends this state to the result sorting module 46, so that the result sorting module 46 can generate the corresponding BIN code and wafer prober control command. Through this reasoning process, the system transforms the abstract leakage phase space evolution law into an intuitive diagnostic conclusion. This scheme not only helps to screen out devices that have undergone obvious degradation, but also provides an objective reference for identifying early-stage chips with potential trap defects in the dielectric layer, thereby expanding the evaluation dimensions of semiconductor parameter testing.

[0058] To ensure data consistency between the model training and online testing phases, in this embodiment, the main control computer 40 manages the sampling rate, stepped voltage sequence, sliding window calculation parameters, phase space physical boundary, grid resolution, normalization method, multi-voltage stepped trajectory merging rules, and the number of model input channels as a single test recipe file. Training sample generation, model validation, and online inference all utilize the same parameters from this test recipe file to avoid classification result shifts due to inconsistent preprocessing scales.

[0059] See attached document Figure 8 , Figure 8 This is a flowchart of test result sorting and system closed-loop feedback according to an embodiment of the present invention. After completing the deep learning-based dielectric layer defect diagnosis, the system needs to convert the aforementioned classification and evaluation results into actual action commands for the wafer probe station to achieve overall automated operation of wafer-level testing. This embodiment completes the end of the test cycle and status reset by constructing a multi-level sorting mapping and hardware status monitoring mechanism. The execution process of step S600 can be specifically divided into the following sub-steps: S610, the result sorting module 46 receives the final evaluation result output by the defect classification module 45 and generates the corresponding physical sorting code according to the preset yield grading specification.

[0060] In the specific implementation of generating sorting codes and control instructions, this embodiment maps the physical state classification labels obtained from the classification output layer to the BIN code format commonly used in semiconductor manufacturing. The result sorting module 46 internally stores a static mapping table. When the final evaluation result is normal, it is assigned the BIN1 code representing a qualified product; when the evaluation result is an early hidden danger such as a microscopic trap defect in the dielectric layer, it is assigned the BIN2 code representing degraded use; when the evaluation result is a critical breakdown precursor or already damaged, it is directly assigned the BIN9 code representing a failed product; when the evaluation result is a retest or manual verification state, it is assigned the BIN3 code representing pending re-inspection. This mapping process transforms the classification vector output by the neural network into discrete instruction identifiers that the wafer sorting machine can directly recognize and call.

[0061] After establishing the sorting code of the chip under test, the sorting module 46 updates the wafer test pattern inside the main control computer and sends equipment control commands to the wafer probe station.

[0062] The testing system writes the generated BIN code into the corresponding coordinate array of the wafer test pattern based on the two-dimensional physical coordinates of the current chip, thereby realizing the visualization and data persistence of the yield distribution of the entire wafer. Simultaneously, the result sorting module 46 sends lift and step commands to the wafer probe station via the communication interface, driving the robotic arm to move the test probe above the pads of the next chip under test. The underlying communication handshake protocol between the main control computer and the wafer probe station, as well as the closed-loop drive control of the stepper motor, can be implemented using the standard SECS / GEM semiconductor device communication standard by those skilled in the art. The underlying hardware control logic is well-known in the field and will not be elaborated upon here.

[0063] To ensure data reliability in large-scale continuous testing scenarios, the S630 result sorting module 46 introduces a probe status monitoring and self-maintenance mechanism based on historical transient time constants.

[0064] In the stage of triggering the closed-loop feedback of the system, the system determines the degree of wear or contamination of the physical probe by tracking the drift trend of the contact impedance. The result sorting module 46 maintains a local transient time constant history cache table, which records the corresponding data for each tested chip according to the chip testing order. The system calculates the moving average of the transient time constant of a fixed number of recently tested valid chips (excluding samples with abnormal open / short circuit failures or those pre-marked as abnormal extreme values) and their wafer coordinates. To address the algorithm dead zone problem in the early stages of single-wafer testing, where insufficient tested chips lead to data overflow within the fixed moving window, the system employs an adaptive length mean calculation logic. The mathematical formula for this calculation logic is: ; In the formula, This is the moving average of the transient time constant within the dynamic window; The actual number of samples used in the calculation is [value to be filled in]. , This represents the total number of chips that have completed testing on the current wafer. The maximum evaluation sample window length is typically set between 50 and 200 as a preferred method. For the first The actual transient time constant extracted during chip testing.

[0065] The sorting module 46 then compares the moving average value with the system's preset tolerance upper limit threshold in real time. This tolerance upper limit threshold is typically based on the non-destructive state reference time constant obtained from the preceding steps. To perform the scaling up, those skilled in the art can set it according to the probe card material and process tolerance. 3 to 5 times. When the moving average is in a continuous If the tolerance threshold is exceeded in all test cycles, then... The preset alarm confirmation count, preferably 3 to 5 times, indicates that excessive oxide may have accumulated at the probe tip or structural deformation may have occurred. At this point, the affine transformation algorithm in step S400 alone is insufficient to fully compensate for severe physical distortion. The system then triggers a hardware interrupt, pausing the wafer probe station's step-by-step test sequence and automatically invoking the probe cleaning program or sending a probe card maintenance alarm to the operating terminal. This device self-maintenance logic based on real-time electrical parameters enables the test system to proactively warn of probe mechanical degradation, helping to reduce the continuous generation of invalid test data.

[0066] Taking the automated sorting (WaferSort) process of a 6-inch p-GaN gate HEMT wafer in a certain wafer fab as an example, this paper elaborates on the closed-loop execution process of the system in a real production line environment.

[0067] Probe residence and background physical quantity determination: The wafer probe stage steps over the chip under test at coordinates (X:12, Y:34) and completes Z-axis bonding. To avoid potential damage to the gate from strong electrical stress, the low-voltage source measurement module uses Kelvin four-wire logic, applying 10... A weak DC injection establishes a local loop between the excitation probe and the monitoring probe residing on the same test pad. The voltage channel synchronously captures a tiny voltage drop of 5.0mV at this interface, from which the impedance extraction module calculates the actual physical contact impedance. Retrieve the system's stray capacitors stored in the configuration file. Calculate the transient time constant of the current link. At this point, the lossless reference time constant at the system's underlying layer... Calibrated as This indicates that the probe tip has a certain degree of mechanical wear or oxide contamination.

[0068] High-frequency step stress and polynomial optimization: The pulse generation module applies a step stress sequence to the gate with an initial voltage of 1V, an ending voltage of 6V, and a step size of 1V, with each step dwelling for 10ms. The high-frequency acquisition module synchronously captures the leakage current at a sampling rate of 1MSPS, extracting 10,000 discrete time points for each voltage step. During the data reconstruction phase, the analytical differentiation module... This physical hysteresis dynamically widens the reference window size from the theoretically ideal 11 sampling points to 15. Within this window, a second-order polynomial approximation is performed on the local scattered points, and the analytical derivative is directly extracted. This adaptive mechanism not only filters out high-frequency thermal noise in the system background but also fully preserves the transient rate-of-change edges that reflect the nonlinear characteristics of the dielectric layer.

[0069] Phase space manifold calibration (in conjunction with appendix) Figure 9 ): Combined with appendix Figure 9 The phase space trajectory evolution shows that the impedance distortion introduced by the wear of this batch of probes causes significant nonlinear compression of the original trajectory on the vertical axis (rate of change of derivative) (as shown in the attached figure). Figure 9 As shown by the dashed line trajectory with a cross in the image, this kind of external hardware interference can directly mask the intrinsic minor defect characteristics of the device.

[0070] Therefore, the feature extraction module calculates the scaling factor based on the ratio of the preceding time constant. Affine transformation matrix with diagonal elements [1, 2, 0] is constructed. This matrix performs linear stretching on the distorted coordinates, eliminating the masking effect of mechanical contact degradation on the high-frequency response and restoring the calibrated manifold topology (as shown in the attached figure). Figure 9 (As shown by the solid line trajectory with circles in the middle), enabling the calibration phase space to purely map the charge trapping and releasing dynamics of the internal lattice.

[0071] Density characterization and physical sorting: The calibration coordinate set is meshed and mapped to After the feature density matrix is ​​calculated, it is fed into a convolutional neural network for forward computation. The final classification state vector output by the Softmax layer is: [Normal: 0.04, Early Trap Defect: 0.95, Failure: 0.01]. The sorting module determines that the dielectric layer has an early trap defect based on extreme value optimization, writes the downgrade sorting code BIN2 to the current coordinate of the wafer map, and then issues a lifting command, and the robotic arm enters the testing cycle for the next chip.

[0072] Experimental verification and engineering effect analysis: To verify the industrial applicability of the aforementioned compensation mechanism and topology classification algorithm, the applicant conducted a comparative evaluation using 1000 p-GaN chips from the same batch, conducted within a standard semiconductor testing environment (ATE). The experiment subjected all chips that had completed classification and evaluation to long-term high-temperature gate bias (HTGB, stress conditions: 150℃). An aging test lasting 1000 hours was conducted, and the actual degradation and breakdown results after HTGB were used as the gold standard for reverse retrospective analysis.

[0073] The control group was set up as follows: Option A (Traditional Static Leakage Method): Only reads the steady-state current at the end of the step jump, bypassing... The threshold is used to determine whether to block.

[0074] Option B (Phase Space Difference + Conventional Machine Learning): Constructs a two-dimensional space by taking the derivative of the difference between adjacent points, without superimposing the time constant affine calibration, and directly feeds it into the support vector machine for classification.

[0075] Scheme C (Technical Architecture of the Invention): Adaptive analytical differentiation is adopted, and impedance affine compensation and CNN inference are superimposed.

[0076] Classification accuracy and failure tracing (in conjunction with appendix) Figure 10 With appendix Figure 11 ): The quantitative comparison data and macro performance are attached. Figure 11 The bar chart shows the distribution. Scheme A, due to extreme dimensionality reduction of the test waveform (only looking at the steady-state amplitude), completely loses the ability to perceive the transient hysteresis effect caused by deep-level traps inside the gate, resulting in up to 18.2% of early defective chips entering the qualified product pool (extremely high risk of false negatives). Scheme B, while capturing dynamic characteristics, lacks a decoupling mechanism for probe link impedance drift, easily misjudging the physical response hysteresis of the test hardware as leakage anomalies in the device itself, causing a 4.3% unwarranted false negative in yield.

[0077] In contrast, this application (Scheme C), by forcibly removing the parasitic variables of the test fixture at the underlying level, achieves an overall recognition accuracy that climbs and stabilizes at 98.7%. Further observation of the appendix... Figure 10 The confusion matrix predicted by the model of this invention demonstrates extremely high convergence along the main diagonal. In particular, when defining the fuzzy transition state of "BIN2 (potential danger)," the CNN network can accurately extract the subtle divergent texture of the closed-loop branch of the trajectory after affine calibration. Only a very few edge samples at the physical critical state cross the classification boundary, which not only eliminates false positives caused by fluctuations in measurement hardware, but also constructs a highly reliable wafer-level reliability screening defense line.

[0078] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A machine learning-based method for identifying gate leakage current in GaN chips, characterized in that, include: A test signal is applied to the chip test pad to obtain the physical contact impedance, and the transient time constant is calculated in combination with the preset parasitic capacitance parameters; A stepped voltage is applied to the gate of the chip under test and the leakage current is recorded to generate a discrete sequence of leakage current. A sliding window is determined based on the transient time constant. Within the sliding window, the discrete leakage sequence is fitted and differentiated to obtain a smoothed leakage sequence and a derivative sequence. An initial phase space is established using the smoothed leakage sequence and the derivative sequence, and an affine transformation is performed on the initial phase space according to the transient time constant to generate a calibration phase space trajectory; The calibration phase space trajectory is converted into a feature matrix and input into a machine learning classification model. The model outputs a predicted probability vector and generates a physical sorting code to trigger the sorting action.

2. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The step of applying a test signal to the chip test pad to obtain the physical contact impedance and calculating the transient time constant in combination with preset parasitic capacitance parameters includes: A constant current signal is output from the Kelvin four-wire control current excitation channel as the test signal, forming a local conduction loop between probes residing on the same chip test pad; The voltage drop across the two ends of the local conduction loop is collected; The physical contact impedance is obtained by dividing the voltage drop across the two ends by the value of the constant current signal. The transient time constant is obtained by multiplying the physical contact impedance by the parasitic capacitance parameter.

3. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, Determining the sliding window based on the transient time constant includes: The basic smooth span is calculated based on the baseline window size constant, the adjustment coefficient, and the transient time constant. The basic smooth span is then rounded and oddized to generate a size parameter that is always an odd number, which is used as the length of the sliding window.

4. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The step of fitting and differentiating the discrete leakage sequence within the sliding window to obtain a smoothed leakage sequence and a derivative sequence includes: Using the discrete data point at the current moment as the center, the least squares method is performed within the sliding window to construct a polynomial fitting function; The first-order analytic derivative function of the polynomial fitting function is obtained; Substituting the discrete time series nodes into the polynomial fitting function and the first-order analytic derivative function respectively, the smoothed leakage sequence and the corresponding derivative sequence are obtained respectively.

5. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The step of generating a calibration phase space trajectory by performing an affine transformation on the initial phase space based on the transient time constant includes: Read the preset reference time constant, calculate the ratio of the transient time constant to the reference time constant, and limit the ratio within a preset threshold range to obtain the vertical axis scaling factor; Construct a two-dimensional affine transformation matrix in diagonal form using the aforementioned scaling factor for the ordinate; The discrete coordinate points in the initial phase space are multiplied by the two-dimensional affine transformation matrix to generate the calibration phase space trajectory.

6. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The step of converting the calibration phase space trajectory into a feature matrix includes: The coordinate system is discretized according to the preset physical boundaries to construct a mesh; The coordinate points in the calibration phase space trajectory are aggregated into the same physical boundary. The number of coordinate points falling into each grid area is counted, and the statistical values ​​are linearly mapped to a preset interval using a normalization algorithm to generate a fixed-dimensional two-dimensional matrix as the feature matrix.

7. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The machine learning classification model is a pre-trained convolutional neural network model, and the training process includes: Historical test data of GaN devices in the same batch are obtained and a two-dimensional feature matrix set is generated as training samples. The training samples are then given real labels that characterize the physical state. The training samples are input into the convolutional neural network model, and the error between the predicted probability distribution and the real label is calculated using the cross-entropy loss function. The error calculation is based on the sum of the logarithmic multiplication of the one-hot encoded value of the real label and the logarithmic multiplication of the output predicted probability value. The weight parameters are iteratively updated using the backpropagation algorithm until the loss value on the validation set converges to within the tolerance threshold.

8. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, The process of outputting a predicted probability vector and generating a physical sorting code to trigger the sorting action includes: The category corresponding to the maximum probability in the predicted probability vector is selected as the evaluation result of the chip under test; If the maximum probability value is higher than the preset confidence threshold, the evaluation result is mapped to a physical sorting code representing qualified products, downgraded products, or defective products. If the maximum probability is lower than the preset confidence threshold, a physical sorting code representing the pending re-examination status is assigned.

9. The GaN chip gate leakage current identification method based on machine learning according to claim 1, characterized in that, After the sorting action is triggered, the method further includes: Record the transient time constants corresponding to the tested chips according to the test order. After removing abnormal open / short circuit failures or samples that have been marked as abnormal extreme values, extract a fixed number of valid chips and calculate the moving average of the transient time constants. When the sliding average value exceeds the tolerance upper limit threshold within a preset number of consecutive times, a hardware interrupt is triggered, the test sequence is paused, and a probe maintenance warning is issued.

10. A GaN chip gate leakage current identification system based on machine learning, employing the GaN chip gate leakage current identification method based on machine learning as described in any one of claims 1 to 9, characterized in that, The system includes: The test host is equipped with an active measurement module, a pulse generation module, and an acquisition module, which are used to perform test signal injection and capture leakage current. The hardware execution unit includes a wafer probe station for driving the probes to perform step contact actions; The main control computer is communicatively connected to the test host and the hardware execution unit via a system bus. The main control computer is equipped with an impedance extraction module, an analytical derivative module, a feature extraction module, and a defect classification module. The impedance extraction module is used to calculate the transient time constant, the analytical derivative module is used to generate a smoothed leakage current sequence and a derivative sequence, the feature extraction module is used to generate a feature matrix, and the defect classification module is equipped with the machine learning classification model to output a predicted probability vector and generate a physical sorting code.

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