A novel silicon-on-insulator wafer and its fabrication method
By fabricating TRL or porous silicon on silicon wafers and injecting hydrogen, combined with low-temperature bonding and high-temperature stripping methods, the problems of large back gate leakage current and poor SiO2 step coverage in radio frequency circuits were solved, resulting in lower back gate leakage current and a smoother surface.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-12-25
- Publication Date
- 2026-06-30
AI Technical Summary
Existing RF circuits suffer from large back-gate leakage current, which affects the back-gate control capability. At the same time, the SiO2 grown by the deposition process has poor step coverage, low surface flatness, and slow yield.
A novel silicon-on-insulator (SiO2) wafer is prepared by fabricating TRL or porous silicon on a silicon wafer and implanting hydrogen to form a hydrogen-implanted silicon wafer. Then, a novel silicon-on-insulator wafer is prepared by low-temperature bonding and high-temperature peeling, including growing SiO2 as a BOX on the substrate and forming a smoother interface by thermal oxidation.
It achieves lower back gate leakage current capability, improves back gate control capability, and forms a smoother, flatter, and more uniform bonding surface.
Smart Images

Figure CN117594522B_ABST