Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, which comprises the following steps: providing a substrate comprising an array region and a peripheral region; forming a target layer, a pattern transfer layer, a first pattern mask layer and a second pattern mask layer; forming a sacrificial layer on the sidewall of the first pattern mask layer and the second pattern mask layer, and forming a first filling layer filling the first gap between the sacrificial layers; removing the first filling layer, the first pattern mask layer and the second pattern mask layer, and retaining the sacrificial layer, the first gap, the second gap replacing the first pattern mask layer and the second pattern mask layer; forming a second filling layer filling the first gap and the second gap; etching the sacrificial layer based on the second filling layer to form an etching pattern, and etching the pattern transfer layer and the target layer based on the etching pattern to form a first pattern target layer in the array region and a second pattern target layer in the peripheral region, so as to improve the pattern defect problem of the array region and the peripheral region in the process of Reverse SADP.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. Background Technology

[0002] Self-Aligned Doubled Patterning (SADP), also known as Sidewall Image Transfer (SIT), is currently the mainstream technology used in advanced manufacturing processes to create closely spaced patterns.

[0003] The SADP fabrication process is characterized by the following steps: After creating the mandrel structure using a first patterning process, gap walls are formed on both sides of the mandrel structure. Subsequently, the mandrel structure is removed, leaving the gap walls as a mask, to etch the underlying material layer not covered by the gap walls. Alternatively, after creating the mandrel structure using a first patterning process, gap walls are formed on both sides of the mandrel structure, and another material layer is formed to fill the remaining gaps between the mandrel structures. Subsequently, the gaps formed by removing the gap walls serve as etching channels to etch the underlying material layer exposed from the gaps. This process is also known as Reverse Self-Aligned Doubled Patterning (Reverse SADP) technology. Furthermore, a second or more patterning processes can be performed to cut or partially remove the pattern defined by the gap walls or mandrel structure, such as Self-Aligned Quadruple Patterning (SAQP) technology. Through the above process, patterns with a target pitch can be produced, which have double the pattern density compared to the pattern defined by the first patterning process (i.e., the mandrel structure).

[0004] However, since semiconductor structures typically include an array region and a peripheral region, which have significant differences in pattern density and height, a loading effect occurs in the fabrication process using SADP or Reverse SADP, causing the target pattern in the array region and the peripheral region to deviate from the expected effect. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and its fabrication method to improve the patterning defects in the array region and peripheral region during the Reverse SADP process.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array region and a peripheral region; forming a target layer covering the top of the substrate and a pattern transfer layer covering the target layer; forming a first pattern mask layer and a second pattern mask layer, the first pattern mask layer being located on the surface of the pattern transfer layer above the array region, and the second pattern mask layer being located on the surface of the pattern transfer layer above the peripheral region, wherein the pattern size in the first pattern mask layer is smaller than the pattern size in the second pattern mask layer, and the pattern density in the first pattern mask layer is greater than the pattern density in the second pattern mask layer; forming a sacrificial layer and a first fill layer, the sacrificial layer at least covering the first pattern mask layer. The sidewalls of the first patterned mask layer and the sidewalls of the second patterned mask layer are formed, and the first filling layer fills the first gap between the sacrificial layers. The first filling layer, the first patterned mask layer and the second patterned mask layer are removed, while the sacrificial layer, the first gap and the second gap replacing the first patterned mask layer and the second patterned mask layer are retained. A second filling layer is formed, which fills the first gap and the second gap, and the top surface of the second filling layer is flush with the top surface of the sacrificial layer. An etching pattern is formed by etching the sacrificial layer based on the second filling layer, and a pattern transfer layer is etched based on the etching pattern. The etching pattern is transferred to the target layer along the etched pattern transfer layer to form a first pattern directly above the array region and a second pattern directly above the peripheral region on the surface of the target layer.

[0007] In some embodiments, the ratio of the thickness of the sacrificial layer on the sidewall of the first pattern mask layer to the width of the sidewall of the first pattern mask layer ranges from 1:2 to 1:10.

[0008] In some embodiments, the width of the first gap located directly above the array region is equal to the width of the second gap.

[0009] In some embodiments, forming a first pattern mask layer and a second pattern mask layer includes: forming a mask layer covering the top surface of a pattern transfer layer; forming a first pattern photoresist on the mask layer; and patterning the mask layer located directly above an array region based on the first pattern photoresist to form the first pattern mask layer; forming a second pattern photoresist on the mask layer; and patterning the mask layer located directly above a peripheral region based on the second pattern photoresist to form the second pattern mask layer.

[0010] In some embodiments, forming a sacrificial layer and a first fill layer includes: forming an initial sacrificial layer that covers the top surface and sidewalls of a first pattern mask layer and the top surface of a pattern transfer layer exposed by the first pattern mask layer, and covers the top surface and sidewalls of a second pattern mask layer and the top surface of a pattern transfer layer exposed by the second pattern mask layer; forming an initial first fill layer that fills the gaps between the initial sacrificial layers and covers the top surface of the initial sacrificial layer; removing a portion of the height of the initial sacrificial layer and the initial first fill layer to expose the top surfaces of the first pattern mask layer and the second pattern mask layer, with the remaining initial sacrificial layer serving as the sacrificial layer and the remaining initial first fill layer serving as the first fill layer.

[0011] In some embodiments, after forming the initial sacrificial layer and before forming the initial first fill layer, the method further includes: removing the initial sacrificial layer from the top surfaces of the first pattern mask layer and the second pattern mask layer, as well as the initial sacrificial layer located on the surface of the pattern transfer layer; forming the initial first fill layer further includes: the initial first fill layer covering the surface of the pattern transfer layer and the top surfaces of the first pattern mask layer and the second pattern mask layer.

[0012] In some embodiments, removing a portion of the initial height of the initial sacrificial layer and the initial first fill layer includes: removing a portion of the initial height of the initial first fill layer to expose the initial sacrificial layer located on the top surfaces of the first pattern mask layer and the second pattern mask layer; and removing the initial sacrificial layer on the top surfaces of the first pattern mask layer and the second pattern mask layer.

[0013] In some embodiments, the pattern transfer layer includes a hard mask layer and a sub-transfer layer, wherein the sub-transfer layer covers the surface of the target layer and the hard mask layer covers the surface of the sub-transfer layer.

[0014] In some embodiments, forming a second filler layer includes: forming an initial second filler layer that fills the first gap and the second gap, and having a top surface higher than the top surface of the sacrificial layer; and removing a portion of the height of the initial second filler layer to expose the top surface of the sacrificial layer.

[0015] In some embodiments, forming the initial second fill layer includes: the height difference between the top surface of the initial second fill layer located above the array region and the top surface of the initial second fill layer located above the peripheral region is less than 5 nm.

[0016] In some embodiments, the process for forming the sacrificial layer includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0017] In some embodiments, the material forming the sacrificial layer includes silicon oxide.

[0018] In some embodiments, the process of forming the first filler layer and the second filler layer both include a spin-coating carbon process.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure also provides a semiconductor structure, including: a substrate, the substrate including an array region and a peripheral region; a target layer, the target layer covering the surface of the substrate; wherein the surface of the target layer has a first pattern located directly above the array region and a second pattern located directly above the peripheral region, the first pattern and the second pattern being formed by the semiconductor structure fabrication method of any one of the above embodiments.

[0020] The technical solution provided by this disclosure has at least the following advantages: By forming a target layer, a pattern transfer layer, a first pattern mask layer, and a second pattern mask layer on the surface of a substrate, wherein the first pattern mask layer is located on the surface of the pattern transfer layer at the top of the array region, and the second pattern mask layer is located on the surface of the pattern transfer layer at the top of the peripheral region, the pattern size in the first pattern mask layer is smaller than the pattern size in the second pattern mask layer, and the pattern density in the first pattern mask layer is greater than the pattern density in the second pattern mask layer, so that a target layer with a first pattern and a second pattern can be formed based on the first pattern mask layer and the second pattern mask layer respectively in subsequent processes; then a sacrificial layer covering the sidewalls of the first pattern mask layer and the second pattern mask layer and a first filling layer filling the first gap are formed, so that the portion of the sacrificial layer located on the sidewalls of the first pattern mask layer and the second pattern mask layer serves as the size basis of the target pattern; then the first filling layer, the first pattern mask layer, and the second pattern mask layer are removed. The process involves retaining the sacrificial layer, the first gap, and the second gap that replaces the first and second patterned mask layers. A second filler layer is then used to fill the first and second gaps. This backfilling process controls the height difference between the peripheral area and the array area within a certain range, preventing pattern defects caused by excessive height differences. Subsequently, the sacrificial layer and the pattern transfer layer are etched based on the second filler layer, and the etched pattern is transferred to the target layer. This forms a first pattern directly above the array area and a second pattern directly above the peripheral area on the target layer surface. The pattern transfer layer facilitates the transition, preventing the target layer in the peripheral area from being directly etched through due to the height difference between the peripheral and array areas during the direct etching process based on the etched pattern. This avoids etching damage to other material layers below the target layer, improving the accuracy of the target layer pattern and mitigating pattern defects in the array and peripheral areas during the ReverseSADP process. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figures 1 to 7 This is a schematic diagram of the various steps corresponding to a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0023] As is known from the background art, since semiconductor structures typically include an array region and a peripheral region, and the array region and the peripheral region have significant differences in pattern density and height, there are pattern defects in the array region and the peripheral region of the semiconductor structure during the Reverse SADP process.

[0024] Analysis revealed that the Reverse Self-Aligned Double Patterning (ReSADP) process involves: fabricating a mandrel structure using a first patterning process; then forming spacers on both sides of the mandrel structure; and finally forming another material layer to fill the remaining gaps between the mandrel structures. The gaps created by removing the spacers then serve as etching channels to etch the underlying material layer exposed by these gaps. However, in existing Reverse SADP processes, the difference in pattern density between the array region and the peripheral region of the semiconductor structure creates a loading effect, resulting in a height difference between the peripheral and array regions. During the etching process to create gaps between the sacrificial layers in the array and peripheral regions, this height difference can easily lead to over-etching of the sacrificial layer in the peripheral region, resulting in pattern defects.

[0025] It should be noted that the "loading effect" mentioned in this article generally refers to the micro-loading effect. When there are regions with different design pattern densities in a semiconductor structure, during processes such as exposure, etching, or polishing, the densely patterned regions and the sparsely patterned regions will react differently to varying degrees, resulting in uneven processing, such as uneven etching depth. Some pattern distortion may also occur at the boundaries between these regions with uneven pattern density.

[0026] One embodiment of this disclosure provides a semiconductor structure to improve the patterning defects in the array region and peripheral region during the Reverse SADP process.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] Figures 1 to 7 The accompanying drawings are schematic diagrams illustrating the various steps of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. The method for fabricating the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0029] refer to Figures 1 to 7 Methods for fabricating semiconductor structures include:

[0030] refer to Figure 1 A substrate 100 is provided, which includes an array region 101 and a peripheral region 102; a target layer 201 covering the top of the substrate 100 and a pattern transfer layer 202 covering the target layer 201 are formed.

[0031] For substrate 100, the material of substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0032] For array region 101, there are arrayed storage cells, which can be used to store data in semiconductor integrated circuits.

[0033] The peripheral area 102 has a circuit structure for controlling the storage array. The circuit structure can transmit data to a specified storage cell for storage to realize the write operation, and can also transmit data in a specified storage cell to the circuit structure to realize the read operation.

[0034] In some embodiments, the target layer can be used to form a capacitive contact window. For example, when there is an array of transistor structures on the substrate of the array region, the target layer covers and fills the gaps between the transistor structures, and the material of the target layer can be tungsten metal. As the integration density of semiconductor structures increases, the size of transistor structures becomes smaller and the arrangement density becomes higher. Photomasks cannot directly form process windows that are too small. Therefore, it is necessary to pattern the target layer through multiple patterning to form a capacitive contact window.

[0035] For pattern transfer layers, the pattern transfer layer can serve as a transition layer to transfer patterns to the target layer. This prevents the target layer from being directly etched through due to the height difference between the outer region and the array region during the etching process based on the etch pattern, thereby avoiding the etching damage to other material layers below the target layer.

[0036] In some embodiments, the material forming the pattern transfer layer includes amorphous carbon.

[0037] In some embodiments, the pattern transfer layer includes a hard mask layer and a sub-transfer layer. The sub-transfer layer covers the surface of the target layer, and the hard mask layer covers the surface of the sub-transfer layer. The hard mask layer above the sub-transfer layer can act as an etching barrier layer. The hard mask layer can have a high etching selectivity. During the etching process of the pattern above the pattern transfer layer, the hard mask layer serves as the etching endpoint, maintaining the same height for the sub-transfer layers below the hard mask layers in the array region and the peripheral region. The pattern is then transferred onto the hard mask layer, and the sub-mask layer is etched based on the hard mask layer. This ensures that the thickness of the sub-mask layers in the peripheral region and the array region is the same, resulting in the same etching depth. This avoids different etching depths caused by different height differences between the peripheral region and the array region, thereby preventing pattern defects in the peripheral region and the array region.

[0038] In some embodiments, the material forming the hard mask layer includes silicon nitride; the material forming the sub-mask layer includes amorphous carbon.

[0039] refer to Figure 2 A first pattern mask layer 213 and a second pattern mask layer 223 are formed. The first pattern mask layer 213 is located on the surface of the pattern transfer layer 202 at the top of the array region 101, and the second pattern mask layer 223 is located on the surface of the pattern transfer layer 202 at the top of the peripheral region 102. The pattern size in the first pattern mask layer 213 is smaller than the pattern size in the second pattern mask layer 223, and the pattern density in the first pattern mask layer 213 is greater than the pattern density in the second pattern mask layer 223.

[0040] For the first pattern mask layer 213 and the second pattern mask layer 223, the materials forming the first pattern mask layer 213 and the second pattern mask layer 223 both include at least one of amorphous carbon, silicon nitride, or silicon carbide.

[0041] In some embodiments, forming a first pattern mask layer and a second pattern mask layer includes: forming a mask layer covering the top surface of a pattern transfer layer; forming a first pattern photoresist on the mask layer; and patterning the mask layer located directly above an array region based on the first pattern photoresist to form the first pattern mask layer; forming a second pattern photoresist on the mask layer; and patterning the mask layer located directly above a peripheral region based on the second pattern photoresist to form the second pattern mask layer. By forming a mask layer covering the surface of the pattern transfer layer and then defining the patterns of the peripheral region and the array region separately using photoresist, mask patterns for both the peripheral region and the array region can be formed simultaneously. This eliminates the need to first form a mask to cover the array region to pattern the peripheral region, and then form a mask layer to cover the peripheral region to pattern the array region, simplifying the semiconductor structure fabrication process and improving the semiconductor structure fabrication efficiency.

[0042] For the mask layer, the material forming the mask layer includes at least one of amorphous carbon, silicon nitride, or silicon carbide.

[0043] In other embodiments, the materials forming the first pattern mask layer and the second pattern mask layer can be photoresist. By directly forming a photoresist layer on the surface of the pattern transfer layer and then defining the photoresist layer by illumination, the remaining photoresist in the array region forms the first pattern mask layer, and the remaining photoresist in the peripheral region forms the second pattern mask layer, thereby reducing the process steps of mask fabrication and improving the fabrication efficiency of semiconductor structures.

[0044] refer to Figure 3 A sacrificial layer 204 and a first filler layer 215 are formed. The sacrificial layer 204 at least covers the sidewalls of the first pattern mask layer 213 and the sidewalls of the second pattern mask layer 223. The first filler layer 215 fills the first gap S1 between the sacrificial layers 204.

[0045] For the sacrificial layer, the material forming the sacrificial layer includes silicon oxide. In the Reserve SADP process, because silicon oxide can achieve a higher etch selectivity compared to the materials of the first filler layer 215, the first pattern mask layer 213, and the second pattern mask layer 223, the sacrificial layer can be removed more easily during the etching process to form gaps without damaging other filler materials. This avoids damage to the etching pattern or deviation from the expected effect, thereby improving the accuracy of the etching pattern in the Reserve SADP process.

[0046] In some embodiments, the process for forming the sacrificial layer includes chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0047] In some embodiments, the ratio of the thickness of the sacrificial layer on the sidewall of the first pattern mask layer to the width of the sidewall of the first pattern mask layer ranges from 1:2 to 1:10. Specifically, the ratio of the thickness of the sidewall of the first pattern mask layer to the width of the sidewall of the first pattern mask layer can be 1:2, 1:4, 1:8, or 1:10. During the Reserve SADP process, the sacrificial layer on the sidewall of the first pattern mask layer is etched to form a gap. This gap can serve as an etching channel for etching the target pattern to etch the material beneath the sacrificial layer. The first pattern mask layer typically has a large sidewall thickness to facilitate the fabrication of windows. The thickness of the sacrificial layer on the sidewall of the first pattern mask and the width of the sidewall of the first pattern mask layer can reflect the relationship between the gap width formed by the sacrificial layer and the size of the target pattern. Therefore, the appropriate sidewall width of the first pattern mask layer and the appropriate sacrificial layer thickness can be selected through calculation. Understandably, the ratio of the thickness of the sacrificial layer on the sidewall of the first pattern mask layer to the width of the sidewall of the first pattern mask layer needs to be selected within a reasonable range to avoid the sacrificial layer being too thick and directly filling the gaps between the first pattern mask layers, or the sacrificial layer being too thin and causing defects in the target pattern.

[0048] For the first filler layer, the material forming the first filler layer includes amorphous carbon; the process for forming the first filler layer includes spin-coating carbon.

[0049] Specifically, in some embodiments, a sacrificial layer 204 and a first filler layer 215 are formed, including: reference Figure 4 An initial sacrificial layer 214 is formed, covering the top surface and sidewalls of the first pattern mask layer 213 and the top surface of the pattern transfer layer 202 exposed by the first pattern mask layer 213, and also covering the top surface and sidewalls of the second pattern mask layer 223 and the top surface of the pattern transfer layer 202 exposed by the second pattern mask layer 223; an initial first fill layer 315 is formed, filling the gaps between the initial sacrificial layers 214 and covering the top surface of the initial sacrificial layers 214; Return to Reference Figure 3 A portion of the initial sacrificial layer 214 and the initial first fill layer 315 are removed to expose the top surfaces of the first pattern mask layer 213 and the second pattern mask layer 223. The remaining initial sacrificial layer 214 serves as the sacrificial layer 204, and the remaining initial first fill layer 315 serves as the first fill layer 215.

[0050] Specifically, removing a portion of the initial sacrificial layer and the initial first fill layer includes: removing a portion of the initial first fill layer to expose the initial sacrificial layer located on the top surfaces of the first pattern mask layer and the second pattern mask layer; and removing the initial sacrificial layer on the top surfaces of the first pattern mask layer and the second pattern mask layer. Since the initial sacrificial layer and the initial first fill layer are made of different materials, their etching selectivity ratios may differ. By first removing a portion of the initial first fill layer to expose the initial sacrificial layer on top of the first pattern mask layer and the second pattern mask layer, and then laterally removing the initial sacrificial layer on top of the first pattern mask layer and the second pattern mask layer, different etching conditions can be selected to target different material layers, thereby increasing the accuracy of the etched pattern and avoiding pattern defects caused by a single etching condition.

[0051] Furthermore, in some embodiments, after forming the initial sacrificial layer and before forming the initial first fill layer, the method further includes: removing the initial sacrificial layer from the top surfaces of the first pattern mask layer and the second pattern mask layer, as well as the initial sacrificial layer located on the surface of the pattern transfer layer; forming the initial first fill layer further includes: the initial first fill layer covering the surface of the pattern transfer layer and the top surfaces of the first pattern mask layer and the second pattern mask layer, thereby forming as shown in the figure. Figure 5 The semiconductor structure shown is as follows. First, the initial sacrificial layer located on the top surfaces of the first and second patterned mask layers is removed, as is the initial sacrificial layer located on the surface of the pattern transfer layer. Only the initial sacrificial layers on the sidewalls of the first and second patterned mask layers are retained. Then, the gaps between the initial sacrificial layers are filled. This prevents the sacrificial layers between the first gaps from being laterally etched during subsequent etching of the etching pattern based on the sacrificial layers, thus avoiding affecting the morphology of the etching pattern and preventing errors in the etching pattern of the pattern transfer layer.

[0052] refer to Figure 6 The first fill layer 215, the first pattern mask layer 213, and the second pattern mask layer 223 are removed, while the sacrificial layer 204, the first gap S1, and the second gap S2 replacing the first pattern mask layer 213 and the second pattern mask layer 223 are retained. A second fill layer 225 is then formed, filling the first gap S1 and the second gap S2, with the top surface of the second fill layer 225 flush with the top surface of the sacrificial layer 204. By removing the first fill layer, the first pattern mask layer, and the second pattern mask layer from both the array region and the peripheral region, the pattern density in the array region can be reduced. During the refilling process of the second fill layer, the load effect in the peripheral region and the array region can be reduced, avoiding an excessive height difference between the peripheral region and the array region.

[0053] In this embodiment, the processes for forming the first filler layer and the second filler layer are both spin-coating carbon processes, that is, the materials of the first filler layer and the second filler layer are the same, both being amorphous carbon materials, and they are represented by the same features in the accompanying drawings provided in this embodiment; in other embodiments, the materials for forming the first filler layer and the processes for forming the second filler layer may be different, and the materials of the first filler layer and the second filler layer may be different.

[0054] Specifically, forming a second filling layer includes: forming an initial second filling layer that fills the first gap and the second gap, with its top surface higher than the top surface of the sacrificial layer. The height difference between the top surface of the initial second filling layer above the array region and the top surface of the initial second filling layer above the peripheral region is less than 5 nm. Specifically, the height difference between the top surface of the initial second filling layer above the array region and the top surface of the initial second filling layer above the peripheral region can be 0 nm, 1 nm, 3 nm, or 5 nm. A portion of the initial second filling layer is removed to expose the top surface of the sacrificial layer. First, the initial second filling layer fills the first gap and the second gap, filling the gaps between the sacrificial layers, and its top surface is higher than the top surface of the sacrificial layer. The height difference between the top surface of the initial second filling layer above the array region and the top surface of the initial second filling layer above the peripheral region is less than 5 nm. This reduces the height difference between the array region and the peripheral region after filling with the initial second filling layer, preventing excessive height differences between the array region and the peripheral region from causing different etching depths in subsequent etching, thereby avoiding pattern defects in the array region and the peripheral region. It is understandable that the smaller the height difference between the initial second fill layer above the array area and the initial second fill layer above the array area, the higher the requirements for process conditions; if the height difference between the initial second fill layer above the array area and the initial second fill layer above the array area is too large, it will not be able to achieve the effect of reducing the height difference between the array area and the peripheral area. Therefore, the filling of the initial second fill layer needs to be within a certain range to meet the requirement of reducing the height difference between the array area and the peripheral area without placing too much burden on the process.

[0055] In some embodiments, the width of the first gap S1 located directly above the array region is equal to the width of the second gap S2. When the widths of the first gap S1 and the second gap S2 are equal, after etching the sacrificial layer based on the second fill layer, the remaining second fill layer has equal width and equal gaps, thereby forming a regular target pattern to meet the fabrication requirements of the corresponding structure.

[0056] refer to Figure 7An etching pattern is formed by etching the sacrificial layer based on the second fill layer, and then an etching transfer layer is etched based on the etched pattern. The etched pattern is transferred to the target layer along the etched pattern transfer layer to form a first pattern directly above the array region and a second pattern directly above the peripheral region on the surface of the target layer. The pattern transfer layer can serve as a transition layer for transferring the etched pattern to the target layer, preventing the target layer from being directly etched through due to the height difference between the peripheral region and the array region during the direct etching process based on the etched pattern, thereby avoiding etching damage to other material layers below the target layer.

[0057] The semiconductor structure fabrication method provided in this disclosure involves forming a target layer, a pattern transfer layer, a first pattern mask layer, and a second pattern mask layer on the surface of a substrate. The first pattern mask layer is located on the surface of the pattern transfer layer at the top of the array region, and the second pattern mask layer is located on the surface of the pattern transfer layer at the top of the peripheral region. The pattern size in the first pattern mask layer is smaller than the pattern size in the second pattern mask layer, and the pattern density in the first pattern mask layer is greater than the pattern density in the second pattern mask layer. This facilitates the formation of a target layer with a first pattern and a second pattern based on the first and second pattern masks in subsequent processes. A sacrificial layer covering the sidewalls of the first and second pattern masks, and a first fill layer filling the first gap, are then formed, with the portion of the sacrificial layer located on the sidewalls of the first and second pattern masks serving as the size basis for the target pattern. Finally, the first fill layer, the first pattern mask layer, and the second pattern mask layer are removed. The process involves two pattern mask layers: a sacrificial layer, a first gap, and a second gap replacing the first and second pattern mask layers. A second filler layer is then used to fill the first and second gaps. This backfilling process controls the height difference between the peripheral area and the array area within a certain range, preventing pattern defects caused by excessive height differences between the peripheral and array areas. Subsequently, the sacrificial layer and pattern transfer layer are etched based on the second filler layer, and the etched pattern is transferred to the target layer to form a first pattern directly above the array area and a second pattern directly above the peripheral area on the surface of the target layer. The pattern transfer layer facilitates the transition, preventing the target layer in the peripheral area from being directly etched through due to the height difference between the peripheral and array areas during the direct etching process based on the etched pattern. This avoids etching damage to other material layers below the target layer, improves the accuracy of the target layer pattern, and mitigates pattern defects in the array and peripheral areas during the Reverse SADP process.

[0058] Another embodiment of this disclosure provides a semiconductor structure that can be formed based on the above-described semiconductor structure fabrication method to improve the patterning defects in the array region and peripheral region during the Reverse SADP process. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be described in detail below.

[0059] The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0060] Continue to refer to Figure 7 A semiconductor structure includes: a substrate 100, the substrate including an array region 101 and a peripheral region 102; a target layer 201, the target layer 201 covering the surface of the substrate 100; wherein the surface of the target layer 201 has a first pattern located directly above the array region 101 and a second pattern located directly above the peripheral region 102, the first pattern and the second pattern being formed by the semiconductor structure fabrication method provided in any of the above embodiments.

[0061] For substrate 100, the material of substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0062] For array region 101, there are arrayed storage cells, which can be used to store data in semiconductor integrated circuits.

[0063] The peripheral area 102 has a circuit structure for controlling the storage array. The circuit structure can transmit data to a specified storage cell for storage to realize the write operation, and can also transmit data in a specified storage cell to the circuit structure to realize the read operation.

[0064] In some embodiments, the target layer can be used to form a capacitive contact window. For example, when there is an array of transistor structures on the substrate of the array region, the target layer covers and fills the gaps between the transistor structures, and the material of the target layer can be tungsten metal. As the integration density of semiconductor structures increases, the size of transistor structures becomes smaller and the arrangement density becomes higher. Photomasks cannot directly form process windows that are too small. Therefore, it is necessary to pattern the target layer through multiple patterning to form a capacitive contact window.

[0065] The semiconductor structure provided in this disclosure is based on the semiconductor structure fabrication method provided in the above embodiments, in order to improve the pattern defect problem of the array region and the peripheral region in the Reverse SADP process.

[0066] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an array region and a peripheral region; Form a target layer covering the top of the substrate and a graphics transfer layer covering the target layer; A first pattern mask layer and a second pattern mask layer are formed. The first pattern mask layer is located on the surface of the pattern transfer layer at the top of the array region, and the second pattern mask layer is located on the surface of the pattern transfer layer at the top of the peripheral region. The pattern size in the first pattern mask layer is smaller than the pattern size in the second pattern mask layer, and the pattern density in the first pattern mask layer is greater than the pattern density in the second pattern mask layer. A sacrificial layer and a first fill layer are formed, wherein the sacrificial layer at least covers the sidewalls of the first pattern mask layer and the sidewalls of the second pattern mask layer, and the first fill layer fills the first gap between the sacrificial layers; Remove the first fill layer, the first pattern mask layer, and the second pattern mask layer, while retaining the sacrificial layer, the first gap, and the second gap that replaces the first pattern mask layer and the second pattern mask layer; A second filler layer is formed, which fills the first gap and the second gap, and the top surface of the second filler layer is flush with the top surface of the sacrificial layer; The sacrificial layer is etched based on the second fill layer to form an etching pattern, and the pattern transfer layer is etched based on the etching pattern; The etched pattern is transferred to the target layer along the etched pattern transfer layer to form a first pattern directly above the array region and a second pattern directly above the peripheral region on the surface of the target layer.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The ratio of the thickness of the sacrificial layer on the sidewall of the first pattern mask layer to the width of the sidewall of the first pattern mask layer is in the range of 1:2 to 1:

10.

3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The width of the first gap located directly above the array area is equal to the width of the second gap.

4. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The formation of the first pattern mask layer and the second pattern mask layer includes: A mask layer is formed, which covers the top surface of the pattern transfer layer; A first patterned photoresist is formed on the mask layer, and based on the first patterned photoresist, the mask layer located directly above the array region is patterned to form the first patterned mask layer; A second patterned photoresist is formed on the mask layer. Based on the second patterned photoresist, the mask layer located directly above the peripheral region is patterned to form the second patterned mask layer.

5. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The formation of the sacrificial layer and the first filler layer includes: An initial sacrificial layer is formed, which covers the top surface and sidewalls of the first pattern mask layer and the top surface of the pattern transfer layer exposed by the first pattern mask layer, and also covers the top surface and sidewalls of the second pattern mask layer and the top surface of the pattern transfer layer exposed by the second pattern mask layer; An initial first fill layer is formed, which fills the gaps between the initial sacrificial layers and covers the top surface of the initial sacrificial layers; A portion of the initial sacrificial layer and the initial first fill layer are removed to expose the top surfaces of the first pattern mask layer and the second pattern mask layer, leaving the remaining initial sacrificial layer as the sacrificial layer and the remaining initial first fill layer as the first fill layer.

6. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, include: After the initial sacrificial layer is formed and before the initial first fill layer is formed, the method further includes: removing the initial sacrificial layer from the top surfaces of the first pattern mask layer and the second pattern mask layer, and the initial sacrificial layer located on the surface of the pattern transfer layer; The formation of the initial first fill layer further includes: the initial first fill layer covering the surface of the pattern transfer layer and the top surfaces of the first pattern mask layer and the second pattern mask layer.

7. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The removal of a portion of the height of the initial sacrificial layer and the initial first fill layer includes: Remove a portion of the initial first fill layer to expose the initial sacrificial layer located on the top surfaces of the first pattern mask layer and the second pattern mask layer; Remove the initial sacrificial layer from the top surfaces of the first pattern mask layer and the second pattern mask layer.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The pattern transfer layer includes a hard mask layer and a sub-transfer layer, wherein the sub-transfer layer covers the surface of the target layer and the hard mask layer covers the surface of the sub-transfer layer.

9. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The formation of the second filling layer includes: An initial second filler layer is formed, which fills the first gap and the second gap, and the top surface of the initial second filler layer is higher than the top surface of the sacrificial layer; Remove a portion of the initial second filler layer to expose the top surface of the sacrificial layer.

10. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, The formation of the initial second fill layer includes: the height difference between the top surface of the initial second fill layer located above the array region and the top surface of the initial second fill layer located above the peripheral region is less than 5 nm.

11. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The process for forming the sacrificial layer includes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

12. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The material forming the sacrificial layer includes silicon oxide.

13. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The processes for forming the first filler layer and the second filler layer both include a spin-coating carbon process.

14. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising an array region and a peripheral region; Target layer, the target layer covering the surface of the substrate; The target layer surface has a first pattern located directly above the array region and a second pattern located directly above the peripheral region, the first pattern and the second pattern being formed by a semiconductor structure fabrication method as described in any one of claims 1 to 13.

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