A variable rate communication system and communication method based on FPGA

Abstract

The present invention discloses a variable rate communication system and communication method based on FPGA, which relates to the field of communication data transmission. The key points of the technical solution are: a variable rate communication system based on FPGA, including a transceiver system that can be respectively set in two devices and used between the two devices, each of which includes a serial data sending unit, a serial data receiving unit and an error processing unit implemented based on FPGA; a communication method of a variable rate communication system based on FPGA, including the following steps: S1, system initialization; S2, calculation of CRC check code of sent data; S3, 4B / 5B encoding; S4, sending data to the opposite end device; S5, receiving data; S6, 4B / 5B decoding; S7, receiving data check. The present invention realizes end-to-end efficient communication between two devices, and can better control and monitor the complex situation of equipment field operation.

Description

Technical Field

[0001] The present invention relates to the field of communication data transmission, and more specifically, to a variable rate communication system and a communication method based on FPGA. Background Art

[0002] In the use of many industrial products, in addition to the common industrial bus for complex multi-device communication, there are also a large number of end-to-end devices with variable speeds. For example, the communication between the servo drive and the encoder usually requires the use of an internal custom protocol, such as SSI communication or BISS communication protocol, and the interface form is the direct connection between the devices through the chip port.

[0003] like Figure 4 The figure shows a schematic diagram of the currently commonly used serial communication. In this scheme, the external device is input to the serial shift register of the receiver through the line, and is received after data buffering; when sending, the sending data is first stored in the buffer and then sent to the external device by the serial shift register.

[0004] In the above system, the MCU core directly shifts the data during the data reception process, which makes it easy to receive bits caused by jump errors in the line, thereby causing hidden dangers to upstream equipment; and no data balancing is performed when sending data, so the data sent is also easily affected by line interference, which ultimately affects the normal operation of external devices.

[0005] Therefore, a new solution needs to be proposed to solve this problem. Summary of the invention

[0006] In view of the deficiencies in the prior art, the purpose of the present invention is to provide a variable-rate communication system and communication method based on FPGA, which realizes efficient end-to-end communication between two devices and can better control and monitor the complex situations of on-site operation of the equipment.

[0007] The above technical purpose of the present invention is achieved through the following technical solutions: a variable rate communication system based on FPGA, comprising two transceiver systems that can be respectively arranged in two devices and used for end-to-end communication between the two devices, each of the transceiver systems comprising a serial data sending unit, a serial data receiving unit and an error processing unit implemented based on FPGA, the serial data sending unit comprising a sending data CRC check module, a sending data encoding module and a serial variable rate data sending module electrically connected in sequence, the serial data receiving unit comprising a serial variable rate data receiving module, a receiving data decoding module and a receiving data CRC check module electrically connected in sequence, the error processing unit is electrically connected to the receiving data CRC check module, the serial variable rate data sending module in one of the transceiver systems is communicatively connected to the serial variable rate data receiving module in the other transceiver system through a serial line, and the serial variable rate data sending module in the other transceiver system is communicatively connected to the serial variable rate data receiving module in the one of the transceiver systems through a serial line.

[0008] In one embodiment, the serial variable rate data transmission module includes a clock frequency division transmission component and a frame transmission component electrically connected to the clock frequency division transmission component.

[0009] In one embodiment, the serial variable rate data receiving module includes a frame sampling component and an entropy increase energy filtering component and a clock frequency division receiving component electrically connected to the frame sampling component respectively.

[0010] In one of the embodiments, the sending data encoding module is a 4B / 5B encoding module, and the receiving data decoding module is a 4B / 5B decoding module.

[0011] In one embodiment, a communication method using a variable rate communication system based on an FPGA comprises the following steps:

[0012] S1, system initialization: At the beginning, the system is powered on, and the FPGA and the serial data sending unit, serial data receiving unit and error processing unit connected to the FPGA are initialized;

[0013] S2. Calculate the CRC check code of the transmitted data: after receiving the byte data of one of the devices, the CRC check code module of the transmitted data in one of the transceiver systems starts to calculate the CRC-16 of the received byte data to form the transmitted data check code, and sends it toward the transmitted data encoding module according to the data width required by the encoding of the transmitted data encoding module;

[0014] S3, 4B / 5B encoding: The transmission data encoding module encodes the transmission data check code in S2 and sends the encoded data to the serial variable rate data transmission module;

[0015] S4, sending data to the peer device: the variable rate data sending module sets the corresponding communication rate according to the requirements of the peer device, and then processes the encoded data into a frame structure, and then converts the frame structure into a serial variable rate data receiving module in another transceiver system;

[0016] S5, receiving data: the serial variable rate data receiving module sets the corresponding communication rate according to the requirements of the upstream device, and sends the received upstream data to the receiving data decoding module;

[0017] S6, 4B / 5B decoding: The receiving data decoding module performs 4B / 5B decoding on the data received in S5 and sends it to the receiving data CRC check module;

[0018] S7, received data check: The received data CRC check module performs received data CRC check on the data in S6 to determine whether the received data has errors. If there are no errors in the data, it is sent to the upstream device normally. If there are errors in the data, it is sent to the error processing unit. The error processing unit reports the error statistics of the error data to quickly reflect the communication abnormality of the device.

[0019] In one embodiment, the frame structure processing in S4 comprises the following steps:

[0020] S41, parameter configuration: The encoded data enters the clock frequency division transmission component, and the global clock frequency division integrated in the FPGA generates a transmission clock corresponding to the rate;

[0021] S42, sending a single-bit data stream: the sending clock in S41 enters the frame sending component, and the frame sending component sends a single-bit data stream with a variable rate according to the sending clock, and finally sends it to the serial variable rate data receiving module of the opposite end transceiver system through the serial line.

[0022] In one of the embodiments, when the bit data stream in S42 enters the entropy increase energy filtering component in the serial variable rate data receiving module, the entropy increase energy filtering component first performs entropy increase energy filtering on it, and then in the clock division receiving component, a sampling clock corresponding to the rate is generated through the global clock division integrated inside the FPGA, and then the stable single-bit data stream obtained after filtering is sampled at a variable rate in the frame sampling component.

[0023] In summary, the present invention has the following beneficial effects:

[0024] 1. The present invention realizes end-to-end communication between two devices, and the present invention is based on FPGA design. FPGA has good programmability, and the modification of communication protocol and the addition of functions will not lead to the extension of design cycle and the increase of cost;

[0025] 2. The present invention uses the CRC check module and the error processing unit to quickly report the error data when a data error occurs in the upstream device, and will not directly send it to the downstream device to cause hidden dangers. In this way, when the device receives data for a long time without flipping, it is considered that the line is faulty and a corresponding error count is generated, which can facilitate people to quickly identify the fault point of the device;

[0026] 3. In the present invention, by setting up a serial variable rate data sending module and a serial variable rate data receiving module, the two can respectively adapt to the complex and changeable industrial field communication environment through the setting of corresponding clock frequency division parameters. When the field communication environment is poor, the communication bit error rate can be reduced by lowering the setting of the frequency division parameters, thereby reducing the complex problems caused by communication problems; when the quality of the field communication signal is good, the field industrial communication bandwidth can be improved by increasing the frequency division parameters, so that the equipment can process more data in a limited time and better control and monitor the complex situation of field operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A structural block diagram of a variable rate communication system based on FPGA according to an embodiment of the present application;

[0028] Figure 2 A structural block diagram of a serial variable rate data transmission module in a variable rate communication system based on FPGA according to an embodiment of the present application;

[0029] Figure 3 A structural block diagram of a serial variable rate data receiving module in a variable rate communication system based on FPGA according to an embodiment of the present application;

[0030] Figure 4 It is a schematic diagram of serial communication in the prior art.

[0031] In the figure: 1. CRC check module for sending data; 2. CRC check module for sending data; 3. Serial variable rate data sending module; 31. Clock frequency division sending component; 32. Frame sending component; 4. Serial variable rate data receiving module; 41. Clock frequency division receiving component; 42. Frame sampling component; 43. Entropy increase energy filtering component; 5. Received data decoding module; 6. CRC check module for receiving data; 7. Error handling unit. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention; the terms "first", "second", and "third" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance. In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0034] like Figures 1 to 3 As shown, the embodiment of the present application provides a variable rate communication system based on FPGA, including two transceiver systems that can be respectively set in two devices for end-to-end communication between the two devices. Each of the transceiver systems includes a serial data sending unit, a serial data receiving unit and an error processing unit 7 implemented based on FPGA, and the serial data sending unit, the serial data receiving unit and the error processing unit 7 are electrically connected to the FPGA respectively. The serial data sending unit includes a sending data CRC check module 1, a sending data encoding module 2 and a serial variable rate data sending module 3 that are electrically connected in sequence. The serial data receiving unit includes a serial variable rate data receiving module 4, a receiving data decoding module 5 and a receiving data CRC check module 6 that are electrically connected in sequence, and the error processing unit 7 is electrically connected to the receiving data CRC check module 6. The serial variable rate data sending module 3 in one of the transceiver systems is connected to the serial variable rate data receiving module 4 in the other transceiver system through a serial line, and the serial variable rate data sending module 3 in the other transceiver system is connected to the serial variable rate data receiving module 4 in the one of the transceiver systems through a serial line.

[0035] It should be noted that the FPGA in this embodiment adopts the existing technology. FPGA is a semi-custom circuit in the application-specific integrated circuit. It is a programmable logic array that can effectively solve the problem of the small number of gate circuits of the original device. The basic structure of FPGA includes programmable input and output units, configurable logic blocks, global digital clock modules, embedded block RAM, wiring resources, embedded dedicated hard cores and bottom embedded functional units.

[0036] The above method realizes end-to-end communication between two devices, and the present invention is based on FPGA design. FPGA has good programmability, and the modification of communication protocol and the addition of functions will not lead to the extension of design cycle and the increase of cost;

[0037] Through the setting of the CRC check module and the error processing unit 7, when a data error occurs in the upstream device, the error processing unit 7 can quickly report the error data, and will not directly send it to the downstream device to cause equipment hidden dangers. In this way, when the device receives data for a long time without flipping, it is considered that the line is faulty and a corresponding error count is generated, which can facilitate people to quickly identify the fault point of the device;

[0038] Through the settings of the serial variable rate data sending module 3 and the serial variable rate data receiving module 4, the two can respectively adapt to the complex and changeable industrial field communication environment through the setting of corresponding clock division parameters. When the field communication environment is poor, the communication bit error rate can be reduced by lowering the setting of the division parameter, thereby reducing the complex problems caused by communication problems; when the field communication signal quality is good, the field industrial communication bandwidth can be improved by increasing the division parameter, so that the equipment can process more data in a limited time and better control and monitor the complex situation of field operation.

[0039] On the basis of the above, the serial variable rate data sending module 3 includes a clock frequency division sending component 31 and a frame sending component 32 electrically connected to the clock frequency division sending component 31 .

[0040] During operation, the encoded data enters the clock division sending component 31, and the global clock division integrated inside the FPGA generates a sending clock corresponding to its rate. The sending clock enters the frame sending component 32, and the frame sending component 32 sends a single-bit data stream with a variable rate according to the sending clock, and finally sends it to the serial variable rate data receiving module 4 of the opposite end transceiver system through the serial line.

[0041] The above method makes data transmission more stable and less susceptible to interference from the external environment.

[0042] On the basis of the above, the serial variable rate data receiving module 4 includes a frame sampling component 42 and an entropy increase energy filtering component 43 and a clock frequency division receiving component 41 which are electrically connected to the frame sampling component 42 respectively.

[0043] During operation, the entropy increase energy filtering component 43 first performs entropy increase energy filtering, and then in the clock division receiving component 41, a sampling clock corresponding to its rate is generated through the global clock division integrated inside the FPGA, and then the stable data obtained after filtering is sampled at a variable rate in the frame sampling component 42.

[0044] The above method can change the sampling rate of data and improve the stability of data.

[0045] On the basis of the above, the sending data encoding module 2 is a 4B / 5B encoding module, and the receiving data decoding module 5 is a 4B / 5B decoding module.

[0046] It should be noted that the 4B / 5B encoding module and the 4B / 5B decoding module both adopt existing technologies, and their specific implementation methods are not described in detail in this embodiment.

[0047] A communication method using a variable rate communication system based on FPGA, comprising the following steps:

[0048] S1, system initialization: At the beginning, the system is powered on, and the FPGA and the serial data sending unit, serial data receiving unit and error processing unit 7 connected to the FPGA are initialized;

[0049] S2, calculating the CRC check code of the transmitted data: after receiving the byte data from one of the devices, the CRC check module 1 in one of the transceiver systems starts to calculate the CRC-16 of the received byte data to form the transmitted data check code, and sends it toward the transmitted data encoding module 2 according to the data width required by the encoding of the transmitted data encoding module 2;

[0050] S3, 4B / 5B encoding: the sending data encoding module 2 encodes the sending data check code in S2, and sends the encoded data to the serial variable rate data sending module 3;

[0051] S4, sending data to the peer device: the variable rate data sending module sets the corresponding communication rate according to the requirements of the peer device, and then processes the encoded data into a frame structure, and then converts the frame structure into a serial variable rate data receiving module 4 in another transceiver system;

[0052] S5, receiving data: the serial variable rate data receiving module 4 sets the corresponding communication rate according to the requirements of the upstream device, and sends the received upstream data to the receiving data decoding module 5;

[0053] S6, 4B / 5B decoding: the received data decoding module 5 performs 4B / 5B decoding on the data received in S5 and sends the decoded data to the received data CRC check module 6;

[0054] S7, received data check: The received data CRC check module 6 performs a received data CRC check on the data in S6 to determine whether the received data has an error. If the data has no error, it is sent to the upstream device normally. If the data has an error, it is sent to the error processing unit. The error processing unit 7 reports the error statistics on the error data to quickly reflect the communication abnormality of the device.

[0055] Based on the above, the frame structure processing described in S4 includes the following steps:

[0056] S41, parameter configuration: the encoded data enters the clock frequency division transmission component 31, and generates a transmission clock corresponding to the rate through the global clock frequency division integrated in the FPGA;

[0057] S42, sending a single-bit data stream: the sending clock in S41 enters the frame sending component 32, and the frame sending component 32 sends a variable-rate single-bit data stream according to the sending clock, and finally sends it to the serial variable-rate data receiving module 4 of the opposite end transceiver system through the serial line.

[0058] On the basis of the above, when the bit data stream in S42 enters the entropy increase energy filtering component 43 in the serial variable rate data receiving module 4, the entropy increase energy filtering component 43 first performs entropy increase energy filtering on it, and then in the clock division receiving component 41, the global clock division integrated inside the FPGA generates a sampling clock corresponding to its rate, and then the stable single-bit data stream obtained after filtering is sampled at a variable rate in the frame sampling component 42.

[0059] It is worth noting that in this embodiment, the frame sampling component 42 in the serial variable rate data receiving module 4 and the frame sending component 32 in the serial variable rate sending module can both change the settings of the internal frame structure (such as the frame header frame length, etc.) and then directly connect and communicate with the common industrial communication protocols currently on the market, such as BISS communication, SSI communication, Tamagawa communication, etc.

[0060] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A variable rate communication system based on FPGA, comprising two transceiver systems which can be respectively arranged in two devices for end-to-end communication between the two devices, characterized in that: Each of the transceiver systems comprises a serial data transmission unit, a serial data receiving unit and an error processing unit (7) implemented based on FPGA, the serial data transmission unit comprises a transmission data CRC check module (1), a transmission data encoding module (2) and a serial variable rate data transmission module (3) which are electrically connected in sequence, the serial data receiving unit comprises a serial variable rate data receiving module (4), a reception data decoding module (5) and a reception data CRC check module (6) which are electrically connected in sequence, the error processing unit (7) is electrically connected to the reception data CRC check module (6), the serial variable rate data transmission module (3) in one of the transceiver systems is communicatively connected to the serial variable rate data receiving module (4) in another transceiver system via a serial line, and the serial variable rate data transmission module (3) in the other transceiver system is communicatively connected to the serial variable rate data receiving module (4) in one of the transceiver systems via a serial line; The serial variable rate data transmission module (3) comprises a clock frequency division transmission component (31) and a frame transmission component (32) electrically connected to the clock frequency division transmission component (31).

2. The FPGA-based variable rate communication system according to claim 1, characterized in that: The serial variable rate data receiving module (4) comprises a frame sampling component (42), and an entropy increase energy filtering component (43) and a clock frequency division receiving component (41) which are electrically connected to the frame sampling component (42), respectively.

3. The FPGA-based variable rate communication system according to claim 1, characterized in that: The sending data encoding module (2) is a 4B / 5B encoding module, and the receiving data decoding module (5) is a 4B / 5B decoding module.

4. A communication method for the FPGA-based variable rate communication system according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1, system initialization: at the beginning, the system is powered on, and the FPGA and the serial data sending unit, serial data receiving unit and error processing unit (7) connected to the FPGA are initialized; S2, calculating the CRC check code of the transmitted data: after receiving the byte data from one of the devices, the transmitted data CRC check module (1) in one of the transceiver systems starts to calculate the CRC-16 of the received byte data to form the transmitted data check code, and sends it toward the transmitted data encoding module (2) according to the data width required by the encoding of the transmitted data encoding module (2); S3, 4B / 5B encoding: the transmission data encoding module (2) encodes the transmission data check code in S2, and sends the encoded data to the serial variable rate data transmission module (3); S4, sending data to the peer device: the variable rate data sending module sets the corresponding communication rate according to the requirements of the peer device, and then processes the encoded data into a frame structure, and then converts the frame structure into a serial variable rate data receiving module (4) in another transceiver system; S5, receiving data: the serial variable rate data receiving module (4) sets the corresponding communication rate according to the requirements of the upstream device, and sends the received upstream data to the receiving data decoding module (5); S6, 4B / 5B decoding: the received data decoding module (5) performs 4B / 5B decoding on the data received in S5 and sends the result to the received data CRC check module (6); S7, received data check: The received data CRC check module (6) performs received data CRC check on the data in S6 to determine whether the received data has errors. If the data has no errors, it is sent to the upstream device normally. If the data has errors, it is sent to the error processing unit. The error processing unit (7) reports error statistics on the error data to quickly reflect the communication abnormality of the device.

5. The communication method of the variable rate communication system based on FPGA according to claim 4, characterized in that: The frame structure processing described in S4 includes the following steps: S41, parameter configuration: the encoded data enters the clock frequency division transmission component (31), and the global clock frequency division integrated in the FPGA generates a transmission clock corresponding to the rate; S42, sending a single-bit data stream: the sending clock in S41 enters the frame sending component (32), and the frame sending component (32) sends a variable-rate single-bit data stream according to the sending clock, and finally sends it to the serial variable-rate data receiving module (4) of the opposite end transceiver system through the serial line.

6. The communication method of the variable rate communication system based on FPGA according to claim 5, characterized in that: When the bit data stream in S42 enters the entropy increase energy filtering component (43) in the serial variable rate data receiving module (4), the entropy increase energy filtering component (43) first performs entropy increase energy filtering on it, and then generates a sampling clock corresponding to the rate through the global clock division integrated in the FPGA in the clock division receiving component (41), and then performs variable rate sampling on the stable single-bit data stream obtained after filtering in the frame sampling component (42).

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