Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the semiconductor field, and provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: an active pillar, the active pillar comprising a channel region, a first doped region and a second doped region located on both sides of the channel region respectively, the channel region comprising a first channel region and a second channel region, the first channel region being adjacent to the first doped region, the second channel region being adjacent to the second doped region and located between the first channel region and the second doped region, the first doped region, the second channel region and the second doped region all having a first doping type, the first channel region having a second doping type, the first doping type being one of N type or P type, and the second doping type being the other one of N type or P type; and a gate electrode, the gate electrode being located on the surface of the channel region. The leakage current of the semiconductor structure can be reduced.

Description

1.1.1 Technical Field This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for fabricating the same. 1.1.2 Background Technology Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a transistor, which includes a source, a gate, and a drain. However, as semiconductor structures continue to shrink, the corresponding transistor structures also shrink, which leads to a reduction in the length of the channel region. This causes band-to-band tunneling (BTBT) between conduction band electrons and valence band holes, resulting in drain leakage current. 1.1.3 Summary of the Invention This disclosure provides a semiconductor structure and a method for fabricating the same, which can at least reduce the leakage current of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: an active pillar, the active pillar including a channel region and a first doped region and a second doped region respectively located on both sides of the channel region, the channel region including a first channel region and a second channel region, the first channel region being adjacent to the first doped region, the second channel region being adjacent to the second doped region and located between the first channel region and the second doped region, the first doped region, the second channel region and the second doped region all having a first doping type, the first channel region having a second doping type, the first doping type being one of N-type or P-type, and the second doping type being the other of N-type or P-type; and a gate, the gate being located on the surface of the channel region.

[0006] In some embodiments, in the direction from the first doped region to the second doped region, the length of the first channel region is 1 / 5 to 3 / 5 of the total channel region length. In some embodiments, the doping concentration of the first channel region is 1E16 to 1E18 cm⁻¹. -3 .

[0007] In some embodiments, the second doped region includes a first sub-doped region and a second sub-doped region, wherein the first sub-doped region is located between the second channel region and the second sub-doped region, and the doping concentration of the first sub-doped region is lower than the doping concentration of the second sub-doped region.

[0008] In some embodiments, the doping concentration of the second channel region is equal to the doping concentration of the first sub-doped region.

[0009] In some embodiments, the doping concentration of the first sub-doped region is 1E16~1E19 cm⁻¹ -3 The doping concentration of the second sub-doped region is 1E19~1E22 cm⁻¹ -3 .

[0010] In some embodiments, in the direction from the first doped region to the second doped region, the lengths of the first sub-doped region and the second sub-doped region are equal.

[0011] In some embodiments, the system further includes a capacitor that is in contact with the surface of the second sub-doped region.

[0012] In some embodiments, the gate surrounds the entire surface of the channel region.

[0013] In some embodiments, in a direction perpendicular to the first doped region toward the second doped region, the thickness of the first channel region is equal to the thickness of the second channel region.

[0014] In some embodiments, the system further includes a third channel region adjacent to the first doped region, the first channel region being located between the third channel region and the gate, and the third channel region having a first doping type.

[0015] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing an initial active pillar; performing ion doping on the initial active pillar to form an active pillar, the active pillar including a channel region and a first doped region and a second doped region respectively located on both sides of the channel region; the channel region including a first channel region and a second channel region; the first channel region being adjacent to the first doped region; the second channel region being adjacent to the second doped region and located between the first channel region and the second doped region; the first doped region, the second channel region, and the second doped region all having a first doping type; the first channel region having a second doping type; the first doping type being either N-type or P-type; and the second doping type being either N-type or P-type; forming a gate located on the surface of the channel region.

[0016] In some embodiments, the ion doping includes: a first ion doping, which forms a first doped region and a second sub-doped region; a second ion doping, which forms a first channel region; and a third ion doping, which forms a second channel region and a first sub-doped region, wherein the doping concentration of the first sub-doped region is less than the concentration of the second sub-doped region, and the first sub-doped region and the second sub-doped region constitute the second doped region.

[0017] In some embodiments, the first ion doping includes: forming a first mask layer covering the surface of the channel region and the first sub-doped region; and performing the first ion doping to ion dope the second sub-doped region and the first doped region.

[0018] In some embodiments, the second ion doping includes: forming a second mask layer covering the surfaces of the first doped region and the second sub-doped region; and performing the second ion doping to ion dope the first channel region.

[0019] In some embodiments, the third ion doping includes: forming a third mask layer covering the first channel region; and performing the third ion doping to ion dope the second channel region and the first sub-doped region.

[0020] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by setting a first channel region and a second channel region between the first doped region and the second doped region, and setting the doping type of the first channel region to the second doping type, and setting the doping type of the first doped region and the second doped region to the first doping type, when the carriers of the first doped region flow to the second doped region, some of the carriers are neutralized by the carriers of the first channel region, thereby increasing the barrier height between the first doped region and the second doped region. 1.1.4 Attached Figure Description One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a cross-sectional view of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 4 This is a three-dimensional structural diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figures 5 to 9 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figures 10 to 13 This is a schematic diagram of the steps in a method for fabricating another semiconductor structure according to an embodiment of the present disclosure. 1.1.5 Detailed Implementation As the background technology shows, with the continuous miniaturization of integration, the channel length also decreases. When the channel length decreases to a certain extent, the proportion of the depletion regions of the source and drain in the entire channel region increases, reducing the amount of charge required to form an inversion layer on the substrate surface under the gate, thus decreasing the threshold voltage. Simultaneously, the charge on the lateral widening portion of the depletion region along the channel length within the substrate increases the threshold voltage. When the channel length decreases to the same order of magnitude as the depletion layer length, the reduction in threshold voltage becomes very significant, meaning the reduction in barrier height becomes very significant.

[0024] This disclosure provides a semiconductor structure in which a first channel region and a second channel region are disposed between a first doped region and a second doped region. The first channel region is doped with a second doping type, and the first doped region, the second doped region, and the second channel region are all doped with a first doping type. This allows some carriers to be neutralized by the first channel region during the flow of carriers from the first doped region to the second doped region, thereby increasing the barrier height between the first doped region and the second doped region and increasing the threshold voltage of the semiconductor structure.

[0025] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0026] refer to Figure 1 , Figure 1 A semiconductor structure is provided as an embodiment of this disclosure.

[0027] The semiconductor structure includes: an active pillar 100, which includes a channel region 110 and a first doped region 120 and a second doped region 130 located on both sides of the channel region 110. The channel region 110 includes a first channel region 111 and a second channel region 112. The first channel region 111 is adjacent to the first doped region 120, and the second channel region 112 is adjacent to the second doped region 130 and located between the first channel region 111 and the second doped region 130. The first doped region 120, the second channel region 112, and the second doped region 130 all have a first doping type, and the first channel region 111 has a second doping type. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. A gate 140 is located on the surface of the channel region 110.

[0028] In some embodiments, the gate 140 is used to control whether the first doped region 120 and the second doped region 130 are turned on. When there is no voltage on the gate 140, no current flows between the first doped region 120 and the second doped region 130, that is, the semiconductor structure is in a cut-off state. When a positive voltage is provided to the gate 140, taking the first doping type as an example and the second doping type as an example, the negative electrons in the first doped region 120 and the second doped region 130 are attracted and flow to the gate 140. However, since the gate 140 is not in direct contact with the active pillar 100, the electrons accumulate between the first doped region 120 and the second doped region 130, thereby forming a current, making the first doped region 120 and the second doped region 130 conduct. It can be understood that as the integration density continues to shrink, the first As the spacing between the first doped region 120 and the second doped region 130 becomes closer, the voltage required for the gate 140 to control the conduction between the first doped region 120 and the second doped region 130 decreases, meaning the barrier height between the first doped region 120 and the second doped region 130 decreases. In this embodiment, a first channel region 111 is provided between the first doped region 120 and the second doped region 130, which allows some of the gathered electrons to neutralize the holes in the first channel region 111. In other words, the barrier height between the first doped region 120 and the second doped region 130 increases, thereby increasing the threshold voltage of the semiconductor structure and creating a band change between the channel regions 110. This also helps to suppress the decrease in the drain-induced barrier, thus suppressing the impact of the drain-induced barrier low (DIBL) on leakage current.

[0029] In some embodiments, in the direction from the first doped region 120 to the second doped region 130, the length of the first channel region 111 is 1 / 5 to 3 / 5 of the length of the channel region 110. It is understood that the wider the first channel region 111, the stronger its ability to neutralize charge carriers; conversely, the shorter the first channel region 111, the weaker its ability to neutralize charge carriers. When the length of the first channel region 111 is less than 1 / 5 of the length of the channel region 110, its effect on improving the barrier height between the first doped region 120 and the second doped region 130 is poor. When the length of the first channel region 111 is greater than 3 / 5 of the length of the channel region 110, too many charge carriers are neutralized, resulting in too few charge carriers flowing from the first doped region 120 to the second doped region 130, which affects the performance of the semiconductor structure.

[0030] In some embodiments, the gate 140 surrounds the entire surface of the channel region 110, that is, the gate 140 can be a fully surrounding gate. By setting the gate 140 to surround the entire surface of the channel region 110, the contact area between the gate and the channel region 110 can be increased, thereby improving the gate 140's control over the conduction between the first doped region 120 and the second doped region 130. In other embodiments, the gate 140 can also cover part of the surface of the channel region 110, such as covering the top and bottom surfaces of the channel region, or covering the top, bottom, and one side surface of the channel region, etc.

[0031] In some embodiments, a gate dielectric layer 141 is further included between the gate 140 and the active post 100, through which the gate 140 and the active post 100 can be isolated.

[0032] In some embodiments, the first doped region 120 is defined as the source region, and the first channel region 111 is adjacent to the source region. The second doped region 130 is then defined as the drain region. By setting the first channel region 111 adjacent to the source region, when both the source and drain regions are conducting, the first channel region 111 can neutralize some of the charge carriers, thereby increasing the potential barrier height between the source and drain regions. In other embodiments, the first doped region can also be defined as the drain region, and the first channel region is adjacent to the drain region.

[0033] In some embodiments, the doping concentration of the first channel region 111 is 1E16~1E18 cm⁻¹. -3 For example, 1E16cm -3 1E17cm -3 Or 1E18cm -3It is understandable that the higher the doping concentration of the first channel region 111, the stronger its ability to neutralize charge carriers; conversely, the lower the doping concentration of the first channel region 111, the weaker its ability to neutralize charge carriers. When the doping concentration of the first channel region 111 is below 1E16 cm⁻¹... -3 When the first channel region 111 is not effective in improving the barrier height between the first doped region 120 and the second doped region 130, the effect is not significant when the doping concentration of the first channel region 111 is higher than 1E18cm. -3 If too many charge carriers are neutralized, the number of charge carriers flowing from the first doped region 120 to the second doped region 130 will be too small, which will affect the performance of the semiconductor structure. This can be mitigated by setting the doping concentration of the first channel region 111 to 1E16~1E18 cm⁻¹. -3 This can ensure that the first channel region 111 has a good improvement effect while avoiding excessive carriers in the first channel region 111.

[0034] In some embodiments, the second doped region 130 includes a first sub-doped region 131 and a second sub-doped region 132. The first sub-doped region 131 is located between the second channel region 112 and the second sub-doped region 132, and the doping concentration of the first sub-doped region 131 is lower than the doping concentration of the second sub-doped region 132. By setting the doping concentration of the first sub-doped region 131 to be lower than the doping concentration of the second sub-doped region 132, the leakage current of the second doped region 130 can be reduced.

[0035] In some embodiments, the doping concentration of the second channel region 112 is equal to the doping concentration of the first sub-doped region 131. By setting the doping concentration of the second channel region 112 to be equal to the doping concentration of the first sub-doped region 131, it is easier to form, that is, the second channel region 112 and the first sub-doped region 131 can be formed in the same step, thereby reducing the number of formation steps in the semiconductor structure fabrication process.

[0036] In some embodiments, the doping concentration of the first sub-doped region 131 is 1E16~1E19 cm⁻¹. -3 The doping concentration of the second sub-doped region 132 is 1E19~1E22 cm⁻¹. -3 It is understandable that a higher doping concentration results in a greater number of charge carriers and stronger conductivity. However, a higher doping concentration also increases the likelihood of leakage. Therefore, the doping concentration of the first sub-doped region 131 is set to 1E16~1E19 cm⁻¹. -3 This reduces the possibility of leakage while ensuring the first sub-doped region 131 has a certain conductivity. The doping concentration of the second sub-doped region 132 is set to 1E19~1E22 cm⁻¹. -3This can give the second sub-doped region 132 a strong conductivity, thereby improving the conduction rate of the semiconductor structure.

[0037] In some embodiments, in the direction from the first doped region 120 toward the second doped region 130, the lengths of the first sub-doped region 131 and the second sub-doped region 132 are equal. In other words, in the second doped region 130, the volume of the region with low doping concentration is equal to the volume of the region with high doping concentration. That is, the second doped region 130 is divided equally, with half used for low concentration doping and the other half used for high concentration doping, thereby improving the conductivity of the second doped region while minimizing the possibility of leakage.

[0038] In some embodiments, in the direction from the first doped region 120 to the second doped region 130, the length of the first sub-doped region 131 can be 2 / 5 to 3 / 5 of the length of the second doped region 130. The wider the length of the first sub-doped region 131, the stronger its ability to improve the leakage current of the semiconductor structure. However, the wider the length of the first sub-doped region 131, the less the total amount of doped ions in the second doped region 130. By setting the length of the first sub-doped region 131 to be 2 / 5 to 3 / 5 of the length of the second doped region 130, the possibility of leakage current can be reduced while the conductivity of the second doped region can be improved.

[0039] In some embodiments, in the direction perpendicular to the first doped region 120 toward the second doped region 130, the thickness of the first channel region 111 is equal to the thickness of the second channel region 112. That is, the channel region 110 is divided into two regions along the direction perpendicular to the first doped region 120 toward the second doped region 130, one of which is the first channel region 111 and the other is the second channel region 112, and the thickness of the first channel region 111 is equal to the thickness of the second channel region 112. By setting the thickness of the first channel region 111 and the second channel region 112 to be equal, the barrier height between the first doped region 120 and the second doped region 130 can be improved.

[0040] In some embodiments, the system further includes a third channel region 113, which is adjacent to the first doped region 120. The first channel region 111 is located between the third channel region 113 and the gate 140, and the third channel region 113 has a first doping type. Taking the active pillar 100 as a cuboid as an example, in the direction perpendicular to the first doped region 120 toward the second doped region 130, the channel region 110 sequentially includes the first channel region 111, the third channel region 113, and the first channel region 111. That is, the channel region 110 includes two spaced first channels. Region 111, and the third channel region 113 is located between two adjacent first channel regions 111. It is understood that when a voltage is supplied to the gate 140, the carriers usually converge in the area where the active pillar 100 contacts the gate 140. By setting the first channel region 111 to be located where this part of the carriers converge, some carriers can be neutralized when the gate controls the first doped region 120 and the second doped region 130 to be turned on, thereby increasing the barrier height between the first doped region 120 and the second doped region 130, and thus increasing the threshold voltage of the semiconductor structure.

[0041] In some embodiments, the first channel region 111 may also wrap around the surface of the third channel region 113. That is, in the direction from the first doped region 120 to the second doped region 130, the third channel region penetrates the first channel region 111 and is adjacent to the first doped region 120 and the second channel region 112. Similarly, when the gate controls the first doped region 120 and the second doped region 130 to be turned on, some carriers can be neutralized, thereby increasing the barrier height between the first doped region 120 and the second doped region 130, and thus increasing the threshold voltage of the semiconductor structure.

[0042] In other embodiments, taking the active pillar 100 as a cuboid as an example, in the direction perpendicular to the first doped region 120 towards the second doped region 130, the channel region 110 sequentially includes a first channel region 111 and a third channel region 113. That is, the bottom surface of the third channel region 113 coincides with the bottom surface of the active pillar 100, and the top surface of the first channel region 111 coincides with the top surface of the active pillar 100. By setting the bottom surface of the third channel region 113 to coincide with the bottom surface of the active pillar 100 and the top surface of the first channel region 111 to coincide with the top surface of the active pillar 100, the barrier height between the first doped region 120 and the second doped region 130 can also be increased, thereby increasing the threshold voltage of the semiconductor structure.

[0043] In some embodiments, the system further includes a capacitor 150, which is in contact with the surface of the second sub-doped region 132. That is, the lower electrode plate of the capacitor 150 is in contact with the surface of the second sub-doped region 132. The capacitor 150, which is in contact with the surface of the second sub-doped region 132, is used to store data.

[0044] In some embodiments, the lower electrode plate of capacitor 150 may be the entire surface surrounding the second sub-doped region 132, or the lower electrode plate may only cover a portion of the surface of the second sub-doped region 132. The shape of the lower electrode plate of capacitor 150 may be set according to actual production requirements.

[0045] In some embodiments, capacitor 150 further includes: a capacitor dielectric layer and an upper electrode plate, wherein the capacitor dielectric layer is located on the surface of the lower electrode plate, and the upper electrode plate is located on the surface of the capacitor dielectric layer. The material of the lower electrode plate may include any one or any combination of metal materials such as titanium nitride, tantalum nitride, copper, or tungsten; the material of the capacitor dielectric layer may include any one or any combination of ZrO, AlO, ZrNbO, ZrHfO, and ZrAlO; the material of the upper electrode plate may include compounds formed from one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, titanium silicon nitride, or other conductive materials, or the material of the upper electrode plate may also be a conductive semiconductor material, such as polycrystalline silicon, germanium silicon, etc.

[0046] In some embodiments, the semiconductor structure further includes: a bit line 160, which is in contact with the surface of the first doped region 120 of the active pillar 100; the semiconductor structure further includes: a word line 180, which is in contact with the gate 140.

[0047] refer to Figure 3 The semiconductor structure can also be a stacked structure, that is, the semiconductor structure includes: active pillars 100 extending along a first direction X, and the active pillars 100 are spaced apart along a second direction Y and a third direction Z. In some embodiments, bit lines 160 extend along the second direction Y and are spaced apart along the third direction Z, and the active pillars 100 spaced apart along the second direction Y are connected to the same bit line 160; word lines 180 extend along the third direction Z and are spaced apart along the second direction Y, and the active pillars 100 spaced apart along the third direction Z are connected to the same word line 180.

[0048] refer to Figure 4 Bit line 160 extends along the third direction Z and is spaced along the second direction Y. Active pillars 100 spaced along the third direction Z are connected to the same bit line 160. Word line 180 extends along the second direction Z and is spaced along the third direction Y. Active pillars 100 spaced along the second direction Z are connected to the same word line 180.

[0049] In some embodiments, adjacent bit lines 160 are further further divided by a first isolation structure 170, which isolates adjacent bit lines 160 to improve the insulation between adjacent bit lines 160; adjacent word lines 180 are further divided by a second isolation structure 190, which isolates adjacent word lines 180 to improve the insulation between adjacent word lines 180.

[0050] In some embodiments, the first isolation structure 170 and the second isolation structure 190 may be made of the same material, such as insulating materials like silicon nitride or silicon oxide.

[0051] This embodiment of the present disclosure provides a first channel region 111 and a second channel region 112 between a first doped region 120 and a second doped region 130. The first channel region 111 is doped with a second doping type, while the first doped region 120, the second doped region 130, and the second channel region 112 are doped with a first doping type. This allows some carriers to be neutralized by the first channel region 111 during the flow of carriers from the first doped region 120 to the second doped region 130, thereby increasing the barrier height between the first doped region 120 and the second doped region 130 and increasing the threshold voltage of the semiconductor structure.

[0052] Another embodiment of this disclosure also provides a method for fabricating a semiconductor structure. This method can be used to fabricate the above-mentioned semiconductor structure. The method for fabricating the semiconductor structure provided by the embodiments of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions in the foregoing embodiments, and will not be repeated below.

[0053] refer to Figures 5 to 9 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figures 10 to 13 and Figure 1 This is a schematic diagram of the steps corresponding to the fabrication method of another semiconductor structure provided in an embodiment of the present disclosure. The difference between the two methods is that the doping order is different, and the same or corresponding steps are only described in one of the semiconductor structure fabrication methods.

[0054] Figures 5 to 9 The diagram is divided into AA view and BB view. AA view is a three-dimensional view corresponding to each step of the semiconductor structure fabrication process, while BB view is a cross-sectional view along the dotted line in AA view.

[0055] In some embodiments, a method for fabricating a semiconductor structure includes: providing an initial active pillar 101; performing ion doping on the initial active pillar 101 to form an active pillar 100; the active pillar 100 includes a channel region 110 and a first doped region 120 and a second doped region 130 located on both sides of the channel region 110; the channel region 110 includes a first channel region 111 and a second channel region 112; the first channel region 111 is adjacent to the first doped region 120; the second channel region 112 is adjacent to the second doped region 130 and located between the first channel region 111 and the second doped region 130; the first doped region 120, the second channel region 112, and the second doped region 130 all have a first doping type; the first channel region 111 has a second doping type; the first doping type is either N-type or P-type; and the second doping type is either N-type or P-type; and forming a gate 140 located on the surface of the channel region 110. By forming a first channel region 111 between the first doped region 120 and the second doped region 130 during the formation of the channel region 110, and by having an ion doping type different from that of the first doped region 120, some of the carrier ions can be neutralized by the first channel region 111 when the doped ions in the first doped region 120 move toward the second doped region 130. By introducing junction isolation between the first doped region 120 and the second doped region 130, leakage current between the first doped region 120 and the second doped region 130 can be prevented, thereby increasing the barrier height between the first doped region 120 and the second doped region 130, increasing the tunnel length of the band tunneling, and reducing the off-state leakage current between the first doped region 120 and the second doped region 130.

[0056] Understandably, electrons in the valence band of the P-block must possess energy exceeding the band gap to transition to the conduction band and then drift to the conduction band of the N-block. However, according to quantum theory, if the conduction band of the N-block is close enough to the valence band of the P-block, even if an electron lacks the energy to transition to the conduction band, it has the opportunity to tunnel directly from the valence band of the P-block to the conduction band of the N-block, much like a tunnel. This tunneling effect from the valence band to the conduction band is called band-to-band tunneling.

[0057] For details, please refer to Figure 5 Provides an initial active column 101.

[0058] refer to Figures 6 to 8The ion doping process includes: a first ion doping, forming a first doped region 120 and a second sub-doped region 132; a second ion doping, forming a first channel region 111; and a third ion doping, forming a second channel region 112 and a first sub-doped region 131. The doping concentration of the first sub-doped region 131 is less than that of the second sub-doped region 132. The first sub-doped region 131 and the second sub-doped region 132 constitute the second doped region 130. Multiple ion doping processes are used to form the corresponding channel region 110, the first doped region 120, and the second doped region 130. The formed second doped region 130 has a first sub-doped region 131 and a second sub-doped region 132. The doping concentration of the first sub-doped region 131 is less than that of the second sub-doped region 132, which can reduce the leakage current of the second doped region 130.

[0059] refer to Figure 6 The first ion doping includes: forming a first mask layer 200, which covers the surface of the channel region 110 and the first sub-doped region 131; and performing the first ion doping to ion-dope the second sub-doped region 132 and the first doped region 120. By forming the first mask layer 200 and covering the portions that do not need to be ion-doped, the length of the portions that need to be doped can be determined.

[0060] In some embodiments, the doping concentration of the first ion doping can be 1E19~1E22 cm⁻¹. -3 .

[0061] refer to Figure 7 The second ion doping includes: forming a second mask layer 210, which covers the surfaces of the first doped region 120 and the second sub-doped region 132; and performing a second ion doping to ion-dope the first channel region. By covering the second sub-doped region 132 and the first doped region 120 formed by the first ion doping with the second mask layer 210, the second ion doping can be prevented from affecting the second sub-doped region 132 and the first doped region 120.

[0062] In some embodiments, before forming the second mask layer 210, the method further includes removing the first mask layer 200.

[0063] In some embodiments, the dopant ion type of the first ion doping is a first doping type, and the dopant ion type of the second ion doping is a second doping type.

[0064] In some embodiments, the doping concentration of the second ion doping is 1E16~1E18 cm⁻¹. -3 .

[0065] refer to Figure 8 The third ion doping includes: forming a third mask layer 220, which covers the first channel region 111; and performing a third ion doping to ion-dope the second channel region 112 and the first sub-doped region 131. By forming the third mask layer 220, the first channel region 111 formed by the second ion doping can be covered, thereby preventing the third ion doping from affecting the first channel region 111.

[0066] In some embodiments, the doping concentration of the third ion doping is: 5E17~1E19 cm⁻¹ -3 It is understandable that during the second ion doping process, the second channel region 112 and the first sub-doped region 131 are also doped. Therefore, before the third ion doping, the ions in the second channel region 112 and the first sub-doped region 131 are of the second doping type. At this time, the second channel region 112 and the first sub-doped region 131 need to be doped with a higher concentration of the first doping type to neutralize the second doping type in the second channel region 112 and the first sub-doped region 131.

[0067] In some embodiments, the first mask layer 200, the second mask layer 210, and the third mask layer 220 may be made of the same material, while in other embodiments, the first mask layer 200, the second mask layer 210, and the third mask layer 220 may be made of different materials.

[0068] refer to Figure 9 A gate dielectric layer 141 is formed on the surface of the channel region 110, and a gate 140 is formed on the surface of the gate dielectric layer 141.

[0069] refer to Figures 10 to 13 and Figure 1 This is a schematic diagram showing the structural steps corresponding to each step of a method for fabricating another semiconductor structure according to an embodiment of this disclosure. Specifically, refer to... Figure 10 Provides an initial active column 101.

[0070] refer to Figure 11 The initial active pillar 101 is doped with the second type of doped ions to form the first channel region 111.

[0071] refer to Figure 12 ,right Figure 11 The active pillar formed in the middle is ion-doped to form a first doped region 120 and a second sub-doped region 132, and the doped ion type is the first doping type.

[0072] refer to Figure 13 ,right Figure 12The active pillar 100 formed in the middle is ion-doped to form a second channel region 112 and a first sub-doped region 131, and the doped ion type is the first doping type.

[0073] refer to Figure 1 A gate dielectric layer 141 and a gate 140 are formed.

[0074] In this embodiment, a first channel region 111 is formed between the first doped region 120 and the second doped region 130 when the channel region 110 is formed. The ion doping type of the first channel region 111 is different from that of the first doped region 120. This allows some of the carrier ions to be neutralized by the first channel region 111 when the doped ions in the first doped region 120 move toward the doped ions in the second doped region 130. By introducing junction isolation between the first doped region 120 and the second doped region 130, leakage between the first doped region 120 and the second doped region 130 can be prevented. This increases the barrier height between the first doped region 120 and the second doped region 130, increases the tunnel length of the band tunneling, and reduces the off-state leakage between the first doped region 120 and the second doped region 130.

[0075] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: An active pillar includes a channel region and a first doped region and a second doped region located on both sides of the channel region. The channel region includes a first channel region and a second channel region. The first channel region is adjacent to the first doped region, and the second channel region is adjacent to the second doped region and located between the first channel region and the second doped region. The first doped region, the second channel region, and the second doped region all have a first doping type. The first channel region has a second doping type. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. A gate, which is located on the surface of the channel region.

2. The semiconductor structure according to claim 1, characterized in that, In the direction from the first doped region to the second doped region, the length of the first channel region is 1 / 5 to 3 / 5 of the length of the channel region.

3. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the first channel region is 1E16~1E18 cm⁻¹ -3 .

4. The semiconductor structure according to claim 1, characterized in that, The second doped region includes a first sub-doped region and a second sub-doped region, wherein the first sub-doped region is located between the second channel region and the second sub-doped region, and the doping concentration of the first sub-doped region is lower than the doping concentration of the second sub-doped region.

5. The semiconductor structure according to claim 4, characterized in that, The doping concentration of the second channel region is equal to the doping concentration of the first sub-doped region.

6. The semiconductor structure according to claim 4, characterized in that, The doping concentration of the first sub-doped region is 1E16~1E19 cm⁻¹ -3 The doping concentration of the second sub-doped region is 1E19~1E22 cm⁻¹ -3 .

7. The semiconductor structure according to claim 4, characterized in that, In the direction from the first doped region to the second doped region, the lengths of the first sub-doped region and the second sub-doped region are equal.

8. The semiconductor structure according to claim 4, characterized in that, Also includes: A capacitor that is in contact with the surface of the second sub-doped region.

9. The semiconductor structure according to claim 1, characterized in that, The gate surrounds the entire surface of the channel region.

10. The semiconductor structure according to claim 1, characterized in that, In the direction perpendicular to the first doped region toward the second doped region, the thickness of the first channel region is equal to the thickness of the second channel region.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: A third channel region is adjacent to the first doped region, the first channel region is located between the third channel region and the gate, and the third channel region has a first doping type.

12. A method for fabricating a semiconductor structure, characterized in that, include: An initial active pillar is provided, and the initial active pillar is ion-doped to form an active pillar. The active pillar includes a channel region and a first doped region and a second doped region located on both sides of the channel region. The channel region includes a first channel region and a second channel region. The first channel region is adjacent to the first doped region, and the second channel region is adjacent to the second doped region and located between the first channel region and the second doped region. The first doped region, the second channel region, and the second doped region all have a first doping type. The first channel region has a second doping type. The first doping type is either N-type or P-type, and the second doping type is either N-type or P-type. A gate is formed, the gate being located on the surface of the channel region.

13. The method for fabricating a semiconductor structure according to claim 12, characterized in that, The ion doping includes: The first ion doping is used to form the first doped region and the second sub-doped region. The second ion doping is used to form the first channel region; A third ion doping process is performed to form the second channel region and the first sub-doped region. The doping concentration of the first sub-doped region is less than that of the second sub-doped region. The first sub-doped region and the second sub-doped region constitute the second doped region.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The first ion doping includes: forming a first mask layer, the first mask layer covering the surface of the channel region and the first sub-doped region; The first ion doping is performed to ion dope the second sub-doped region and the first doped region.

15. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The second ion doping includes: A second mask layer is formed, which covers the surfaces of the first doped region and the second sub-doped region; The second ion doping is performed to ion dope the first channel region.

16. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The third ion doping includes: A third mask layer is formed, which covers the first channel region; The third ion doping is performed to ion dope the second channel region and the first sub-doped region.

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