Programmable watchdog and timer logic ip design method for feiteng processor

Abstract

The application discloses a programmable watchdog and timer logic IP design method for a Feiteng processor, a watchdog timeout time register is designed in the watchdog logic IP, a watchdog reset logic carries out internal counting according to the set time, combines the state of a watchdog feeding signal and a watchdog enable signal, and outputs a watchdog reset signal when the counter reaches the value corresponding to the timeout time, so that the programmability of the watchdog timeout time is realized. The timer logic IP realizes the counting control of the programmable timer by instantiating a timer period, a timer emptying and a timer starting register, and outputs an external interrupt to the domestic Feiteng processor after the counter reaches the set value. The application effectively expands the timer resource of the domestic embedded system based on the Feiteng processor.

Description

Technical Field

[0001] This invention belongs to the field of embedded design technology, specifically relating to a design method for a programmable watchdog and timer logic IP. Background Technology

[0002] Watchdog reset functionality is used in embedded systems for automatic reset control in case of application execution exceptions. Hardware watchdog reset functionality can be implemented using a watchdog reset chip, but the timeout period is limited by the hardware state of the watchdog reset chip and is generally a fixed time. With the increasing variability of application scenarios, airborne embedded systems require programmable watchdog reset functionality. This can be achieved by instantiating a logic IP and controlling the watchdog timeout period according to system needs, thereby increasing the scalability and flexibility of the watchdog logic IP.

[0003] In embedded systems, programmable timers can be programmed to periodically trigger timer interrupts at software-defined intervals, causing the processor to enter an interrupt service routine to handle the interrupt task. Currently, domestically produced Phytium processors lack an internal timer and cannot implement timer interrupts. To expand the functionality of embedded systems based on domestic Phytium processors, timer interrupt control can be implemented by instantiating logic IPs. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a design method for a programmable watchdog and timer logic IP for Phytium processors. The watchdog logic IP incorporates a watchdog timeout register. The watchdog reset logic performs an internal count based on a pre-set time, combined with the states of the watchdog feed and enable signals. When the counter reaches the timeout value, a watchdog reset signal is output, thus achieving programmability of the watchdog timeout. The timer logic IP implements programmable timer counting control through instantiation of the timer period, timer clear, and timer start registers. When the counter reaches a set value, the logic chip outputs an external interrupt to the Phytium processor. This invention effectively expands the timer resources of domestically produced embedded systems based on Phytium processors.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows:

[0006] Step 1: Reset the watchdog control logic;

[0007] The watchdog reset control logic is used to control the timing of the watchdog reset output; when the watchdog timeout configuration chip select Wdg_time_csn is valid, the timeout time is written to the watchdog timeout time register through the Phytium processor's LBC interface;

[0008] In application mode, the watchdog feed signal Wdg_wdi and the watchdog enable register wdg_en are read and counted using a logic reference clock. When the count value reaches the value configured in the watchdog timeout register, the watchdog is reset, which resets the Phytium processor and all interfaces.

[0009] Step 2: Timer reset control logic;

[0010] The timer is instantiated in the logic IP and configured through the Phytium processor's LBC interface, which controls the timer period (Timer_period), timer clear (Timer_clear), and timer start (Timer_start) registers.

[0011] When the timer clear signal is valid, the timer counter register is cleared; when the timer clear signal is invalid and the timer start signal is valid, the timer counter register is incremented. When the count value reaches the set value of the timer period register, an external interrupt is output to the Phytium processor.

[0012] Step 3: Phytium processor;

[0013] The Phytium processor receives the reset signal from the watchdog reset logic output to reset itself, reload and run the software; the Phytium processor receives the timer interrupt signal from the timer output of the instantiated timer in the logic IP through an external interrupt, enters the interrupt service routine, and executes the interrupt task.

[0014] The beneficial effects of this invention are as follows:

[0015] This invention realizes the programmability of the watchdog timer in domestic embedded systems and extends the timer function of the Phytium processor through logic IP. Attached Figure Description

[0016] Figure 1 This is a block diagram of the SPI interface logic IP of the present invention. Detailed Implementation

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0018] The purpose of this invention is to provide an extended programmable watchdog and timer logic IP design for domestic Phytium processors, enabling the watchdog reset timeout to be settable and extending the timer function of domestic Phytium processors.

[0019] To achieve the above objectives, this invention is implemented using the standard Verilog language and based on a domestically produced CPLD hardware platform.

[0020] This invention discloses an extended programmable watchdog and timer logic IP design for a domestic Phytium processor. The implementation involves instantiating a watchdog timeout register within the logic, which can be written to via an LBC interface. In application mode, the watchdog reset logic reads the watchdog feed signal and the state of the watchdog enable register, counts using a logic reference clock, and when the count reaches the value corresponding to the timeout period, the logic IP outputs a watchdog reset signal to reset the CPU and all interfaces. The extended timer section instantiates timer period, timer clear, and timer start control registers. Using the logic reference clock as the trigger condition, when the timer clear signal is valid, the timer count register is cleared; when the timer clear signal is invalid and the timer start signal is valid, the timer count register is incremented. When the count reaches the set value of the timer period register, an external interrupt is triggered, and an interrupt signal is output to the Phytium processor. This technology allows the Phytium processor to periodically enter interrupt mode and execute interrupt service routines according to a preset cycle.

[0021] This invention achieves the following functions:

[0022] By configuring and controlling the watchdog timeout register, timer period register, timer clear register, and timer start control registers in the logic IP through the LBC interface of the domestic Phytium processor, the programmability of the watchdog reset function of the domestic embedded system and the functional expansion of the timer of the domestic processor can be realized.

[0023] The timeout of the programmable watchdog timer is controlled by writing to the corresponding registers through the LBC interface of the domestic Phytium processor, thus achieving programmability;

[0024] The timer period register, timer clear register, and timer start control registers in the timer logic IP can be configured through the LBC interface of the domestic Phytium processor;

[0025] After configuring the registers such as the timer period register, timer clear register, and timer start control in the timer logic IP, the timer can be instantiated and implemented through timing control, thus extending the timer function of the domestic embedded system. Specific implementation examples:

[0027] The block diagram for the design and implementation of the extended programmable watchdog and timer logic IP for domestic Phytium processors is as follows: Figure 1 As shown, it includes:

[0028] 1. Watchdog reset control logic

[0029] The watchdog reset control logic is used to control the timing of the watchdog reset output. When the watchdog timeout configuration chip select (Wdg_time_csn) is valid, the timeout period is written to the watchdog timeout register via the Phytium processor's LBC interface. In application mode, the status of the watchdog feed signal (Wdg_wdi) and the watchdog enable register (wdg_en) can be read, and a count is performed using a logic reference clock. When the count value reaches the value configured in the watchdog timeout register, a watchdog reset is triggered, resetting the CPU processor and all interfaces.

[0030] 2. Timer reset control logic

[0031] The timer is instantiated in this logic IP, and the timer period (Timer_period), timer clear (Timer_clear), and timer start control (Timer_start) registers are configured through the Phytium processor's LBC interface. When the timer clear signal is valid, the timer counter register is cleared. When the timer clear signal is invalid and the timer start signal is valid, the timer counter register is incremented. When the count value reaches the set value of the timer period register, an external interrupt is output to the Phytium processor.

[0032] 3. Domestic Phytium processor

[0033] The domestically produced Phytium processor receives the reset signal from the watchdog reset logic to reset itself, reload, and run the software. It also receives timer interrupt signals from the timer instantiated in the logic IP via an external interrupt, enters the interrupt service routine, and executes the interrupt task.

Claims

1. A method for designing a programmable watchdog and timer logic IP for a Phytium processor, characterized in that, Includes the following steps: Step 1: Reset the watchdog control logic; The watchdog reset control logic is used to control the timing of the watchdog reset output; when the watchdog timeout configuration chip select Wdg_time_csn is valid, the timeout time is written to the watchdog timeout time register through the Phytium processor's LBC interface; In application mode, the watchdog feed signal Wdg_wdi and the watchdog enable register wdg_en are read and counted using a logic reference clock. When the count value reaches the value configured in the watchdog timeout register, the watchdog is reset, which resets the Phytium processor and all interfaces. Step 2: Timer reset control logic; The timer is instantiated in the logic IP and configured through the Phytium processor's LBC interface, which controls the timer period (Timer_period), timer clear (Timer_clear), and timer start (Timer_start) registers. When the timer clear signal is valid, the timer counter register is cleared; when the timer clear signal is invalid and the timer start signal is valid, the timer counter register is incremented. When the count value reaches the set value of the timer period register, an external interrupt is output to the Phytium processor. Step 3: Phytium processor; The Phytium processor receives the reset signal from the watchdog reset logic output to reset itself, reload and run the software; the Phytium processor receives the timer interrupt signal from the timer output of the instantiated timer in the logic IP through an external interrupt, enters the interrupt service routine, and executes the interrupt task.

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