Decoder, chip, high-speed serial transmission interface and electronic device

Abstract

This application relates to a decoder, a chip, a high-speed serial transmission interface, and an electronic device, belonging to the field of electronic technology. The decoder is used to decode N parallel input channels of first target data and N parallel input channels of second target data into parallel N-bit PRBS data output. The N channels of first target data are data obtained after serial-to-parallel conversion of first sampled data, and the N channels of second target data are data obtained after serial-to-parallel conversion of second sampled data. The first sampled data is data obtained by sampling encoded data using a first sampling threshold, and the second sampled data is data obtained by sampling encoded data using a second sampling threshold. N is an even number greater than or equal to 4. Because this decoder can be located after the serial-to-parallel conversion circuit, the high-frequency clock requirement of the decoder can be significantly reduced, thereby reducing the power consumption on the clock and increasing the upper limit of the decoder's operating speed.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a decoder, a chip, a high-speed serial transmission interface, and an electronic device. Background Technology

[0002] The schematic diagram of the high-speed serial transmission interface is as follows: Figure 1 As shown, it includes a transmitter and a receiver. The difference from a traditional source-synchronous parallel transmission interface is that the transmitter does not need to transmit a synchronization clock while transmitting data to the receiver. Traditional source-synchronous parallel interfaces require the transmitter to transmit a synchronization clock while transmitting data to the receiver. The transmitter is mainly used to encode the parallel input N-bit PRBS (Pseudo Random Binary Sequence) data into L, H, and M signals that satisfy the PAM3 (3Pulse Amplitude Modulation) communication protocol. The L signal represents signal 0; the M signal can represent either signal 0 or signal 1, depending on the encoding of the previous data. For example, if the previous data was encoded as L, then the M bits are signal 0; if the previous data was encoded as H, then the M bits are signal 1. The H signal represents signal 1. The decoder at the receiver decodes the L, H, and M signals into the corresponding PRBS data based on the clock signal (Rxclk). The clock signal (Rxclk) is recovered by the clock recovery circuit based on the transition edges of the L, H, and M signals.

[0003] The principle of existing decoders is as follows Figure 2 As shown, the corresponding waveform timing diagram is as follows: Figure 3 As shown in the diagram. Here, TxDat is the original data before encoding, PAD is the encoded data, ah (first sampled data) is the signal sampled by a comparator using vh as the threshold, and al (second sampled data) is the signal sampled by a comparator using vl as the threshold. For decoding the encoded data, level L is decoded into a 0 signal, level H is decoded into a 1 signal, and level M is determined based on the data decoded from the previous bit. If the data decoded from the previous bit is 0, level M will be decoded into a 0 signal; if the data decoded from the previous bit is 1, level M will be decoded into a 1 signal. Using data... <n>This represents the currently solved data, data <n-1>If the data obtained from the previous bit is represented, then the decoding process satisfies the formula data. <n>=(data <n-1>==1'b0)? ah:al, that is, if data <n-1>=0, then data <n>=ah, otherwise data <n>=al. For mux_odd, data_even is its previous bit of data, and for mux_even, data_odd is its previous bit of data, so its decoding process satisfies the formula mux_odd = (data_even == 1'b0) ? ah:al; mux_even = (data_odd == 1'b0) ? ah:al.

[0004] For this decoder to function correctly, the timing must satisfy T0 + T1 + T2 < 1UI. Here, UI is the time difference between the rising edge of Rxclkp and the rising edge of Rxclkn (e.g., ...). Figure 3 As shown), these two rising edges correspond to Figure 2 The sampling clocks for `data_even` and `data_odd` are specified. To ensure that the clock of `Rxclkn` can sample the correct decoded data, the timing relationship T0 + T1 + T2 < 1UI must be satisfied. T0 is the delay from the rising edge of `Rxclkp` to the `clk` input of the D1 flip-flop and its Q output `data_even`; T1 is the combinational logic delay from the Q output of `data_even` of the D1 flip-flop to the D input of the D2 flip-flop via `mux_odd`; T2 is the setup time of the D2 flip-flop. When the data transmission rate increases significantly, UI becomes very small, and the three physical parameters T0, T1, and T2 do not change with the data transmission rate. Therefore, when the data transmission rate increases, a situation where T0 + T1 + T2 > 1UI can easily occur, which will cause the decoder to malfunction and result in decoding errors. Summary of the Invention

[0005] Therefore, the purpose of this application is to provide a decoder, chip, high-speed serial transmission interface and electronic device to improve the existing decoder, which is prone to malfunction and decoding errors when the data transmission rate is greatly increased.

[0006] The embodiments of this application are implemented as follows:

[0007] In a first aspect, embodiments of this application provide a decoder for decoding N parallel input channels of first target data and N parallel input channels of second target data into parallel N-bit PRBS data output. The N channels of first target data are data obtained by serial-to-parallel conversion of first sampled data, and the N channels of second target data are data obtained by serial-to-parallel conversion of second sampled data. The first sampled data is data obtained by sampling encoded data using a first sampling threshold, and the second sampled data is data obtained by sampling the encoded data using a second sampling threshold. N is an even number greater than or equal to 4.

[0008] In this embodiment, the decoder shown in this application can decode N parallel input channels of first target data and N parallel input channels of second target data into parallel N-bit PRBS data output. This allows the decoder to be located after the serial-to-parallel conversion circuit. Since the data rate of serial transmission is faster than that of parallel transmission, placing the decoder after the serial-to-parallel conversion circuit significantly reduces the decoder's requirement for a high-frequency clock, thereby reducing the power consumption on the clock and increasing the upper limit of the decoder's operating speed. Simultaneously, the change in the decoder's position significantly reduces the data rate input to the decoder, and the clock frequency required by the decoder also decreases, thus reducing the risk of the decoder malfunctioning and encountering decoding errors.

[0009] In one possible implementation of the first aspect embodiment, the decoder includes: N decoding circuits and a trigger, each of the N decoding circuits being used to obtain a corresponding PRBS data bit based on one data bit from the N first target data, one data bit from the N second target data, and a specified signal; the trigger has its data input terminal connected to the last decoding circuit in the N decoding circuits and its output terminal connected to the first decoding circuit in the N decoding circuits; wherein i takes values ​​from 1 to N sequentially, for the i-th decoding circuit in the N decoding circuits, when i = 1, the specified signal is the data signal output by the trigger, and when i is greater than 1, the specified signal is the internal signal output by the (i-1)-th decoding circuit.

[0010] In this embodiment, by adopting the structure of the above-mentioned N-channel decoding circuit and flip-flops, the decoder shown in this application can decode the parallel input of N channels of first target data and N channels of second target data into parallel N-bit PRBS data output. This allows the decoder to be located after the serial-to-parallel conversion circuit. Since the data rate of serial transmission is faster than that of parallel transmission, placing the decoder after the serial-to-parallel conversion circuit can significantly reduce the decoder's requirement for a high-frequency clock, thereby reducing the power consumption consumed on the clock and increasing the upper limit of the decoder's operating speed.

[0011] In one possible implementation of the first aspect embodiment, the i-th decoding circuit includes: a selection unit and a sample-and-hold unit; the selection unit is used to selectively output one data from the N first target data or one data from the N second target data according to a specified signal input to itself, to obtain an internal signal; wherein, when i=1, the specified signal input to the selection unit in the i-th decoding circuit is the data signal output by the flip-flop, and when i is greater than 1, the specified signal input to the selection unit in the i-th decoding circuit is the output signal of the selection unit in the (i-1)-th decoding circuit; the sample-and-hold unit is connected to the output terminal of the selection unit, and the sample-and-hold unit is used to sample the output data of the selection unit and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one bit of PRBS data.

[0012] In this embodiment of the application, each decoding circuit includes a selection unit and a sample-and-hold unit. Through the cooperation of these two modules, the function of obtaining one PRBS data bit based on one of the N first target data, one of the N second target data, and a specified signal is realized, thereby completing the decoding function.

[0013] In one possible implementation of the first aspect embodiment, the selection unit includes: a selector, a first input terminal of which is used to receive one data from the N first target data, and a second input terminal of which is used to receive one data from the N second target data; the selector is used to selectively output one data from the N first target data or one data from the N second target data according to a specified signal input to itself.

[0014] In the embodiments of this application, a hardware circuit such as a selector is used to implement its function. While achieving the purpose of the invention, it can avoid the problems caused by implementing the same function in software, such as the defects of software being prone to running errors and requiring additional programming.

[0015] In one possible implementation of the first aspect embodiment, the sample-and-hold unit includes a flip-flop, the data input terminal of which is connected to the output terminal of the selection unit. The flip-flop is used to sample the output data of the selection unit according to the input clock signal and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one bit of PRBS data.

[0016] In this embodiment, a trigger is used to sample the output data of the selection unit and keep the sampled data unchanged for a certain period of time to obtain the corresponding one-bit PRBS data. While achieving the purpose of the invention, it can avoid the problems caused by implementing the same function in software, such as the defects of software being prone to running errors and requiring additional programming.

[0017] Secondly, embodiments of this application also provide a chip, including two serial-to-parallel converters and a decoder as provided in any possible implementation of the first aspect embodiment and / or in combination with the first aspect embodiment; one of the serial-to-parallel converters is used to perform serial-to-parallel conversion on first sampled data to obtain N channels of first target data, wherein the first sampled data is data obtained by sampling encoded data with a first sampling threshold; the other serial-to-parallel converter is used to perform serial-to-parallel conversion on second sampled data to obtain N channels of second target data, wherein the second sampled data is data obtained by sampling the encoded data with a second sampling threshold.

[0018] In one possible implementation of the second aspect embodiment, each of the serial-to-parallel converters includes: a first serial-to-parallel conversion circuit and a second serial-to-parallel conversion circuit; the first serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on the first sampled data or the second sampled data to obtain two intermediate data streams; the second serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on the two intermediate data streams to obtain the N first target data streams or the N second target data streams.

[0019] In one possible implementation of the second aspect embodiment, the first serial-to-parallel conversion circuit includes: a first flip-flop and a second flip-flop; the first flip-flop is used to sample the first sampled data or the second sampled data according to an input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining one intermediate data among the two intermediate data; the second flip-flop is used to sample the first sampled data or the second sampled data according to an input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining the other intermediate data among the two intermediate data; wherein, the input data of the first flip-flop is the same as the input data of the second flip-flop, and the clock signal of the first flip-flop is opposite to the clock signal of the second flip-flop.

[0020] Thirdly, embodiments of this application also provide a high-speed serial transmission interface, including: a data transmitting end and a data receiving end; the data receiving end includes a chip provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments.

[0021] Fourthly, embodiments of this application also provide an electronic device, including: a body and a chip provided as described in the second aspect embodiments and / or in combination with the second aspect embodiments, or a high-speed serial transmission interface provided as described in the second aspect embodiments.

[0022] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The above and other objects, features, and advantages of this application will become clearer through the drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale to actual size; the focus is on illustrating the main points of this application.

[0024] Figure 1 This is a schematic diagram of a high-speed serial transmission interface in the prior art.

[0025] Figure 2 This is a schematic diagram of the principle of a decoder in the prior art.

[0026] Figure 3 for Figure 2 The waveform diagram of the timing involved in the decoder.

[0027] Figure 4 This is a schematic diagram of the structure of a decoder provided in an embodiment of this application.

[0028] Figure 5 This is a schematic diagram of the structure of another decoder provided in an embodiment of this application.

[0029] Figure 6 This is a schematic diagram of the circuit principle of a decoder provided in an embodiment of this application.

[0030] Figure 7 This is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0031] Figure 8 This is a schematic diagram of the structure of another chip provided in an embodiment of this application.

[0032] Figure 9 This is a schematic diagram of a chip provided in an embodiment of this application.

[0033] Figure 10 This is a schematic diagram of a high-speed serial transmission interface provided in an embodiment of this application. Detailed Implementation

[0034] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0035] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., used in the description of this application are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, article, or apparatus that includes said element.

[0036] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0037] Given existing decoders, when the data transmission rate increases significantly, the decoder is prone to malfunction, resulting in decoding errors. After careful research, the inventors of this application discovered that, because the data transmission rate is faster than the parallel transmission rate, such as... Figure 1 In this circuit, the data rate for 4-channel parallel transmission is 1.6Gbps, while the data rate for serial transmission is 6.4Gbps. Placing the decoder before the serial-to-parallel conversion circuit significantly increases the decoder's operating frequency. However, the increased data transmission rate further reduces the time difference (UI) between the rising edge of Rxclkp and the rising edge of Rxclkn, potentially causing the decoder to malfunction and produce decoding errors. This also increases the receiver's demand for a higher-frequency clock, resulting in significantly higher power consumption from the clock signal.

[0038] The inventors of this application have discovered that by moving the decoder from before to after the serial-to-parallel conversion circuit, the high-speed serial data decoding is transformed into low-speed parallel data decoding. This significantly reduces the receiver's requirement for a high-frequency clock, lowers the decoder's operating frequency, and consequently reduces the power consumption on the clock. Simultaneously, the change in the decoder's position drastically reduces the data rate input to the decoder, thus preventing the decoder from malfunctioning and causing decoding errors.

[0039] It should be emphasized that the defects of the above solutions are the result of the inventors' practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the inventors in the embodiments of the present invention below should be considered as contributions made by the inventors to the present invention.

[0040] As the input data of the decoder changes from high-speed serial data decoding to low-speed parallel data decoding, the existing structure is no longer applicable. After repeated research, the inventors of this application propose a completely new decoder, which is used to decode N parallel input first target data (such as data_h) <n:1>(represented by) N-way second target data (e.g., using data_l) <n:1>(represented), decoded into parallel N-bit PRBS data (e.g., using data) <n:1>The output is represented as follows: N channels of first target data are the data obtained after serial-to-parallel conversion of the first sampled data (e.g., 'ah'), and N channels of second target data are the data obtained after serial-to-parallel conversion of the second sampled data (e.g., 'al'). The first sampled data is the data obtained by sampling the encoded data (e.g., PAD signal) with a first sampling threshold (e.g., 'vh'), and the second sampled data is the data obtained by sampling the encoded data with a second sampling threshold (e.g., 'vl'). N is an even number greater than or equal to 4, such as 4, 6, 8, 10, 12, 14, 16, etc.

[0041] The structural diagram of the decoder is as follows: Figure 4 As shown. It includes: a flip-flop (e.g., denoted by D0) and an N-channel decoding circuit.

[0042] The data input terminal (e.g., D terminal) of the flip-flop is connected to the last decoding circuit (i.e., the Nth circuit) in the N-channel decoding circuit, and its output terminal (e.g., Q terminal) is connected to the first decoding circuit in the N-channel decoding circuit. The flip-flop can be a D flip-flop, or it can be another flip-flop that implements the same clock sampling logic function as a D flip-flop, such as a level-sampling flip-flop (latch).

[0043] Each decoding circuit in the N-channel decoding circuitry is used to obtain a corresponding one-bit PRBS data based on one data point from the N channels of first target data, one data point from the N channels of second target data, and a specified signal. Here, i takes values ​​from 1 to N sequentially. For the i-th decoding circuit in the N-channel decoding circuitry, when i = 1, the specified signal is the data signal output by the flip-flop; when i is greater than 1, the specified signal is the internal signal output by the (i-1)-th decoding circuit (e.g., using a mux). <i-1>express).

[0044] For example, the first decoding circuit is used to decode one of the N channels of first target data (e.g., using data_h). <1> (represented as) one of the N-way second target data (e.g., using data_l) <1> (representation) and the data signal output by the trigger (such as using a mux) <n>(_delay represents), to obtain the corresponding one-bit PRBS data (e.g., using data). <1> (represented); the second decoding circuit is used to decode one of the N channels of first target data (e.g., using data_h). <2> (represented as) one of the N-way second target data (e.g., using data_l) <2> (represented) and the internal signal output from the first decoding circuit (e.g., using a mux) <1> (represented), to obtain the corresponding one-bit PRBS data (e.g., using data). <2> (representation); the third decoding circuit is used to decode one of the N channels of first target data (e.g., using data_h). <3> (represented as) one of the N-way second target data (e.g., using data_l) <3> (represented) and the internal signal output from the second decoding circuit (such as using a mux) <2> (represented), to obtain the corresponding one-bit PRBS data (e.g., using data). <3> (represented); and so on, the Nth decoding circuit is used to decode one of the N first target data streams (e.g., using data_h). <n>(represented as) one of the N-way second target data (e.g., using data_l) <n>(represented) and the internal signal output from the (N-1)th decoding circuit (e.g., using a mux) <n-1>(represented), to obtain the corresponding one-bit PRBS data (e.g., using data). <n>express)

[0045] Each decoding circuit includes: a selection unit and a sample-and-hold unit, such as Figure 5 As shown.

[0046] The selection unit is used to selectively output one data from the N first target data or one data from the N second target data according to the specified signal input to itself, to obtain an internal signal. When i = 1, the specified signal input to the selection unit in the i-th decoding circuit is the data signal output by the flip-flop. When i is greater than 1, the specified signal input to the selection unit in the i-th decoding circuit is the output signal of the selection unit in the (i-1)-th decoding circuit.

[0047] The sample-and-hold unit is connected to the output of the selection unit. The sample-and-hold unit is used to sample the output data of the selection unit and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one-bit PRBS data.

[0048] In one implementation, the selection unit can be a software functional module, in which case the above functions are implemented in software; in another implementation, the selection unit is a hardware circuit.

[0049] When the selection unit is a hardware circuit, in one embodiment, the selection unit includes: a selector, the first input terminal of the selector is used to receive one data from N first target data, the second input terminal of the selector is used to receive one data from N second target data; the selector is used to selectively output one data from the N first target data or one data from the N second target data according to the specified signal input to itself.

[0050] In one implementation, the sample-and-hold unit can be a software functional module, in which case the above functions are implemented in software; in another implementation, the sample-and-hold unit is a hardware circuit.

[0051] When the sample-and-hold unit is a hardware circuit, in one embodiment, the sample-and-hold unit includes a flip-flop. The data input terminal of the flip-flop is connected to the output terminal of the selection unit. The flip-flop is used to sample the output data of the selection unit according to the input clock signal and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one bit of PRBS data.

[0052] In this embodiment, the position of the decoder is moved from before the serial-to-parallel conversion circuit to after the serial-to-parallel conversion circuit, changing the high-speed serial data decoding to low-speed parallel data decoding. This greatly reduces the data rate processed by the decoder. For example, taking N=8 as an example, the data rate processed by the decoder is reduced to 1 / 8 of the data rate on the PAD, thereby solving the timing problem of the decoder.

[0053] In one alternative implementation, the circuit schematic of the decoder is as follows: Figure 6 As shown. It should be noted that the value of N is not limited to 8; therefore, it cannot be... Figure 6 The case shown where N=8 is to be understood as a limitation of this application.

[0054] data_h<8:1> and data_l<8:1> are the input data of the decoder. The clk4 signal is the input clock signal of the decoder, which is a 4-division clock of Rxclkp. data<8:1> is the output data of the decoder, with the least significant bit data transmitted first.

[0055] The decoding principle is the same as that of the background technology: data <n>=(data <n-1>==1'b0)?data_h <n>:data_l <n>The decoding principle is that if the previous bit of data is 0, then the current output data is... <n>Select data_h <n>Otherwise, choose data_l <n>For example: mux <1> =0, data <2> =data_h <2> mux <1> =1, data <2> =data_l <2> .

[0056] In terms of timing, data is output from the last bit. <8> Let's look at mux. <8> Before reaching the D8 flip-flop, the clock signal clk4 of the D8 flip-flop will have a setup time T2, mux <8> From mux <1> The result is calculated with a delay of T1*7, and the D0 trigger outputs a mux. <8> _delay to selector output mux <1> The delay between them is T1. The rising edge of the clk4 clock reaches the clock input (Clk) of the D0 flip-flop and outputs dmux at its Q output. <8> The delay of _delay is T0.

[0057] Therefore, the timing requirement for the entire decoder is T0 + T1*8 + T2 < 8UI, where 8UI is one clock cycle of the clk4 clock signal. Thus, the design proposed in this patent significantly reduces the timing requirements, allowing the decoder to operate at higher speeds.

[0058] Based on the same inventive concept, this application also provides a chip, such as... Figure 7 As shown, it includes two serial-to-parallel converters and the decoder mentioned above.

[0059] One serial-to-parallel converter is used to convert the first sampled data (e.g., ah) into serial-to-parallel data to obtain N channels of first target data, wherein the first sampled data is the data obtained by sampling the encoded data with a first sampling threshold (e.g., vh). The other serial-to-parallel converter is used to convert the second sampled data (e.g., al) into serial-to-parallel data to obtain N channels of second target data, wherein the second sampled data is the data obtained by sampling the encoded data with a second sampling threshold (e.g., vl).

[0060] In one optional implementation, each serial-to-parallel converter includes: a first serial-to-parallel conversion circuit and a second serial-to-parallel conversion circuit, such as... Figure 8 As shown. The first serial-to-parallel conversion circuit is used to convert the first sampled data or the second sampled data into serial-to-parallel data to obtain two intermediate data streams; the second serial-to-parallel conversion circuit is used to convert the two intermediate data streams into serial-to-parallel data to obtain N first target data streams or N second target data streams.

[0061] One of the first serial-to-parallel conversion circuits is used to convert the first sampled data into serial-to-parallel data, obtaining two intermediate data streams (e.g., denoted as d0_h<2:1>). Another first serial-to-parallel conversion circuit is used to convert the second sampled data into serial-to-parallel data, obtaining two intermediate data streams (e.g., denoted as d0_l<2:1>). For example, a second serial-to-parallel conversion circuit is used to convert the two intermediate data streams (e.g., denoted as d0_h<2:1>) into serial-to-parallel data, obtaining N streams of first target data (e.g., denoted as data_h). <n:1>(Represented by d0_l<2:1>). Another second serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on the two intermediate data (e.g., represented by d0_l<2:1>) to obtain N channels of second target data (e.g., represented by data_l). <n:1>express).

[0062] The first serial-to-parallel conversion circuit can be a 1:2 serial-to-parallel conversion circuit commonly found on the market, and the second serial-to-parallel conversion circuit can be a 2:N serial-to-parallel conversion circuit commonly found on the market.

[0063] In one optional implementation, the first serial-to-parallel conversion circuit includes: a first flip-flop and a second flip-flop. The first flip-flop is used to sample either first or second sampled data according to an input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining one intermediate data path from the two intermediate data paths. For example, one first flip-flop is used to sample the first sampled data according to an input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining one intermediate data path from the two intermediate data paths (such as d0_h). <1> (represented); another first flip-flop is used to sample the second sampled data according to the input clock signal, and keep the sampled data unchanged for a certain period of time, so as to obtain one intermediate data of the two intermediate data (such as using d0_l). <1> express).

[0064] The second flip-flop is used to sample either the first or second sampled data according to the input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining the other intermediate data from the two intermediate data streams. For example, one second flip-flop is used to sample the first sampled data according to the input clock signal, and keep the sampled data unchanged for a certain period of time, thereby obtaining the other intermediate data from the two intermediate data streams (such as using d0_h). <2> (represented); another second flip-flop is used to sample the second sampled data according to the input clock signal and keep the sampled data unchanged for a certain period of time, thereby obtaining the other intermediate data in the two intermediate data (such as using d0_l). <2> express).

[0065] The input data of the first flip-flop is the same as that of the second flip-flop, and the clock signal of the first flip-flop (e.g., represented by Rxclkp) is opposite to that of the clock signal of the second flip-flop (e.g., represented by Rxclkn).

[0066] The first and second flip-flops can be D flip-flops, or other flip-flops that perform the same clock sampling logic function as D flip-flops, such as level sampling flip-flops (latch).

[0067] In this implementation method, the circuit schematic of the chip is as follows: Figure 9 As shown. It should be noted that, in addition to the method shown in this application, the first serial-to-parallel conversion circuit can also sample a common 1:2 serial-to-parallel conversion circuit.

[0068] The decoder provided in the chip embodiment has the same implementation principle and the same technical effect as the decoder embodiment. For the sake of brevity, any parts not mentioned in the chip embodiment can be referred to the corresponding content in the aforementioned decoder embodiment.

[0069] Based on the same inventive concept, embodiments of this application also provide a high-speed serial transmission interface, such as... Figure 10 As shown. This high-speed serial transmission interface includes a data transmitter and a data receiver; the data receiver includes the aforementioned chip. This high-speed serial transmission interface can be used for data transmission between two chips. For example, by connecting the data transmitter of the high-speed serial transmission interface to one chip and the data receiver to the other chip, data transmission between the two chips can be achieved. It should be noted that... Figure 10 In the schematic diagram shown, the input signals of the decoder are four channels of first target data and four channels of second target data input in parallel.

[0070] The chip provided in the high-speed serial transmission interface embodiment has the same implementation principle and technical effect as the aforementioned chip embodiment. For the sake of brevity, any parts not mentioned in the high-speed serial transmission interface embodiment can be referred to the corresponding content in the aforementioned chip embodiment.

[0071] Based on the same inventive concept, this application also provides an electronic device. This electronic device includes a body and the aforementioned chip, or, as described above, a high-speed serial transmission interface. This electronic device can be a mobile phone, tablet, computer, or other electronic device.

[0072] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0073] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims. < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A decoder, characterized by This is used to decode N parallel input channels of first target data and N parallel input channels of second target data into parallel N-bit PRBS data output. The N channels of first target data are obtained by serial-to-parallel conversion of first sampled data, and the N channels of second target data are obtained by serial-to-parallel conversion of second sampled data. The first sampled data is obtained by sampling encoded data using a first sampling threshold, and the second sampled data is obtained by sampling the encoded data using a second sampling threshold. N is an even number greater than or equal to 4. The decoder includes: N-channel decoding circuits, each of which is used to obtain a corresponding PRBS data bit based on one data bit from the N-channel first target data, one data bit from the N-channel second target data, and a specified signal; A trigger, the data input terminal of which is connected to the last decoding circuit in the N-channel decoding circuit, and the output terminal of which is connected to the first decoding circuit in the N-channel decoding circuit; Where i takes values ​​from 1 to N in sequence, for the i-th decoding circuit in the N-way decoding circuit, when i=1, the specified signal is the data signal output by the flip-flop, and when i is greater than 1, the specified signal is the internal signal output by the (i-1)-th decoding circuit.

2. The decoder according to claim 1, characterized in that, The i-th decoding circuit includes: The selection unit is used to selectively output one data point from the N first target data points or one data point from the N second target data points according to the specified signal input to itself, thereby obtaining an internal signal; wherein, when i=1, the specified signal input to the selection unit in the i-th decoding circuit is the data signal output by the trigger, and when i is greater than 1, the specified signal input to the selection unit in the i-th decoding circuit is the output signal of the selection unit in the (i-1)-th decoding circuit. A sample-and-hold unit is connected to the output of the selection unit. The sample-and-hold unit is used to sample the output data of the selection unit and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one-bit PRBS data.

3. The decoder according to claim 2, characterized in that, The selection unit includes: A selector, wherein the first input terminal of the selector is used to receive one data from the N channels of first target data, and the second input terminal of the selector is used to receive one data from the N channels of second target data; the selector is used to selectively output one data from the N channels of first target data or one data from the N channels of second target data according to a specified input signal.

4. The decoder according to claim 2, characterized in that, The sample-and-hold unit includes a flip-flop, the data input terminal of which is connected to the output terminal of the selection unit. The flip-flop is used to sample the output data of the selection unit according to the input clock signal and keep the sampled data unchanged for a certain period of time, thereby obtaining the corresponding one bit of PRBS data.

5. A chip, characterized in that, Includes two serial-to-parallel converters and a decoder as described in any one of claims 1-4; A serial-to-parallel converter is used to perform serial-to-parallel conversion on the first sampled data to obtain N channels of first target data, wherein the first sampled data is data obtained by sampling the coded data with a first sampling threshold; Another serial-to-parallel converter is used to perform serial-to-parallel conversion on the second sampled data to obtain N channels of second target data, wherein the second sampled data is data obtained by sampling the encoded data with a second sampling threshold.

6. The chip according to claim 5, characterized in that, Each of the serial-to-parallel converters includes: The first serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on the first sampled data or the second sampled data to obtain two intermediate data streams. The second serial-to-parallel conversion circuit is used to perform serial-to-parallel conversion on the two intermediate data streams to obtain the N-channel first target data or the N-channel second target data.

7. The chip according to claim 6, characterized in that, The first serial-to-parallel conversion circuit includes: The first flip-flop is used to sample the first sampled data or the second sampled data according to the input clock signal, and keep the sampled data unchanged for a certain period of time, so as to obtain one intermediate data of the two intermediate data. The second flip-flop is used to sample the first sampled data or the second sampled data according to the input clock signal, and keep the sampled data unchanged for a certain period of time, so as to obtain another intermediate data among the two intermediate data; The input data of the first flip-flop is the same as the input data of the second flip-flop, and the clock signal of the first flip-flop is opposite to the clock signal of the second flip-flop.

8. A high-speed serial transmission interface, characterized in that, include: A data transmitting end and a data receiving end; the data receiving end includes the chip as described in any one of claims 5-7.

9. An electronic device, characterized in that, include: ontology; And the chip as described in any one of claims 5-7, or the high-speed serial transmission interface as described in claim 8.

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