Serial-to-parallel conversion circuit and MIPI C-PHY device

Abstract

The invention relates to a serial-to-parallel conversion circuit and MIPI C-PHY equipment, the serial-to-parallel conversion circuit comprises a first frequency division module, a second frequency division module and a serial-to-parallel conversion module, the first frequency division module is used for accessing a first clock signal, performing m-1 frequency division processing and m frequency division processing on the first clock signal and then outputting a second clock signal and a switching signal; the second frequency division module is used for accessing a first clock signal and performing n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; wherein n + 1 is equal to 2m, and n is a positive odd number; the serial-to-parallel conversion module is connected with the first frequency division module and the second frequency division module and is used for outputting the data signal as n paths of data under the control action of the access data signal, the first clock signal, the second clock signal, the switching signal and the synchronous clock signal; the transmission rate of the data signal is twice the frequency of the first clock signal.

Description

Technical Field

[0001] This application relates to the field of serial-to-parallel conversion technology, and particularly to a serial-to-parallel conversion circuit and a MIPI C-PHY device. Background Art

[0002] The existing serial-to-parallel conversion circuit architecture can only achieve the scenario where the data transmission rate is the same as the clock signal frequency, with low applicability. Summary of the Invention

[0003] Based on this, it is necessary to provide a serial-to-parallel conversion circuit and a MIPI C-PHY device for the above problems.

[0004] In a first aspect, this application provides a serial-to-parallel conversion circuit, including:

[0005] A first frequency division module, configured to access a first clock signal, and perform frequency division processing and m-frequency division processing on the first clock signal to output a second clock signal and a switching signal after m-1 frequency division processing and m frequency division processing;

[0006] A second frequency division module, configured to access the first clock signal, and perform n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; where n + 1 = 2m, and n is a positive odd number;

[0007] A serial-to-parallel conversion module, respectively connected to the first frequency division module and the second frequency division module, configured to access a data signal, and under the control of the first clock signal, the second clock signal, the switching signal, and the synchronous clock signal, output the data signal as n channels of data; the transmission rate of the data signal is twice the frequency of the first clock signal.

[0008] In one embodiment, the serial-to-parallel conversion module includes:

[0009] A serial-to-parallel conversion unit, connected to the first frequency division module, configured to access the first clock signal and the data signal, and under the control of the first clock signal, convert the data signal into n + 1 channels of parallel data, and under the control of the second clock signal, synchronously output the n + 1 channels of parallel data;

[0010] A multiplexing unit, connected to the first frequency division module and the serial-to-parallel conversion unit, configured to, under the control of the switching signal, select and output the n + 1 channels of parallel data as n channels of data;

[0011] A triggering unit, connected to the multiplexing unit and the second frequency division module, configured to, under the control of the synchronous clock signal, synchronously output the n channels of data.

[0012] In one embodiment, the n + 1 parallel data includes m parallel data of even columns and m parallel data of odd columns; the serial-to-parallel conversion unit includes:

[0013] A first sub-unit, respectively connected to the first frequency division module and the multiplexing unit, for accessing the data signal, and under the control of the first clock signal, converting the data signal into the m parallel data of even columns, and under the control of the second clock signal, synchronously outputting the m parallel data of even columns;

[0014] A first NOT gate, the input end of the first NOT gate is used for accessing the first clock signal;

[0015] A second sub-unit, respectively connected to the first frequency division module, the multiplexing unit and the output end of the first NOT gate, for converting the data signal into the m parallel data of odd columns under the control of the first clock signal processed by the first NOT gate, and synchronously outputting the m parallel data of odd columns under the control of the second clock signal.

[0016] In one embodiment, both the first sub-unit and the second sub-unit include m - stage trigger components, and each stage of trigger component outputs one path of parallel data;

[0017] Each stage of the trigger component includes a first flip - flop and a second flip - flop;

[0018] The data input end of the first flip - flop in the first - stage trigger component is used for accessing the data signal, the data input end of the first flip - flop in the subsequent stage of trigger component is connected to the output end of the first flip - flop in the previous stage of trigger component, and the clock signal input ends of each first flip - flop are used for accessing the first clock signal;

[0019] The clock signal input end of the second flip - flop is used for accessing the second clock signal, the data input end of the second flip - flop is connected to the output end of the first flip - flop in the same - stage trigger component, and the output end of the second flip - flop is used for outputting one path of parallel data.

[0020] In one embodiment, the n + 1 parallel data includes m parallel data of even columns and m parallel data of odd columns; the multiplexing unit includes:

[0021] m multiplexers, the trigger terminals of each of the multiplexers are connected to the first frequency division module and are used to operate under the control of the switching signal. Two input terminals of one multiplexer are respectively connected to a path of even-column parallel data and a path of odd-column parallel data. Two output terminals of m - 1 multiplexers among the m multiplexers and one output terminal of the remaining one multiplexer among the m multiplexers are respectively connected to the trigger unit to output n paths of data to the trigger unit.

[0022] In one embodiment, the trigger unit includes:

[0023] n third flip-flops, wherein data input terminals of every two of the n - 1 third flip-flops are connected to two output terminals of the same multiplexer among the m - 1 multiplexers, and a data input terminal of the remaining one third flip-flop among the n third flip-flops is connected to one output terminal of the remaining one multiplexer among the m multiplexers to respectively access the n paths of data;

[0024] The clock signal input terminals of each of the third flip-flops are all connected to the second frequency division module and are used to access the synchronous clock signal to synchronously output the n paths of data.

[0025] In one embodiment, m = 4; the first frequency division module includes:

[0026] A fourth flip-flop, the clock signal input terminal of the fourth flip-flop is used to access the first clock signal;

[0027] A fifth flip-flop, the clock signal input terminal of the fifth flip-flop is used to access the first clock signal, the data input terminal of the fifth flip-flop is connected to the output terminal of the fourth flip-flop, and the output terminal of the fifth flip-flop is connected to the serial-parallel conversion module and is used to output the second clock signal;

[0028] A sixth flip-flop, the clock signal input terminal of the sixth flip-flop is connected to the output terminal of the fourth flip-flop;

[0029] A seventh flip-flop, the clock signal input terminal of the seventh flip-flop is connected to the output terminal of the fifth flip-flop, the data input terminal of the seventh flip-flop is connected to the data input terminal of the sixth flip-flop, and the output terminal of the seventh flip-flop is connected to the serial-parallel conversion module and is used to output the switching signal;

[0030] A first NAND gate, the output terminal of the first NAND gate is connected to the data input terminal of the fourth flip-flop, and the first input terminal of the first NAND gate is connected to the output terminal of the fifth flip-flop;

[0031] A first OR gate, an output end of the first OR gate is connected to a second input end of the first NAND gate, a first input end of the first OR gate is connected to an output end of the fourth flip-flop, and a second input end of the first OR gate is connected to an output end of the sixth flip-flop;

[0032] A second NOT gate, an input end of the second NOT gate is connected to an output end of the sixth flip-flop, and an output end of the second NOT gate is connected to data input ends of the seventh flip-flop and the sixth flip-flop.

[0033] In one embodiment, the second frequency division module includes:

[0034] A first shift register unit, a plurality of clock signal input ends of the first shift register unit are all used for accessing the first clock signal;

[0035] A third NOT gate, an input end of the third NOT gate is used for accessing the first clock signal;

[0036] A second shift register unit, a plurality of clock signal input ends of the second shift register unit are all connected to an output end of the third NOT gate;

[0037] A second OR gate, two input ends of the second OR gate are respectively connected to output ends of the first shift register unit and the second shift register unit, and an output end of the second OR gate is connected to the serial-parallel conversion module for outputting the synchronous clock signal.

[0038] In one embodiment, both the first shift register unit and the second shift register unit include:

[0039] n-stage eighth flip-flops, a data input end of the first-stage eighth flip-flop is connected to an output end of the n-stage eighth flip-flop, and data input ends of the remaining stages of the eighth flip-flops are connected to output ends of the previous-stage eighth flip-flops; the remaining stages of the eighth flip-flops are the eighth flip-flops except the first-stage eighth flip-flop among the n-stage eighth flip-flops;

[0040] A fourth NOT gate, an input end of the fourth NOT gate is connected to clock signal input ends of each of the eighth flip-flops;

[0041] A ninth flip-flop, a clock signal input end of the ninth flip-flop is connected to an output end of the fourth NOT gate, and a data input end of the ninth flip-flop is connected to an output end of the (n-2)-stage eighth flip-flop;

[0042] A third OR gate, two input ends of the third OR gate are respectively connected to an output end of the first-stage eighth flip-flop and an output end of the ninth flip-flop, and an output end of the third OR gate is connected to the serial-parallel conversion module for outputting the synchronous clock signal;

[0043] Among them, the clock signal input ends of the n-stage eighth flip-flops in the first shift register unit are all used to access the first clock signal;

[0044] The clock signal input ends of the n-stage eighth flip-flops in the second shift register unit are all used to access the first clock signal processed by the third NOT gate;

[0045] The output ends of the third OR gates in the first shift register unit and the second shift register unit are respectively connected to the two input ends of the second OR gate in a corresponding manner.

[0046] In a second aspect, the present application further provides a MIPI C-PHY device, including the serial-to-parallel conversion circuit as described in the first aspect.

[0047] For the above serial-to-parallel conversion circuit and MIPI C-PHY device, since the transmission rate of the data signal is twice the frequency of the first clock signal, in the present application, the first clock signal is first divided by the first frequency division module to generate a second clock signal and a switching signal, and a synchronous clock signal with a fixed frequency is generated by the second frequency division module, so that the serial-to-parallel conversion module outputs the data signal as n-channel data under the control of the first clock signal, the second clock signal, the switching signal and the synchronous clock signal. Therefore, the present application can be applied to applications where the transmission rate of the data signal is twice the frequency of the first clock signal, and can convert one-channel serial data into n-channel parallel data for output, reducing the working speed of the serial data and providing a larger safe timing serial port. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a schematic structural diagram of a serial-to-parallel conversion circuit in an embodiment of the present application;

[0050] Figure 2 It is a timing diagram of the first clock signal, the second clock signal and the switching signal in an embodiment of the present application;

[0051] Figure 3 It is a schematic structural diagram of a serial-to-parallel conversion module in an embodiment of the present application;

[0052] Figure 4Schematic diagram of the mapping relationship where the serial-parallel conversion module in an embodiment of this application selects and outputs 8-way parallel data as 7-way data;

[0053] Figure 5 Schematic diagram of the structure of the serial-parallel conversion unit in an embodiment of this application;

[0054] Figure 6 Schematic diagram of the structures of the first sub-unit and the second sub-unit in the case of m = 4 in an embodiment of this application;

[0055] Figure 7 Schematic diagram of the structure of the multiplexer unit in an embodiment of this application;

[0056] Figure 8 Schematic diagram of the structure of the trigger unit in an embodiment of this application;

[0057] Figure 9 Schematic diagram of the structure of the first frequency division module in an embodiment of this application;

[0058] Figure 10 Schematic diagram of the structure of the second frequency division module in an embodiment of this application.

[0059] Explanation of the reference numerals in the drawings:

[0060] 110: First frequency division module 110; 111: First NAND gate; 112: First OR gate; 113: Second NOT gate; 120: Second frequency division module; 121: First shift register unit; 122: Third NOT gate; 123: Second shift register unit; 124: Second OR gate; 211: Fourth NOT gate; 212: Third OR gate; 130: Serial-parallel conversion module; 131: Serial-parallel conversion unit; 1311: First sub-unit; 1312: First NOT gate; 1313: Second sub-unit; 311: Trigger component; 132: Multiplexer unit; 1321: Multiplexer; 133: Trigger unit. Detailed implementation manners

[0061] To make the above objects, features, and advantages of this application more obvious and understandable, the following will describe the detailed implementation manners of this application with reference to the accompanying drawings. Many specific details are set forth in the following description to fully understand this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of this application. Therefore, this application is not limited by the specific embodiments disclosed below.

[0062] In the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0063] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0064] In the present application, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0065] In one embodiment, referring to the attached Figure 1 , the attached Figure 1 shows the structure of the serial-parallel conversion circuit in this embodiment. The serial-parallel conversion circuit in this embodiment includes a first frequency division module 110, a second frequency division module 120, and a serial-parallel conversion module 130.

[0066] The first frequency division module 110 is used to access the first clock signal ckin1, and perform frequency division processing and m-frequency division processing on the first clock signal ckin1 to output the second clock signal ckin2 and the switching signal Switch after (m - 1)-frequency division processing and m-frequency division processing. The second frequency division module 120 is used to access the first clock signal ckin1 and perform n / 2-frequency division processing on the first clock signal ckin1 to obtain a synchronous clock signal; where n + 1 = 2m and n is a positive odd number. The serial-to-parallel conversion module 130 is respectively connected to the first frequency division module 110 and the second frequency division module 120, and is used to access the data signal din. Under the control of the first clock signal ckin1, the second clock signal ckin2, the switching signal Switch, and the synchronous clock signal, the data signal din is output as n channels of data; the transmission rate of the data signal din is twice the frequency of the first clock signal ckin1.

[0067] Exemplarily, the frequency of the first clock signal ckin1 is 2D. After the first clock signal ckin1 is subjected to (m - 1)-frequency division processing and m-frequency division processing by the first frequency division module 110, the frequency of the output second clock signal ckin2 alternates between D / 2(m - 1) and D / 2m. The switching signal Switch is high when the frequency of the second clock signal ckin2 is D / 2(m - 1) and low when the frequency of the second clock signal ckin2 is D / 2m. The frequency of the synchronous clock signal output after the first clock signal ckin1 is subjected to n / 2-frequency division processing by the second frequency division module 120 is fixed at D / 2n. The serial-to-parallel conversion module 130 can first convert the data signal din into n + 1 channels of parallel data under the control of the first clock signal ckin1, then synchronize the n + 1 channels of parallel data through the rising edge of the second clock signal ckin2, and then convert the n + 1 channels of parallel data into n channels of data through the switching signal Switch, and finally synchronously output the n channels of data through the synchronous clock signal.

[0068] Exemplarily, as Figure 2 shown in the timing diagrams of the first clock signal ckin1, the second clock signal ckin2, and the switching signal Switch. If the frequency of the first clock signal ckin1 is 2D and n = 7, then m = 4. The first frequency division module 110 can perform 3-frequency division processing and 4-frequency division processing on the first clock signal ckin1 to generate a second clock signal ckin2 with an alternating frequency of D / 6 and D / 8. The switching signal Switch is high when the frequency of the second clock signal ckin2 is D / 6 and low when the frequency of the second clock signal ckin2 is D / 8. The frequency of the synchronous clock signal is fixed at D / 7, improving the duty cycle and being able to provide better timing for subsequent digital circuits. The serial-to-parallel conversion module 130 can output the data signal din as 7 channels of data, realizing 1-to-7 conversion.

[0069] In this embodiment, since the transmission rate of the data signal din is twice the frequency of the first clock signal ckin1, the first clock signal ckin1 is first divided by the first frequency division module 110 to generate a second clock signal ckin2 and a switching signal Switch. The second frequency division module 120 generates a synchronous clock signal with a fixed frequency, so that the serial-to-parallel conversion module 130 outputs the data signal din as n channels of data under the control of the first clock signal ckin1, the second clock signal ckin2, the switching signal Switch, and the synchronous clock signal. Therefore, the present application can be applied to the application where the transmission rate of the data signal din is twice the frequency of the first clock signal ckin1, and can convert one channel of serial data into n channels of parallel data for output, improving the duty cycle of the clock signal, reducing the working speed of the serial data, and providing a larger safe timing serial port.

[0070] In one embodiment, refer to the attached Figure 3 , attached Figure 3 shows the structure of the serial-to-parallel conversion module 130 in this embodiment. The serial-to-parallel conversion module 130 in this embodiment includes a serial-to-parallel conversion unit 131, a multiplexing unit 132, and a trigger unit 133. The serial-to-parallel conversion unit 131 is connected to the first frequency division module 110, and is used to access the first clock signal ckin1 and the data signal din. Under the control of the first clock signal ckin1, the data signal din is converted into n + 1 channels of parallel data, and under the control of the second clock signal ckin2, the n + 1 channels of parallel data are synchronously output; the multiplexing unit 132 is connected to the first frequency division module 110 and the serial-to-parallel conversion unit 131, and is used to select and output n + 1 channels of parallel data as n channels of data under the control of the switching signal Switch; the trigger unit 133 is connected to the multiplexing unit 132 and the second frequency division module 120, and is used to synchronously output n channels of data under the control of the synchronous clock signal.

[0071] Exemplarily, taking n = 7 and the frequency of the first clock signal ckin1 as 2D as an example, refer to the attached Figure 4 shows a schematic diagram of the mapping relationship of the serial-to-parallel conversion module 130 selecting and outputting 8 channels of parallel data as 7 channels of data. Among them, Q<0>~Q<7> refer to 8 channels of parallel data, div3 refers to the frequency of the second clock signal ckin2 being D / 6, and div4 refers to the frequency of the second clock signal ckin2 being D / 8.

[0072] In this embodiment, through the serial-parallel conversion unit 131, the multiplexing unit 132, and the triggering unit 133, it is possible to synchronously output a serial data signal din into n odd-numbered parallel data, significantly reducing the data frequency of the subsequent data decoder, reducing the operating speed of the data decoder, and providing a larger safety timing window.

[0073] In one embodiment, the n + 1 parallel data may include m parallel data of even columns and m parallel data of odd columns.

[0074] Refer to the appendix Figure 5 , appendix Figure 5 shows the structure of the serial-parallel conversion unit 131 in this embodiment. The serial-parallel conversion unit 131 in this embodiment includes a first sub-unit 1311, a first NOT gate 1312, and a second sub-unit 1313.

[0075] The first sub-unit 1311 is respectively connected to the first frequency division module 110 and the multiplexing unit 132, and is used to access the data signal din. Under the control of the first clock signal ckin1, the data signal din is converted into m parallel data of even columns, and under the control of the second clock signal ckin2, the m parallel data of even columns are synchronously output.

[0076] The input end of the first NOT gate 1312 is used to access the first clock signal ckin1.

[0077] The second sub-unit 1313 is respectively connected to the first frequency division module 110, the multiplexing unit 132, and the output end of the first NOT gate 1312, and is used to convert the data signal din into m parallel data of odd columns under the control of the first clock signal ckin1 processed by the first NOT gate 1312, and synchronously output the m parallel data of odd columns under the control of the second clock signal ckin2.

[0078] In this embodiment, under the action of the first clock signal ckin1, the first sub-unit 1311 converts the data signal din into m parallel data of even columns. The first NOT gate 1312 takes the inverse of the first clock signal ckin1. For example, if the first clock signal ckin1 is high, it becomes low after inversion; if the first clock signal ckin1 is high, it becomes low after inversion. The second sub-unit 1313 converts the data signal din into m parallel data of odd columns under the control of the signal obtained by taking the inverse of the first clock signal ckin1. Both the first sub-unit 1311 and the second sub-unit 1313 are connected to the second clock signal ckin2, and the first sub-unit 1311 and the second sub-unit 1313 synchronously output the m parallel data of even columns and the m parallel data of odd columns under the control of the second clock signal ckin2.

[0079] Exemplarily, if m = 4, the first sub-unit 1311 outputs parallel data of q<0>, q<2>, q<4>, q<6> paths, the second sub-unit 1313 outputs parallel data of q<1>, q<3>, q<5>, q<7> paths, and the serial-to-parallel conversion unit 131 outputs 8-path parallel data. m can also be other values, not limited to the above example.

[0080] In one embodiment, both the first sub-unit 1311 and the second sub-unit 1313 include m-level trigger components 311, and each level of trigger component 311 outputs one path of parallel data.

[0081] Each level of trigger component 311 includes a first flip-flop D1 and a second flip-flop D2.

[0082] The data input terminal of the first flip-flop D1 in the first-level trigger component 311 is used to access the data signal din. The data input terminal of the first flip-flop D1 in the subsequent level of trigger component 311 is connected to the output terminal of the first flip-flop D1 in the previous level of trigger component 311. The clock signal input terminals of each first flip-flop D1 are used to access the first clock signal ckin1.

[0083] The clock signal input terminal of the second flip-flop D2 is used to access the second clock signal ckin2. The data input terminal of the second flip-flop D2 is connected to the output terminal of the first flip-flop D1 in the same level of trigger component 311, and the output terminal of the second flip-flop D2 is used to output one path of parallel data.

[0084] Exemplarily, refer to the appendix Figure 6 , appendix Figure 6 shows a schematic structural diagram of the first sub-unit 1311 and the second sub-unit 1313 in the case of m = 4. Among them, the first sub-unit 1311 outputs parallel data of q<0>, q<2>, q<4>, q<6> paths, and the second sub-unit 1313 outputs parallel data of q<1>, q<3>, q<5>, q<7> paths. For the appendix to be more concise and clear, only the first-level trigger component 311 in the first sub-unit 1311 is labeled in the appendix Figure 6 . It can be understood that the structure of each level of trigger component 311 in this embodiment is the same. It can be understood that taking the appendix Figure 6 as an example, the first-level trigger component 311 of the first sub-unit 1311 is the trigger component 311 that outputs q<0> parallel data. The subsequent level of the first-level trigger component 311 is the trigger component 311 that outputs q<2> parallel data. The subsequent level of the trigger component 311 that outputs q<2> parallel data is the trigger component 311 that outputs q<4> parallel data. The last-level trigger component 311 is the trigger component 311 that outputs q<6> parallel data.

[0085] In this embodiment, both the first sub-unit 1311 and the second sub-unit 1313 include m-level trigger components 311. Each level of trigger component 311 outputs a column of parallel data. Therefore, the first sub-unit 1311 and the second sub-unit 1313 can output m columns of parallel data simultaneously, thereby realizing the conversion of a serial data signal din into 2m columns, that is, n + 1 columns of parallel data.

[0086] In one embodiment, the n + 1 paths of parallel data include m paths of first parallel data and m paths of second parallel data.

[0087] Refer to the appendix Figure 7 , appendix Figure 7 shows a schematic structural diagram of the multiplexing unit 132 in this embodiment. The multiplexing unit 132 in this embodiment includes m multiplexers 1321. The trigger terminals of the multiplexers 1321 are all connected to the first frequency division module 110 and are used to operate under the control of the switching signal Switch. Two input terminals in one multiplexer 1321 are respectively connected to one path of first parallel data and one path of second parallel data. Two output terminals of m - 1 multiplexers 1321 among the m multiplexers 1321 and one output terminal of the remaining one multiplexer 1321 among the m multiplexers 1321 are respectively connected to the trigger unit 133 to output n paths of data to the trigger unit 133.

[0088] Exemplarily, m = 4. Two output terminals of 3 out of the 4 multiplexers 1321 are both connected to the trigger unit 133, and one output terminal of 1 out of the 4 multiplexers 1321 is connected to the trigger unit 133.

[0089] In this embodiment, the m multiplexers 1321 can convert the n + 1 paths of parallel data into n paths of parallel data, and then under the action of the trigger unit 133, the n paths of parallel data are synchronously output.

[0090] In one embodiment, refer to the appendix Figure 8 , appendix Figure 8 shows a schematic structural diagram of the trigger unit 133 in this embodiment. The trigger unit 133 in this embodiment includes n third flip-flops D3. The data input terminals of every two of the n - 1 third flip-flops D3 are connected to two output terminals of the same multiplexer 1321 among the m - 1 multiplexers 1321, and the data input terminal of the remaining one third flip-flop D3 among the n third flip-flops D3 is connected to one output terminal of the remaining one multiplexer 1321 among the m multiplexers 1321 to respectively access n paths of data.

[0091] The clock signal input terminals of each third flip-flop D3 are all connected to the second frequency division module 120, and are used to access a synchronous clock signal to synchronously output n paths of data.

[0092] Exemplarily, m = 4, n = 7. The seven third flip-flops D3 are respectively the third flip-flop D3#1, the third flip-flop D3#2, the third flip-flop D3#3, the third flip-flop D3#4, the third flip-flop D3#5, the third flip-flop D3#6, and the third flip-flop D3#7. The four multiplexers 1321 are respectively the multiplexer 1321#1, the multiplexer 1321#2, the multiplexer 1321#3, and the multiplexer 1321#4. Among them, the two output terminals of the multiplexer 1321#1, the multiplexer 1321#2, and the multiplexer 1321#3 are connected to the trigger unit 133, and one output terminal of the multiplexer 1321#4 is connected to the trigger unit 133. Correspondingly, the two output terminals of the multiplexer 1321#1 are respectively connected to the data input terminals of the third flip-flop D3#1 and the third flip-flop D3#2. The two output terminals of the multiplexer 1321#2 are respectively connected to the data input terminals of the third flip-flop D3#3 and the third flip-flop D3#4. The two output terminals of the multiplexer 1321#3 are respectively connected to the data input terminals of the third flip-flop D3#5 and the third flip-flop D3#6. One output terminal of the multiplexer 1321#4 is connected to the data input terminal of the third flip-flop D3#7.

[0093] In this embodiment, through n third flip-flops D3, n paths of parallel data can be synchronously output under the action of the synchronous clock signal, improving the signal processing efficiency.

[0094] In one embodiment, refer to the appendix Figure 9 , appendix Figure 9 shows a schematic structural diagram of the first frequency division module 110 in this embodiment. m = 4. The first frequency division module 110 in this embodiment includes a fourth flip-flop D4, a fifth flip-flop D5, a sixth flip-flop D6, a seventh flip-flop D7, a first NAND gate 111, a first OR gate 112, and a second NOT gate 113.

[0095] The clock signal input terminal of the fourth flip-flop D4 is used to connect to the first clock signal ckin1. The clock signal input terminal of the fifth flip-flop D5 is used to connect to the first clock signal ckin1. The data input terminal of the fifth flip-flop D5 is connected to the output terminal of the fourth flip-flop D4. The output terminal of the fifth flip-flop D5 is connected to the serial-to-parallel conversion module 130 and is used to output the second clock signal ckin2. The clock signal input terminal of the sixth flip-flop D6 is connected to the output terminal of the fourth flip-flop D4. The clock signal input terminal of the seventh flip-flop D7 is connected to the output terminal of the fifth flip-flop D5. The data input terminal of the seventh flip-flop D7 is connected to the data input terminal of the sixth flip-flop D6. The output terminal of the seventh flip-flop D7 is connected to the serial-to-parallel conversion module 130 and is used to output the switching signal Switch. The output terminal of the first NAND gate 111 is connected to the data input terminal of the fourth flip-flop D4. The first input terminal of the first NAND gate 111 is connected to the output terminal of the fifth flip-flop D5. The output terminal of the first OR gate 112 is connected to the second input terminal of the first NAND gate 111. The first input terminal of the first OR gate 112 is connected to the output terminal of the fourth flip-flop D4. The second input terminal of the first OR gate 112 is connected to the output terminal of the sixth flip-flop D6. The input terminal of the second NOT gate 113 is connected to the output terminal of the sixth flip-flop D6. The output terminal of the second NOT gate 113 is connected to the data input terminals of the seventh flip-flop D7 and the sixth flip-flop D6.

[0096] In this embodiment, under the control of the first clock signal ckin1, the fourth flip-flop D4 and the fifth flip-flop D5, in combination with the first NAND gate 111 and the first OR gate 112, can perform a 3-frequency division process and a 4-frequency division process on the first clock signal ckin1 to generate the second clock signal ckin2. The second clock signal ckin2 is a signal with alternating frequencies of D / 6 and D / 8 (taking the frequency of the first clock signal as 2D). At the same time, based on the sixth flip-flop D6, the seventh flip-flop D7, and the third NOT gate 122, the switching signal Switch can be output. The switching signal Switch is high when the frequency of the second clock signal ckin2 is D / 6 and low when the frequency of the second clock signal ckin2 is D / 8. Based on this, the serial-to-parallel conversion circuit can convert 1-channel serial data signal din into 7-channel parallel data, effectively reducing the working speed of the subsequent data decoder.

[0097] In one embodiment, the second frequency division module 120 includes a first shift register unit 121, a third NOT gate 122, a second shift register unit 123, and a second OR gate 124.

[0098] The multiple clock signal input terminals of the first shift register unit 121 are all used to receive the first clock signal ckin1. The input terminal of the third NOT gate 122 is used to receive the first clock signal ckin1. The multiple clock signal input terminals of the second shift register unit 123 are all connected to the output terminal of the third NOT gate 122. The two input terminals of the second OR gate 124 are respectively connected to the output terminals of the first shift register unit 121 and the second shift register unit 123, and the output terminal of the second OR gate 124 is connected to the serial-parallel conversion module 130 for outputting a synchronous clock signal.

[0099] Exemplarily, n = 7, m = 4, refer to the appendix Figure 10 , appendix Figure 10 shows the structural schematic diagram of the second frequency division module 120 in this embodiment.

[0100] In this embodiment, through the first shift register unit 121, the third NOT gate 122, the second shift register unit 123, and the second OR gate 124, it is possible to realize non-integer multiple frequency division of the first clock signal ckin1 by using a shift register unit and a logic circuit, so as to provide a synchronous clock signal with a frequency fixed at 1 / 2n of the frequency of the first clock signal ckin1. Exemplarily, the frequency of the first clock signal ckin1 is 2D, n = 7, then the frequency of the synchronous clock signal is fixed at D / 7. Therefore, the second frequency division module 120 in the embodiment can improve the duty cycle of the clock signal and provide better timing for the subsequent digital circuit.

[0101] In one embodiment, both the first shift register unit 121 and the second shift register unit 123 include: n-stage eighth flip-flops D8, a fourth NOT gate 211, a ninth flip-flop D9, and a third OR gate 212.

[0102] The data input terminal of the first-stage eighth flip-flop D8 is connected to the output terminal of the n-stage eighth flip-flop D8, and the data input terminals of the remaining-stage eighth flip-flops D8 are connected to the output terminals of the previous-stage eighth flip-flops D8; the remaining-stage eighth flip-flops D8 are the eighth flip-flops D8 other than the first-stage eighth flip-flop D8 in the n-stage eighth flip-flops D8.

[0103] The input terminal of the fourth NOT gate 211 is connected to the clock signal input terminals of each eighth flip-flop D8.

[0104] The clock signal input terminal of the ninth flip-flop D9 is connected to the output terminal of the fourth NOT gate 211, and the data input terminal of the ninth flip-flop D9 is connected to the output terminal of the (n - 2)-stage eighth flip-flop D8.

[0105] The two input terminals of the third OR gate 212 are respectively connected to the output terminal of the first-stage eighth flip-flop D8 and the output terminal of the ninth flip-flop D9.

[0106] Among them, the clock signal input ends of the n-stage eighth flip-flop D8 in the first shift register unit 121 are all used to connect to the first clock signal ckin1.

[0107] The clock signal input ends of the n-stage eighth flip-flop D8 in the second shift register unit 123 are all used to connect to the first clock signal ckin1 processed by the third NOT gate 122.

[0108] The output ends of the third OR gate 212 in the first shift register unit 121 and the second shift register unit 123 are respectively and correspondingly connected to the two input ends of the second OR gate 124.

[0109] Exemplarily, continue to refer to the appendix Figure 10 appendix Figure 10 Taking n = 7 as an example, the structures of the first shift register unit 121 and the second shift register unit 123 are shown. The 7-stage eighth flip-flops D8 are respectively the eighth flip-flop D8#1, the eighth flip-flop D8#2, the eighth flip-flop D8#3, the eighth flip-flop D8#4, the eighth flip-flop D8#5, the eighth flip-flop D8#6, and the eighth flip-flop D8#7. Among them, the first-stage eighth flip-flop can be the eighth flip-flop D8#1, the nth-stage eighth flip-flop D8 can be the eighth flip-flop D8#7, and the remaining-stage eighth flip-flops D8 can include the eighth flip-flop D8#2, the eighth flip-flop D8#3, the eighth flip-flop D8#4, the eighth flip-flop D8#5, and the eighth flip-flop D8#6. The (n - 2)th-stage eighth flip-flop can be the eighth flip-flop D8#5. When n = 7, the duty cycles of the signals output from the output end of the third OR gate 212 in the first shift register unit 121 and the output of the third OR gate 212 in the second shift register unit 123 are both 3.5 frequency divisions of 2 / 7. After the OR operation by the second OR gate 124, a 3.5 frequency division with a duty cycle of 3 / 7 can be achieved, improving the duty cycle to provide better timing for subsequent digital circuits.

[0110] It can be understood that in other examples, n can also be other odd numbers, not limited to the above examples, and the numbers of the eighth flip-flops D8 at each stage can also be correspondingly modified.

[0111] In one embodiment, the present application further provides a MIPI C-PHY device (Mobile Industry Processor Interface Camera Physical Layer device), including the serial-parallel conversion circuit in any of the above embodiments.

[0112] Among them, MIPI refers to Mobile Industry Processor Interface, which is an open standard and specification developed for mobile application processors, aiming to promote interoperability among different hardware components in mobile phones and mobile devices. MIPI includes a complete set of interface specifications, covering the connection methods of various internal components in mobile devices such as cameras, displays, and memories. C-PHY is a physical layer interface specification introduced by the MIPI Alliance, mainly used for high-speed data transmission between components such as cameras and displays in mobile devices and application processors.

[0113] The MIPI C-PHY device in this embodiment can be understood as a hardware component adopting the MIPI C-PHY interface specification, such as a camera or a display, etc., which includes the serial-parallel conversion circuit in any of the above embodiments and has the corresponding technical effects of the serial-parallel conversion circuit in any of the above embodiments.

[0114] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0115] The above-described embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A serial-to-parallel conversion circuit, characterized in that: include: A first frequency division module, used for receiving a first clock signal, and performing m-1 frequency division processing and m frequency division processing on the first clock signal, so as to output a second clock signal and a switching signal after the m-1 frequency division processing and the m frequency division processing; A second frequency division module, used for receiving the first clock signal and performing n / 2 frequency division processing on the first clock signal to obtain a synchronous clock signal; wherein n+1=2m, and n is a positive odd number; The serial-to-parallel conversion module is respectively connected to the first frequency division module and the second frequency division module, and is used to access the data signal. Under the control of the first clock signal, the second clock signal, the switching signal and the synchronization clock signal, the data signal is output as n-channel data; the transmission rate of the data signal is twice the frequency of the first clock signal.

2. The serial-to-parallel conversion circuit according to claim 1, characterized in that: The serial-to-parallel conversion module comprises: a serial-to-parallel conversion unit, connected to the first frequency division module, and configured to receive the first clock signal and the data signal, convert the data signal into n+1 parallel data under the control of the first clock signal, and synchronously output the n+1 parallel data under the control of the second clock signal; a multi-channel selection unit connected to the first frequency division module and the serial-to-parallel conversion unit, and configured to select and output the n+1 channels of parallel data as n channels of data under the control of the switching signal; A trigger unit is connected to the multi-channel selection unit and the second frequency division module, and is used to synchronously output the n channels of data under the control of the synchronous clock signal.

3. The serial-to-parallel conversion circuit according to claim 2, characterized in that: The n+1 parallel data include m even-numbered parallel data and m odd-numbered parallel data. The serial-to-parallel conversion unit comprises: A first subunit is connected to the first frequency division module and the multi-channel selection unit respectively, and is used to receive the data signal, convert the data signal into the m-channel even-numbered column parallel data under the control of the first clock signal, and synchronously output the m-channel even-numbered column parallel data under the control of the second clock signal; A first NOT gate, wherein an input end of the first NOT gate is used to receive the first clock signal; The second subunit is respectively connected to the output ends of the first frequency division module, the multi-way selection unit and the first NOT gate, and is used to convert the data signal into the m-way odd-numbered column parallel data under the control of the first clock signal processed by the first NOT gate, and synchronously output the m-way odd-numbered column parallel data under the control of the second clock signal.

4. The serial-to-parallel conversion circuit according to claim 3, characterized in that: The first subunit and the second subunit each include m-level trigger components, and each level of trigger components outputs one channel of parallel data; Each level of the trigger assembly includes a first trigger and a second trigger; The data input terminal of the first trigger in the first-stage trigger component is used to access the data signal, the data input terminal of the first trigger in the next-stage trigger component is connected to the output terminal of the first trigger in the previous-stage trigger component, and the clock signal input terminal of each of the first triggers is used to access the first clock signal; The clock signal input terminal of the second trigger is used to receive the second clock signal, the data input terminal of the second trigger is connected to the output terminal of the first trigger in the same level trigger component, and the output terminal of the second trigger is used to output one parallel data.

5. The serial-to-parallel conversion circuit according to claim 2, characterized in that: The n+1 parallel data include m even-numbered parallel data and m odd-numbered parallel data. The multi-way selection unit comprises: There are m multiplexers, and the trigger end of each of the multiplexers is connected to the first frequency division module, and is used to work under the control of the switching signal. The two input ends of one of the multiplexers are respectively connected to one channel of even-numbered column parallel data and one channel of odd-numbered column parallel data, and the two output ends of m-1 multiplexers among the m multiplexers and one output end of the remaining one of the m multiplexers are respectively connected to the trigger unit to output n channels of data to the trigger unit.

6. The serial-to-parallel conversion circuit according to claim 5, characterized in that: The trigger unit comprises: n third flip-flops, wherein data input terminals of every two third flip-flops in the n-1 third flip-flops are connected to two output terminals of the same multiplexer in the m-1 multiplexers, and a data input terminal of the remaining third flip-flop in the n third flip-flops is connected to an output terminal of the remaining one of the m multiplexers, so as to access the n-way data respectively; The clock signal input end of each of the third triggers is connected to the second frequency division module for receiving the synchronous clock signal to synchronously output the n channels of data.

7. The serial-to-parallel conversion circuit according to claim 1, characterized in that: m=4； The first frequency division module includes: a fourth trigger, wherein a clock signal input terminal of the fourth trigger is used to receive the first clock signal; a fifth trigger, wherein a clock signal input terminal of the fifth trigger is used to receive the first clock signal, a data input terminal of the fifth trigger is connected to an output terminal of the fourth trigger, and an output terminal of the fifth trigger is connected to the serial-to-parallel conversion module for outputting the second clock signal; a sixth flip-flop, wherein a clock signal input terminal of the sixth flip-flop is connected to an output terminal of the fourth flip-flop; a seventh trigger, wherein a clock signal input terminal of the seventh trigger is connected to an output terminal of the fifth trigger, a data input terminal of the seventh trigger is connected to a data input terminal of the sixth trigger, and an output terminal of the seventh trigger is connected to the serial-to-parallel conversion module, for outputting the switching signal; A first NAND gate, wherein an output terminal of the first NAND gate is connected to a data input terminal of the fourth flip-flop, and a first input terminal of the first NAND gate is connected to an output terminal of the fifth flip-flop; a first OR gate, wherein the output terminal of the first OR gate is connected to the second input terminal of the first NAND gate, the first input terminal of the first OR gate is connected to the output terminal of the fourth trigger, and the second input terminal of the first OR gate is connected to the output terminal of the sixth trigger; A second NOT gate, wherein an input terminal of the second NOT gate is connected to an output terminal of the sixth flip-flop, and an output terminal of the second NOT gate is connected to data input terminals of the seventh flip-flop and the sixth flip-flop.

8. The serial-to-parallel conversion circuit according to claim 1, characterized in that: The second frequency division module includes: A first shift register unit, wherein a plurality of clock signal input terminals of the first shift register unit are all used to receive the first clock signal; a third NOT gate, wherein an input end of the third NOT gate is used to receive the first clock signal; a second shift register unit, wherein a plurality of clock signal input terminals of the second shift register unit are all connected to the output terminal of the third NOT gate; A second OR gate, wherein two input ends of the second OR gate are respectively connected to the output ends of the first shift register unit and the second shift register unit, and an output end of the second OR gate is connected to the serial-to-parallel conversion module, for outputting the synchronous clock signal.

9. The serial-to-parallel conversion circuit according to claim 8, characterized in that: The first shift register unit and the second shift register unit both include: n-stage eighth flip-flops, the data input terminal of the first-stage eighth flip-flop is connected to the output terminal of the n-stage eighth flip-flop, and the data input terminals of the remaining stages of the eighth flip-flop are connected to the output terminals of the previous stage of the eighth flip-flop; the remaining stages of the eighth flip-flops are the eighth flip-flops in the n-stage eighth flip-flops except the first-stage eighth flip-flop; a fourth NOT gate, wherein an input terminal of the fourth NOT gate is connected to a clock signal input terminal of each of the eighth flip-flops; a ninth flip-flop, wherein a clock signal input terminal of the ninth flip-flop is connected to an output terminal of the fourth NOT gate, and a data input terminal of the ninth flip-flop is connected to an output terminal of the eighth flip-flop of the n-2th stage; a third OR gate, wherein two input ends of the third OR gate are respectively connected to the output end of the eighth trigger and the output end of the ninth trigger of the first stage, and the output end of the third OR gate is connected to the serial-to-parallel conversion module for outputting the synchronous clock signal; Wherein, the clock signal input terminals of the n-stage eighth flip-flops in the first shift register unit are all used to access the first clock signal; The clock signal input terminals of the n-stage eighth flip-flops in the second shift register unit are all used to receive the first clock signal processed by the third NOT gate; The output ends of the third OR gate in the first shift register unit and the second shift register unit are respectively connected to the two input ends of the second OR gate.

10. A MIPI C-PHY device, characterized in that: The invention comprises a serial-to-parallel conversion circuit as claimed in any one of claims 1 to 9.

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