CIS Deep Trench Isolation Structure and Manufacturing Method

Abstract

This invention discloses a deep trench isolation structure for a CIS (CMOS Image Sensor), comprising: a deep trench formed by plasma etching of a first surface of a first semiconductor substrate, wherein the inner surface of the deep trench has interface defects generated by plasma etching; a first semiconductor epitaxial layer, a second dielectric layer, and a third conductive material layer formed in the deep trench; and a fourth conductive material layer formed in a portion of the deep trench closest to the peripheral region; the fourth conductive material layer being connected to an external electrode; the external electrode being connected to an external control module, which provides an external voltage to each of the third conductive material layers to modulate the interface states of the inner surface of the deep trench, thereby eliminating the adverse effects of interface defects on the interface states. This invention also discloses a method for manufacturing the deep trench isolation structure for a CIS. This invention can modulate the interface states at the interface between the deep trench isolation structure and the semiconductor substrate, optimizing the interface states and thereby reducing dark current and white pixels.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a deep trench isolation (DTI) structure for a CMOS Image Sensor (CIS); this invention also relates to a method for manufacturing a deep trench isolation structure for CIS. Background Technology

[0002] In back-side illumination (BSI) CIS, deep trench isolation structures play an important role in improving crosstalk between adjacent pixels. However, during the deep trench etching (ET) process of DTI, plasma generates many defects on the surface of the deep trench. These defects become photoelectron trapping centers, generating dark currents and white pixels, thus affecting image quality.

[0003] The existing improved technical solutions mainly include:

[0004] 1. Thinning followed by ion implantation annealing;

[0005] 2. Introduce a high-k dielectric film to suppress dark current and white pixels by relying on the field effect.

[0006] The products based on the above technical solutions have all been mass-produced. Product performance depends on process conditions and cannot be adjusted after preparation. Furthermore, quality differences caused by process fluctuations cannot be compensated for. Summary of the Invention

[0007] The technical problem to be solved by this invention is to provide a deep trench isolation structure for CIS (CMOS Image Sensor), which can regulate the interface states at the interface between the deep trench isolation structure and the semiconductor substrate, thereby optimizing the interface states and reducing dark current and white pixels. To this end, this invention also provides a method for manufacturing the deep trench isolation structure for CIS.

[0008] To solve the above-mentioned technical problems, the deep trench isolation structure of CIS provided by the present invention includes a pixel region and a peripheral region on the first semiconductor substrate; the peripheral region surrounds the periphery of the pixel region.

[0009] Deep trench isolation structures are formed in the pixel region, and the area between each deep trench isolation structure constitutes the forming area of ​​a pixel unit; the deep trench isolation structure includes:

[0010] Deep trenches are formed in the first semiconductor substrate by plasma etching of the first surface of the first semiconductor substrate. The top surface of the deep trenches is flush with the first surface of the first semiconductor substrate, and the inner surface of the deep trenches has interface defects generated by the plasma etching. The deep trenches are interconnected.

[0011] A first semiconductor epitaxial layer is formed on the inner surface of the deep trench.

[0012] A second dielectric layer is formed on the surface of the first semiconductor epitaxial layer in the deep trench.

[0013] The third conductive material layer completely fills the deep trench, and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer.

[0014] A fourth conductive material layer is also formed in a portion of the deep trench closest to the peripheral region. The fourth conductive material layer is formed on the top surface of the third conductive material layer and extends to the first surface of the first semiconductor substrate outside the deep trench. A fifth dielectric layer is spaced between the fourth conductive material layer and the first surface of the first semiconductor substrate outside the deep trench.

[0015] The fourth conductive material layer is connected to the external electrode.

[0016] The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers to modulate the interface state of the inner surface of the deep trench, thereby eliminating the adverse effects of the interface defects on the interface state.

[0017] A further improvement is that the first semiconductor substrate comprises a silicon substrate.

[0018] The first semiconductor epitaxial layer includes a silicon epitaxial layer.

[0019] A further improvement is that the material of the second dielectric layer includes a high dielectric constant layer.

[0020] A further improvement is that the fourth conductive material layer is formed by extending the third conductive material layer, and the fifth dielectric layer is formed by stacking the first semiconductor epitaxial layer and the second dielectric layer extending outside the deep trench.

[0021] A further improvement is that the CIS is a back-illuminated CIS, where the first surface of the first semiconductor substrate is the back side and the second surface of the first semiconductor substrate is the front side.

[0022] A further improvement is that the CIS is a stacked CIS.

[0023] The second surface of the first semiconductor substrate is bonded to the front side of the second semiconductor substrate.

[0024] A logic circuit is formed on the second semiconductor substrate.

[0025] A through-silicon via (TSV) passes from the back side of the first semiconductor substrate through the front side of the first semiconductor substrate and enters the second semiconductor substrate. The front metal layers of the first semiconductor substrate and the front metal layers of the second semiconductor substrate are connected through the TSV.

[0026] A back dielectric layer and a back gate mesh layer are also formed on the back side of the first semiconductor substrate. The back gate mesh layer is formed by patterning back metal. The through-silicon via is connected to the metal of the back gate mesh layer corresponding to the top, and the fourth conductive material layer is connected to the metal of the back gate mesh layer corresponding to the top.

[0027] The back dielectric layer is spaced between the metal of the third conductive material layer and the back grid layer in each of the deep trenches outside the formation area of ​​the fourth conductive material layer.

[0028] A further improvement is that the aspect ratio of the deep trench is 1 to 50.

[0029] To solve the above-mentioned technical problems, the manufacturing method of the deep trench isolation structure of CIS provided by the present invention includes the following steps:

[0030] Step 1: Provide a first semiconductor substrate, the first semiconductor substrate including a pixel region and a peripheral region; the peripheral region surrounds the periphery of the pixel region.

[0031] Photolithography defines the formation area of ​​deep trenches, and plasma etching is performed on the first surface of the first semiconductor substrate to form a plurality of deep trenches in the first semiconductor substrate; the deep trenches are located in the pixel area, and the area between each deep trench is the formation area of ​​a pixel unit; each deep trench is interconnected.

[0032] Step 2: Perform an epitaxial growth process to create a first semiconductor epitaxial layer on the inner surface of the deep trench.

[0033] Step 3: Form a second dielectric layer on the surface of the first semiconductor epitaxial layer.

[0034] Step 4: Form a third conductive material layer; the third conductive material layer completely fills the deep trench, and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer.

[0035] Step 5: Form a fifth dielectric layer and a fourth conductive material layer. The fourth conductive material layer is located in a portion of the deep trench closest to the peripheral region. The fourth conductive material layer is formed on the top surface of the third conductive material layer and extends to the first surface of the first semiconductor substrate outside the deep trench. The fifth dielectric layer is spaced between the fourth conductive material layer and the first surface of the first semiconductor substrate outside the deep trench.

[0036] The fourth conductive material layer is used to connect with the external electrode.

[0037] The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers to modulate the interface state of the inner surface of the deep trench, thereby eliminating the adverse effects of the interface defects on the interface state.

[0038] A further improvement is that the first semiconductor substrate comprises a silicon substrate.

[0039] The first semiconductor epitaxial layer includes a silicon epitaxial layer.

[0040] A further improvement is that the material of the second dielectric layer includes a high dielectric constant layer.

[0041] A further improvement is that, in step two, the first semiconductor epitaxial layer extends to the first surface of the first semiconductor substrate outside the deep trench.

[0042] In step five, the fifth dielectric layer is formed by the superposition of the first semiconductor epitaxial layer and the second dielectric layer extending out of the deep trench.

[0043] The fourth conductive material layer is an extension of the third conductive material layer, and step five is integrated into step four. Step four includes the following sub-steps:

[0044] A third conductive material layer is formed, which completely fills the deep trench and extends to the surface of the second dielectric layer outside the deep trench.

[0045] After photolithography defines the formation area of ​​the fourth conductive material layer, the third conductive material layer is etched. After etching, outside the formation area of ​​the fourth conductive material layer, the third conductive material layer completely fills the deep trench, and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer. In the formation area of ​​the fourth conductive material layer, the retained third conductive material layer completely fills the deep trench and forms the fourth conductive material layer.

[0046] A further improvement is that the CIS is a back-illuminated CIS, where the first surface of the first semiconductor substrate is the back side and the second surface of the first semiconductor substrate is the front side.

[0047] A further improvement is that the CIS is a stacked CIS; step five also includes:

[0048] The second surface of the first semiconductor substrate and the front surface of the second semiconductor substrate are bonded together using a bonding process; logic circuits are formed on the second semiconductor substrate.

[0049] A through-silicon via (TSV) is formed, which passes through the front side of the first semiconductor substrate from the back side of the first semiconductor substrate and enters the second semiconductor substrate. The front metal layer of the first semiconductor substrate and the front metal layer of the second semiconductor substrate are connected through the TSV.

[0050] A back dielectric layer and a back gate mesh layer are also formed on the back side of the first semiconductor substrate. The back gate mesh layer is formed by patterning back metal. The through-silicon vias are connected to the metal of the back gate mesh layer corresponding to the top. The fourth conductive material layer is connected to the metal of the back gate mesh layer corresponding to the top. The back dielectric layer is spaced between the metal of the third conductive material layer and the back gate mesh layer in each of the deep trenches outside the formation area of ​​the fourth conductive material layer.

[0051] A further improvement is that the bonding process includes hybrid bonding.

[0052] A further improvement is that the aspect ratio of the deep trench is 1 to 50.

[0053] This invention features a specially designed filling structure for the deep trench isolation structure. The filling structure is configured as a superposition of a first semiconductor epitaxial layer, a second dielectric layer, and a third conductive material layer. In this way, when a voltage is applied to the third conductive material layer, the interface state formed by interface defects on the inner surface of the deep trench can be controlled. This control is performed after the device is formed, which can eliminate the influence of process fluctuations on the interface state of the device during the device formation process. Therefore, this invention can control the interface state at the interface between the deep trench isolation structure and the semiconductor substrate, thereby optimizing the interface state and reducing dark current and white pixels.

[0054] Furthermore, since all the deep trenches of the present invention are interconnected, all the third conductive material layers are also electrically connected to each other. The present invention can form a fourth conductive material layer on top of the third conductive material layer in a portion of the deep trench closest to the outer periphery and connect it to the external electrode through the fourth conductive material layer. Therefore, the electrode lead-out structure of the deep trench isolation structure of the present invention will not adversely affect the performance of the pixel area.

[0055] The deep trench isolation structure of the present invention is particularly suitable for BSI CIS and stack CIS formed on the basis of BSI CIS. The electrode lead-out structure at the top of the fourth conductive material layer of the deep trench isolation structure of the present invention can be realized through the metal of the back gate mesh layer. The electrode lead-out structure of the deep trench isolation structure of the present invention is easy to implement and does not bring additional process costs. Attached Figure Description

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0057] Figure 1 This is a schematic diagram of the overall structure of the deep trench isolation structure of the CIS according to an embodiment of the present invention;

[0058] Figure 2A yes Figure 1 An enlarged view of a deep trench isolation structure in which a fourth conductive material layer is located closest to the outermost area;

[0059] Figure 2B yes Figure 1 An enlarged view of the deep trench isolation structure without a fourth conductive material layer. Detailed Implementation

[0060] like Figure 1 The diagram shown is an overall structural schematic of the deep trench isolation structure of the CIS according to an embodiment of the present invention. Figure 2A yes Figure 1 An enlarged view of the deep trench isolation structure in which a fourth conductive material layer 105a is set in the outermost region;

[0061] Figure 2B yes Figure 1 The image shows an enlarged view of a deep trench isolation structure without a fourth conductive material layer 105a. In the deep trench isolation structure of the CIS of this embodiment, the first semiconductor substrate 101 includes a pixel region and a peripheral region; the peripheral region surrounds the periphery of the pixel region. Figure 1 The area to the left of the dashed line AA is the outer perimeter area, and the area to the right is the pixel area.

[0062] Deep trench isolation structures are formed in the pixel region, and the area between each deep trench isolation structure constitutes the forming area of ​​a pixel unit; the deep trench isolation structure includes:

[0063] Deep trenches 102 are formed in the first semiconductor substrate 101 by plasma etching of the first surface of the first semiconductor substrate 101. The top surface of the deep trenches 102 is flush with the first surface of the first semiconductor substrate 101, and the inner surface of the deep trenches 102 has interface defects generated by the plasma etching. Each of the deep trenches 102 is interconnected.

[0064] In this embodiment of the invention, the aspect ratio of the deep trench 102 is 1 to 50.

[0065] A first semiconductor epitaxial layer 103 is formed on the inner surface of the deep trench 102.

[0066] In this embodiment of the invention, the first semiconductor substrate 101 includes a silicon substrate.

[0067] The first semiconductor epitaxial layer 103 includes a silicon epitaxial layer.

[0068] A second dielectric layer 104 is formed on the surface of the first semiconductor epitaxial layer 103 in the deep trench 102.

[0069] In this embodiment of the invention, the material of the second dielectric layer 104 includes a high dielectric constant layer.

[0070] The third conductive material layer 105 completely fills the deep trench 102, and the top surface of each third conductive material layer 105 is flush with the top surface of the third conductive material layer 105.

[0071] A fourth conductive material layer 105a is also formed in a portion of the deep trench 102 closest to the peripheral region. The fourth conductive material layer 105a is formed on the top surface of the third conductive material layer 105 and extends to the first surface of the first semiconductor substrate 101 outside the deep trench 102. A fifth dielectric layer is spaced between the fourth conductive material layer 105a and the first surface of the first semiconductor substrate 101 outside the deep trench 102.

[0072] In this embodiment of the invention, the fourth conductive material layer 105a is extended from the third conductive material layer 105.

[0073] The first semiconductor epitaxial layer 103 and the second dielectric layer 104 further extend to the outside of the deep trench 102. The fifth dielectric layer is formed by the superposition of the first semiconductor epitaxial layer 103 and the second dielectric layer 104 extending to the outside of the deep trench 102.

[0074] The fourth conductive material layer 105a is connected to the external electrode.

[0075] The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers 105 to modulate the interface state of the inner surface of the deep trench 102, thereby eliminating the adverse effects of the interface defects on the interface state.

[0076] In this embodiment of the invention, the CIS is a back-illuminated CIS, the first surface of the first semiconductor substrate 101 is the back surface, and the second surface of the first semiconductor substrate 101 is the front surface.

[0077] In this embodiment of the invention, the CIS is a stacked CIS, based on the back-illuminated CIS. Figure 1 The structure of the stacked CIS is shown.

[0078] The second surface of the first semiconductor substrate 101 is bonded to the front side of the second semiconductor substrate 201. Figure 1 In the first semiconductor substrate 101, a bonding layer 203 is formed on the second surface, and a bonding layer 202 is formed on the front side of the second semiconductor substrate 201. The bonding between the first semiconductor substrate 101 and the second semiconductor substrate 201 is achieved through the bonding layers 202 and 203.

[0079] Logic circuits are formed on the second semiconductor substrate 201. The difference between a back-illuminated CIS and a stacked CIS is that the logic circuits in a back-illuminated CIS are also formed on the first semiconductor substrate 101. In a stacked CIS, the logic circuits are formed separately on the second semiconductor substrate 201.

[0080] A through-silicon via 204 extends from the back side of the first semiconductor substrate 101 through the front side of the first semiconductor substrate 101 and into the second semiconductor substrate 201. The front metal layer (not shown) of the first semiconductor substrate 101 and the front metal layer (not shown) of the second semiconductor substrate 201 are connected through the through-silicon via 204.

[0081] A back dielectric layer 106 and a back gate mesh layer 107 are also formed on the back side of the first semiconductor substrate 101. The back gate mesh layer 107 is formed by back metal patterning. The through silicon via 204 is connected to the back gate mesh layer 107 at the top, and the fourth conductive material layer 105a is connected to the back gate mesh layer 107 at the top. Figure 1 In this context, the metal of the back gate mesh layer 107 corresponding to the top of the fourth conductive material layer 105a is separately marked as 107a, and the metal of the back gate mesh layer 107 corresponding to the top of the deep trench 102 in the pixel area where the fourth conductive material layer 105a is not provided is separately marked as 107b.

[0082] The back dielectric layer 106 is spaced between the metal of the third conductive material layer 105 and the back grid layer 107 in each of the deep trenches 102 outside the formation area of ​​the fourth conductive material layer 105a.

[0083] Figure 1 The image also shows a dielectric layer 108 formed on top of the back grid layer 107.

[0084] Typically, the metals 107a and 107b of the back grid layer 107 in the pixel area serve as reflective grids, i.e., reflective strips. The metals 107a and 107b are disposed on the top of the corresponding deep trench isolation structure, i.e., they are disposed around the photosensitive unit, i.e., the pixel unit. In other words, the area enclosed by the reflective strips corresponds to the area of ​​the photosensitive unit, so that the area around the photosensitive unit corresponds to the reflective strips. This can prevent crosstalk between adjacent photosensitive units.

[0085] In the peripheral region, the metal of the back gate mesh layer 107 also forms a shielding layer to isolate the photoelectric signals in the peripheral region, so that the CMOS devices in the peripheral region are not exposed to light and thus avoid generating additional leakage current.

[0086] In this embodiment of the invention, the filling structure of the deep trench isolation structure is specially designed. The filling structure is set as a superposition structure of a first semiconductor epitaxial layer 103, a second dielectric layer 104, and a third conductive material layer 105. In this way, when a voltage is applied to the third conductive material layer 105, the interface state formed by interface defects on the inner surface of the deep trench 102 can be controlled. Therefore, this embodiment of the invention can control the interface state at the interface between the deep trench isolation structure and the semiconductor substrate, thereby optimizing the interface state and reducing dark current and white pixels.

[0087] Furthermore, since all deep trenches 102 in this embodiment of the invention are interconnected, all third conductive material layers 105 are also electrically connected to each other. This embodiment of the invention can form a fourth conductive material layer 105a on top of the third conductive material layer 105 in a portion of the deep trench 102 closest to the outermost region and connect it to the external electrode through the fourth conductive material layer 105a. Therefore, the electrode lead-out structure of the deep trench isolation structure in this embodiment of the invention will not adversely affect the performance of the pixel region.

[0088] The deep trench isolation structure of this invention is particularly suitable for BSI CIS and stack CIS formed on the basis of BSI CIS. The electrode lead-out structure at the top of the fourth conductive material layer 105a of the deep trench isolation structure of this invention can be realized by the metal of the back gate mesh layer 107. The electrode lead-out structure of the deep trench isolation structure of this invention is easy to implement and does not bring additional process costs.

[0089] The manufacturing method of the deep trench isolation structure of CIS according to the present invention includes the following steps:

[0090] Step 1: Provide a first semiconductor substrate 101, which includes a pixel region and a peripheral region; the peripheral region surrounds the periphery of the pixel region.

[0091] Photolithography defines the formation area of ​​the deep trench 102, and plasma etching is performed on the first surface of the first semiconductor substrate 101 to form a plurality of the deep trenches 102 in the first semiconductor substrate 101; the deep trenches 102 are located in the pixel area, and the area between each deep trench 102 is the formation area of ​​a pixel unit; each deep trench 102 is interconnected.

[0092] In the method of this embodiment of the invention, the first semiconductor substrate 101 includes a silicon substrate.

[0093] The aspect ratio of the deep trench 102 is 1 to 50.

[0094] Step 2: Perform epitaxial growth process on the first semiconductor epitaxial layer 103 on the inner surface of the deep trench 102.

[0095] In the method of this embodiment of the invention, the first semiconductor epitaxial layer 103 includes a silicon epitaxial layer.

[0096] The first semiconductor epitaxial layer 103 also extends to the first surface of the first semiconductor substrate 101 outside the deep trench 102.

[0097] Step 3: Form a second dielectric layer 104 on the surface of the first semiconductor epitaxial layer 103.

[0098] In the method of this embodiment of the invention, the material of the second dielectric layer 104 includes a high dielectric constant layer.

[0099] Step 4: Form a third conductive material layer 105; the third conductive material layer 105 completely fills the deep trench 102, and the top surface of each third conductive material layer 105 is flush with the top surface of the third conductive material layer 105.

[0100] Step 5: Form a fifth dielectric layer and a fourth conductive material layer 105a. The fourth conductive material layer 105a is located in a portion of the deep trench 102 closest to the peripheral region. The fourth conductive material layer 105a is formed on the top surface of the third conductive material layer 105 and extends to the first surface of the first semiconductor substrate 101 outside the deep trench 102. The fifth dielectric layer is spaced between the fourth conductive material layer 105a and the first surface of the first semiconductor substrate 101 outside the deep trench 102.

[0101] The fourth conductive material layer 105a is used to connect with the external electrode.

[0102] The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers 105 to modulate the interface state of the inner surface of the deep trench 102, thereby eliminating the adverse effects of the interface defects on the interface state.

[0103] In the method of this embodiment of the invention, in step five, the fifth dielectric layer is formed by the superposition of the first semiconductor epitaxial layer 103 and the second dielectric layer 104 extending outside the deep trench 102.

[0104] The fourth conductive material layer 105a is an extension of the third conductive material layer 105, and step five is integrated into step four. Step four includes the following sub-steps:

[0105] The third conductive material layer 105 is formed, which completely fills the deep trench 102 and extends to the surface of the second dielectric layer 104 outside the deep trench 102.

[0106] After photolithography defines the formation area of ​​the fourth conductive material layer 105a, the third conductive material layer 105 is etched. After etching, outside the formation area of ​​the fourth conductive material layer 105a, the third conductive material layer 105 completely fills the deep trench 102, and the top surface of each third conductive material layer 105 is flush with the top surface of the third conductive material layer 105. In the formation area of ​​the fourth conductive material layer 105a, the retained third conductive material layer 105 completely fills the deep trench 102 and forms the fourth conductive material layer 105a.

[0107] In the method of this embodiment of the invention, the CIS is a back-illuminated CIS, the first surface of the first semiconductor substrate 101 is the back surface, and the second surface of the first semiconductor substrate 101 is the front surface.

[0108] Based on the back-illuminated CIS, the CIS is a stacked CIS; after step five, the following is also included:

[0109] The second surface of the first semiconductor substrate 101 and the front surface of the second semiconductor substrate 201 are bonded together using a bonding process; logic circuits are formed on the second semiconductor substrate 201.

[0110] The bonding process includes hybrid bonding.

[0111] The bonding process includes the following steps: Figure 1As shown, a bonding layer 203 is formed on the second surface of the first semiconductor substrate 101, and a bonding layer 202 is formed on the front side of the second semiconductor substrate 201. The bonding between the first semiconductor substrate 101 and the second semiconductor substrate 201 is achieved through the bonding layers 202 and 203.

[0112] A through-silicon via (TSV) 204 is formed, which passes through the front side of the first semiconductor substrate 101 from the back side and enters the second semiconductor substrate 201. The front metal layer of the first semiconductor substrate 101 and the front metal layer of the second semiconductor substrate 201 are connected through the TSV 204.

[0113] A back dielectric layer 106 and a back gate mesh layer 107 are also formed on the back side of the first semiconductor substrate 101. The back gate mesh layer 107 is formed by patterning back metal. The through-silicon via 204 is connected to the metal of the back gate mesh layer 107 corresponding to the top. The fourth conductive material layer 105a is connected to the metal of the back gate mesh layer 107 corresponding to the top. The back dielectric layer 106 is spaced between the metal of the third conductive material layer 105 and the back gate mesh layer 107 in each of the deep trenches 102 outside the formation area of ​​the fourth conductive material layer 105a.

[0114] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A deep trench isolation structure for CIS, characterized in that: A first semiconductor substrate includes a pixel region and a peripheral region; the peripheral region surrounds the periphery of the pixel region. Deep trench isolation structures are formed in the pixel area, and the area between each deep trench isolation structure is the forming area of ​​a pixel unit; The deep trench isolation structure includes: Deep trenches are formed in the first semiconductor substrate by plasma etching of the first surface of the first semiconductor substrate. The top surface of the deep trenches is flush with the first surface of the first semiconductor substrate, and the inner surface of the deep trenches has interface defects generated by the plasma etching. The deep trenches are interconnected. A first semiconductor epitaxial layer is formed on the inner surface of the deep trench; A second dielectric layer formed on the surface of the first semiconductor epitaxial layer in the deep trench; The third conductive material layer completely fills the deep trench, and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer; A fourth conductive material layer is also formed in a portion of the deep trench closest to the peripheral region. The fourth conductive material layer is formed on the top surface of the third conductive material layer and extends to the first surface of the first semiconductor substrate outside the deep trench. A fifth dielectric layer is spaced between the fourth conductive material layer and the first surface of the first semiconductor substrate outside the deep trench. The fourth conductive material layer is connected to the external electrode; The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers to modulate the interface state of the inner surface of the deep trench, thereby eliminating the adverse effects of the interface defects on the interface state.

2. The deep trench isolation structure of CIS as described in claim 1, characterized in that: The first semiconductor substrate includes a silicon substrate; The first semiconductor epitaxial layer includes a silicon epitaxial layer.

3. The deep trench isolation structure of CIS as described in claim 2, characterized in that: The material of the second dielectric layer includes a high dielectric constant layer.

4. The deep trench isolation structure of CIS as described in claim 1, characterized in that: The fourth conductive material layer is formed by extending the third conductive material layer, and the fifth dielectric layer is formed by stacking the first semiconductor epitaxial layer and the second dielectric layer extending outside the deep trench.

5. The deep trench isolation structure of CIS as described in claim 1, characterized in that: The CIS is a back-illuminated CIS, where the first surface of the first semiconductor substrate is the back side and the second surface of the first semiconductor substrate is the front side.

6. The deep trench isolation structure of CIS as described in claim 5, characterized in that: The CIS is a stacked CIS; The second surface of the first semiconductor substrate and the front surface of the second semiconductor substrate are bonded together; A logic circuit is formed on the second semiconductor substrate; A through-silicon via (TSV) passes from the back side of the first semiconductor substrate through the front side of the first semiconductor substrate and enters the second semiconductor substrate. The front metal layer of the first semiconductor substrate and the front metal layer of the second semiconductor substrate are connected through the TSV. A back dielectric layer and a back gate mesh layer are also formed on the back side of the first semiconductor substrate. The back gate mesh layer is formed by patterning back metal. The through-silicon via is connected to the metal of the back gate mesh layer corresponding to the top. The fourth conductive material layer is connected to the metal of the back gate mesh layer corresponding to the top. The back dielectric layer is spaced between the metal of the third conductive material layer and the back grid layer in each of the deep trenches outside the formation area of ​​the fourth conductive material layer.

7. The deep trench isolation structure of CIS as described in claim 1, characterized in that: The depth-to-width ratio of the deep trench is 1 to 50.

8. A method for manufacturing a deep trench isolation structure for CIS, characterized in that: Includes the following steps: Step 1: Provide a first semiconductor substrate, the first semiconductor substrate including a pixel region and a peripheral region; the peripheral region surrounds the periphery of the pixel region; Photolithography defines the formation area of ​​the deep trenches, and plasma etching is performed on the first surface of the first semiconductor substrate to form a plurality of the deep trenches in the first semiconductor substrate; the deep trenches are located in the pixel area, and the area between each deep trench is the formation area of ​​a pixel unit; each deep trench is interconnected; Step 2: Perform epitaxial growth process to create a first semiconductor epitaxial layer on the inner surface of the deep trench; Step 3: Form a second dielectric layer on the surface of the first semiconductor epitaxial layer; Step 4: Form the third conductive material layer; The third conductive material layer completely fills the deep trench, and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer; Step 5: Form a fifth dielectric layer and a fourth conductive material layer, wherein the fourth conductive material layer is located in a portion of the deep trench closest to the peripheral region, and the fourth conductive material layer is formed on the top surface of the third conductive material layer and extends to the first surface of the first semiconductor substrate outside the deep trench; The fifth dielectric layer is spaced between the fourth conductive material layer and the first surface of the first semiconductor substrate outside the deep trench; The fourth conductive material layer is used to connect with the external electrode; The external electrode is connected to an external control module, which provides an external voltage to each of the third conductive material layers to modulate the interface state of the inner surface of the deep trench, thereby eliminating the adverse effects of the interface defects on the interface state.

9. The method for manufacturing the deep trench isolation structure of CIS as described in claim 8, characterized in that: The first semiconductor substrate includes a silicon substrate; The first semiconductor epitaxial layer includes a silicon epitaxial layer.

10. The method for manufacturing the deep trench isolation structure of CIS as described in claim 9, characterized in that: The material of the second dielectric layer includes a high dielectric constant layer.

11. The method for manufacturing the deep trench isolation structure of CIS as described in claim 8, characterized in that: In step two, the first semiconductor epitaxial layer further extends to the first surface of the first semiconductor substrate outside the deep trench; In step five, the fifth dielectric layer is formed by the superposition of the first semiconductor epitaxial layer and the second dielectric layer extending out of the deep trench; The fourth conductive material layer is an extension of the third conductive material layer, and step five is integrated into step four. Step four includes the following sub-steps: The third conductive material layer is formed, which completely fills the deep trench and extends to the surface of the second dielectric layer outside the deep trench; After photolithography defines the formation area of ​​the fourth conductive material layer, the third conductive material layer is etched. After etching, outside the formation area of ​​the fourth conductive material layer, the third conductive material layer completely fills the deep trench and the top surface of each third conductive material layer is flush with the top surface of the third conductive material layer; in the formation area of ​​the fourth conductive material layer, the retained third conductive material layer completely fills the deep trench and forms the fourth conductive material layer.

12. The method for manufacturing the deep trench isolation structure of CIS as described in claim 8, characterized in that: The CIS is a back-illuminated CIS, where the first surface of the first semiconductor substrate is the back side and the second surface of the first semiconductor substrate is the front side.

13. The method for manufacturing the deep trench isolation structure of CIS as described in claim 12, characterized in that: The CIS is a stacked CIS; step five is followed by: The second surface of the first semiconductor substrate and the front surface of the second semiconductor substrate are bonded together using a bonding process; logic circuits are formed on the second semiconductor substrate. A through-silicon via (TSV) is formed, which passes through the front side of the first semiconductor substrate from the back side of the first semiconductor substrate and enters the second semiconductor substrate. The front metal layer of the first semiconductor substrate and the front metal layer of the second semiconductor substrate are connected through the TSV. A back dielectric layer and a back gate mesh layer are also formed on the back side of the first semiconductor substrate. The back gate mesh layer is formed by patterning back metal. The through-silicon vias are connected to the metal of the back gate mesh layer corresponding to the top. The fourth conductive material layer is connected to the metal of the back gate mesh layer corresponding to the top. The back dielectric layer is spaced between the metal of the third conductive material layer and the back gate mesh layer in each of the deep trenches outside the formation area of ​​the fourth conductive material layer.

14. The method for manufacturing the deep trench isolation structure of CIS as described in claim 13, characterized in that: The bonding process includes hybrid bonding.

15. The method for manufacturing the deep trench isolation structure of CIS as described in claim 8, characterized in that: The depth-to-width ratio of the deep trench is 1 to 50.

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