57results about How to "Improve interface state" patented technology

The invention discloses a light-emitting diode (LED) epitaxial wafer, a manufacturing method of the LED epitaxial wafer and an LED chip including the LED epitaxial wafer. The LED epitaxial wafer comprises an undoped GaN layer, an N-type GaN layer, an active layer and a P-type GaN layer which are sequentially arranged from the substrate surface to the outside. The active layer comprises one or more groups of quantum well layers, wherein each quantum well layer comprises an InGaN potential well layer, a GaN potential barrier layer and an MgN potential barrier layer which are sequentially arranged in the direction away from a substrate. The manufacturing method of the LED epitaxial wafer comprises the steps of sequentially forming the undoped GaN layer, the N-type GaN layer, the active layer and the P-type GaN layer from the substrate surface to the outside, wherein the active layer forming step is that one or more groups of quantum well layers are sequentially formed, and the quantum well layer forming step is that the InGaN potential well layer, the GaN potential barrier layer and the MgN potential barrier layer are sequentially formed from the surface of the N-type GaN layer to the outside. By the adoption of the manufacturing method of the LED epitaxial wafer, the LED luminance and the internal quantum efficiency are improved.

The invention provides a manufacturing method of a target module. The manufacturing method of the target module comprises the following steps: a tungsten titanium target blank and a copper back plateare provided, wherein a surface to be welded of the tungsten titanium target blank is a first welded surface, and a surface to be welded of the copper back plate is a second welded surface; the firstwelded surface and the second welded surface are oppositely arranged and bonded to form an initial target module; and a hot isostatic pressing process is performed on the initial target module to obtain the target module. As the hot isostatic pressing process is performed on the initial target module, large-area welding of the tungsten titanium target blank and the copper back plate can be realized, the bonding strength of the tungsten titanium target blank and the copper back plate can be improved, the formed target module can reach the welding bonding rate of above 99% and the welding strength of above 50 MPa, and desoldering of the target module in the use process can be prevented.

An image pickup element includes: a semiconductor substrate including a photoelectric conversion section for each pixel; a pixel separation groove provided in the semiconductor substrate; and a fixed charge film provided on a light-receiving surface side of the semiconductor substrate, wherein the fixed charge film includes a first insulating film and a second insulating film, the first insulating film being provided contiguously from the light-receiving surface to a wall surface and a bottom surface of the pixel separation groove, and the second insulating film being provided on a part of the first insulating film, the part corresponding to at least the light-receiving surface.

The invention provides a manufacturing method of an aluminum alloy product. The manufacturing method of the aluminum alloy product comprises the following steps: a first aluminum alloy plate and a second aluminum alloy plate are provided, wherein a surface to be welded of the first aluminum alloy plate is a first welded surface, and a surface to be welded of the second aluminum alloy plate is a second welded surface; the first welded surface is a plane, and a groove is formed in the second welded surface; or grooves are formed in the first welded surface and the second welded surface; the first welded surface and the second welded surface are oppositely arranged and bonded, and a water way structure, surrounded by the grooves, is formed between the first welded surface and the second welded surface to form an initial aluminum alloy product; the initial aluminum alloy product is filled in a cover; the cover is degassed to form a vacuum cover; then, a hot isostatic pressing process is performed on the initial aluminum alloy product; and the vacuum cover is removed to obtain the aluminum alloy product. As the hot isostatic pressing process is applied on the initial aluminum alloy product, the welding strength of the formed aluminum alloy product is improved, and meanwhile, deformation or even blockage of the water way structure is prevented.

Provided is a transistor and a formation method thereof. The formation method of the transistor include: providing a semiconductor substrate; successively forming, on the surface of the semiconductor substrate, a gate dielectric layer, a first barrier layer on the surface of the gate dielectric layer, and a sacrificial layer on the surface of the first barrier layer; forming an interlayer dielectric layer on the surface of the semiconductor substrate, wherein the surface of the interlayer dielectric layer is aligned to the top of the sacrificial layer; removing the sacrificial layer to form a slot; forming a second barrier layer, which covers the first barrier layer, in the slot, wherein the morphology of the second barrier layer and morphology of the first barrier layer on which the sacrificial layer has been removed are in complementation; forming a metal layer fully filling the slot on the surface of the second barrier layer, wherein the surface of the metal layer is aligned to the top of the interlayer dielectric layer. This invention reduces the leakage current of the gate of the transistor and improves the reliability and electrical properties of the transistor.

The invention discloses a metal oxide semiconductor electrical parameter testing device and a method of manufacture. A gate is a metal gate. A first P-type well region of an N-type substrate and a first N+ region form a first PN junction to constitute a first diode. A second P-type well region of the N-type substrate and a second N+ region form a second PN junction to constitute a second diode. The first diode is in anti-parallel connection with the second diode and is connected with the gate to form an N-type metal oxide semiconductor electrical parameter testing device. Or, the N-type substrate and the first P+ region form a third PN junction to constitute a third diode; the N-type substrate and the second P+ region form a fourth PN junction to constitute a fourth diode; and the third diode is in anti-parallel connection with the fourth diode and is connected with the gate to form a P-type metal oxide semiconductor electrical parameter testing device. According to the invention, positive charge or negative charge introduced due to plasma damage can be well discharged so as to enable small variation in threshold voltage.

The invention discloses a semiconductor structure and a formation method thereof. The method includes providing a substrate, wherein the substrate includes a first area; forming a gate dielectric layer on the first area of the substrate; forming a protective layer on the gate dielectric layer of the first area, wherein the material of the protective layer is a non-crystalline material, and the protective layer has doped ions; and forming a grid electrode on the protective layer of the first area. The protective layer can be taken as a work function layer of the formed semiconductor structure,so that the protective layer cannot be removed in follow-up process, and therefore, technological process can be simplified; and the protective layer can be protected from damaging the gate dielectriclayer during removing, so that the performance of the formed semiconductor structure can be improved.

The invention discloses an interconnection structure and a forming method of the interconnection structure. The forming method of the interconnection structure comprises the following steps: providing a semiconductor substrate, wherein a dielectric layer is formed on the surface of the semiconductor substrate; forming an opening in the dielectric layer, wherein the bottom of the opening is exposed out of the surface of the semiconductor substrate; forming a metal layer filling the opening in the opening, wherein the surface of the metal layer is flush with the top of the dielectric layer; forming a first cap layer on the surfaces of the metal cap layer and the dielectric layer, wherein the first cap layer is made from SiBC; and forming a second cap layer on the surface of the first cap layer. Through adoption of the forming method, the occurrence probability of a copper accumulation phenomenon in the interconnection structure is lowered; the electromigration service life of the interconnection structure is prolonged; and the reliability of the interconnection structure is enhanced.

The invention provides a formation method of GeOI, which comprises the following steps: forming a Ge-containing layer on a first substrate; adopting strontium (Sr) or barium (Ba) to process a first surface of the Ge-containing layer for forming a first passivated thin layer; overturning the first substrate, the Ge-containing layer and the first passivated thin layer and transferring to a silicon substrate with an oxide insulating layer on the surface; and removing the first substrate. In the embodiment of the invention, the passivated thin layer formed by a strontium germanide or a barium germanide belongs to the field of semiconductors, therefore, the interface state problem between a Ge material and an insulating oxide can be improved, the phenomena of electric leakage and scattering in the position of an interface can be reduced, and the migration performance of the Ge material can not be excessively reduced.

The invention discloses a method for forming a self-alignment metal silicide. The two times of annealing technologies are adopted, hydrogen isotope gas is introduced in the first time of annealing technology, the hydrogen isotope gas is used for reacting with trace oxygen in the atmosphere to eliminate the oxygen, metal layers such as Ni are prevented from being oxidized, and therefore surface defects (such as a pyramid shape) of the metal silicide are reduced or avoided, and the metal silicide with a flat appearance and good uniformity is formed; isotope atoms in the introduced hydrogen isotope gas can enter the interface of the metal silicide and a silicon substrate and are combined with Si to form a new key which can be hardly fractured, and therefore the defects at the interface are overcome and reduced, and the interface state (Dit) is improved.

The invention discloses a method for manufacturing an embedded Si (silicon) nanocrystalline SONOS (silicon-oxide-nitride-oxide-silicon) device. The method comprises the following steps: forming a first oxide layer on a substrate in which a grate electrode is formed, and implementing the first annealing process; forming a silicon nitride layer on the first oxide layer, and embedding the Si nanocrystalline in the silicon nitride layer; forming a second oxide layer on the silicon nitride layer and implementing the secondary annealing process; and forming a Si layer on the second oxide layer, and adopting the Si layer as a control grate. According to the method, implements the first annealing process is implemented after the first oxide layer is formed so that the interface state density of the substrate and the interface of the first oxide layer is reduced, the secondary annealing process after forming the second oxide layer is formed on the silicon nitride layer is implemented so that the interface states of the substrate and the first oxide layer are further improved, and the interface between the Si nanocrystalline and the silicon nitride is improved so that the electric charge can retain on the interface between the nanocrystalline and the silicon nitride easily during the compiling and erasing process, so that the reliability of the embedded Si nanocrystalline SONOS device is improved.

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the steps: forming a drift region on a substrate, and etching a well region trench; obtaining a well region in the well region trench through an epitaxial method; and manufacturing a trench gate structure, a source region and a drain region. According to the semiconductor device and the manufacturing method thereof, the well region is manufactured through etching in an epitaxial mode, so that a well region with uniform doping concentration in the longitudinal direction can be obtained, and the semiconductor device with uniform threshold voltage of a trench gate and a plane gate is obtained. The method is mainly characterized in that the well region is manufactured in an epitaxial mode, the uniformity of the longitudinal doping concentration of the well region is mainly optimized to ensure the consistency of the threshold voltage of the trench gate, so that the electrical property of the device is improved. According to the invention, the advantages of the trench gate can be exerted, and the problem of inconsistent threshold voltages of different parts of the trenchgate can be effectively avoided.

The invention discloses a field effect transistor, a preparation method and electronic equipment. The field effect transistor comprises a SiC substrate, a SiC epitaxial layer and a gate oxide structure which are sequentially arranged in a stacked mode, wherein the gate oxide structure comprises a transition layer, a barrier layer and an oxide layer which are sequentially stacked, the transition layer is arranged on the side, which is away from the SiC substrate, of the SiC epitaxial layer, the transition layer and the oxide layer are both made of SiO2, and the thickness of the transition layeris less than that of the oxide layer. Therefore, the interface between the gate oxide structure and the SiC epitaxial layer of the field effect transistor has a good interface state, so that the interface between the gate oxide structure and the SiC epitaxial layer has high mobility, the gate oxide structure has high reliability, and the field effect transistor is enabled to have good use performance.

The invention provides a high-electron-mobility transistor and a memory chip. The high-electron-mobility transistor comprises a substrate, a gallium nitride layer, a gallium nitride aluminum layer, a dielectric layer and an electrode, wherein one side of the gallium nitride layer is compounded on a surface layer of the substrate and the other side of the gallium nitride layer is compounded on a bottom portion of the gallium nitride aluminum layer; the dielectric layer is compounded on a top layer of the gallium nitride aluminum layer, and the dielectric layer is provided with at least two cut-through contact holes; the electrode includes a drain electrode, a gate electrode and a source electrode, and the drain electrode and the source electrode are arranged in the corresponding contact holes of the at least two corresponding cut-through contact holes; and the dielectric layer includes a metal oxide layer and/or an inorganic oxide layer, and the inorganic oxide layer includes a first silicon oxide layer. In the technical scheme, an interface state of the high-electron-mobility transistor is improved, a reverse direction leakage current of the transistor is effectively reduced and simultaneously reliability of the transistor is increased.

The invention provides a high-electron-mobility transistor and a memory chip. The high-electron-mobility transistor comprises a substrate, a gallium nitride layer, a gallium nitride aluminum layer, a dielectric layer and an electrode, wherein one side of the gallium nitride layer is compounded on a surface layer of the substrate and the other side of the gallium nitride layer is compounded on a bottom portion of the gallium nitride aluminum layer; the dielectric layer is compounded on a top layer of the gallium nitride aluminum layer, and the dielectric layer is provided with at least two cut-through contact holes; the electrode includes a drain electrode, a gate electrode and a source electrode, and the drain electrode and the source electrode are arranged in the corresponding contact holes of the at least two corresponding cut-through contact holes; and the dielectric layer includes a metal oxide layer and/or an inorganic oxide layer. In the technical scheme, an interface state of the high-electron-mobility transistor is improved, a reverse direction leakage current of the transistor is effectively reduced and simultaneously reliability of the transistor is increased.

The invention discloses a method for forming self-aligned metal silicide. The method has the advantages that double-step annealing processes are implemented, isotope gas of hydrogen is introduced in the second annealing process, the isotope gas of the hydrogen and trace oxygen in atmosphere react with each other, accordingly, the oxygen can be eliminated, the metal silicide can be prevented from being oxidized, surface defects (such as pyramid shapes) of the metal silicide can be reduced or prevented, and the metal silicide which has flat morphology and is excellent in uniformity can be formed; isotope atoms in the introduced isotope gas of the hydrogen can enter interfaces of the metal silicide and a silicon substrate and can be combined with Si to form new keys which are difficult to break, accordingly, defects at the interfaces can be repaired and reduced, and interface states (Dit) can be improved.

The invention relates to a transistor and a manufacturing method thereof. The transistor comprises a substrate of a first conductivity type; an epitaxial layer of a first conductivity type formed on the substrate; a trench formed in the epitaxial layer; an emission region of a first conductivity type formed at the bottom of the trench and the sidewall; a base region of a second conductivity type formed in the epitaxial layer and surrounding the trench; a base contact region formed in the epitaxial layer region to connect the base region. The forming steps of the base region includes forming afirst polysilicon layer of a second conductivity type on the bottom and sidewalls of the trench; performing a high temperature oxidation process of the first polysilicon layer such that the first polysilicon layer is oxidized into a first oxide layer, and impurities in the first polysilicon layer diffuse toward the epitaxial layer to form a second conductivity type base region surrounding the trench. The transistor has a good interface state between the base region and the emission region, and the amplification coefficient is stable.