Manufacturing method for nitrogenous grid electrode oxidation layer

Abstract

The invention provides a manufacturing method for a nitrogenous grid electrode oxidation layer. The manufacturing method includes the steps that a semiconductor substrate is provided; a thermal oxidation technology and real-time high-temperature nitridation heat treatment are performed on the semiconductor substrate, a grid electrode oxidation layer with a target thickness is formed on the semiconductor substrate, and the high-temperature nitridation heat treatment and / or the thermal oxidation technology is performed through using diluent gas; nitrogen is injected into the grid electrode oxidation layer through a plasma nitridation technology to form the nitrogenous grid electrode oxidation layer; a high-temperature annealing technology is adopted for stabilizing nitrogen distribution in the nitrogenous grid electrode oxidation layer and remedying plasma damage in the nitrogenous grid electrode oxidation layer. The number of Si-H bonds, S-O-H bonds and breakage bonds existing nearby a Si-SiO2 interface is reduced, stress in the grid electrode oxidation layer is reduced, and NBTI performance of a pMOSFET semiconductor device is effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a nitrogen-containing gate oxide layer. Background technique [0002] As the size of semiconductor devices and the thickness of the gate oxide layer continue to shrink, the gate oxide nitride process is widely used. The purpose of the nitride gate oxide process is to reduce the boron diffusion in pMOSFET by doping nitrogen in the gate oxide layer, so as to improve the resistance to hot carriers and increase the dielectric constant. However, the gate oxide layer formed by the gate oxide nitride process greatly enhances the negative bias temperature instability (NBTI: Negative Bias Temperature Instability) effect of the device. The NBTI effect will affect the use of semiconductor devices, and with the reduction of the technology node of semiconductor devices, NBTI has gradually become the bottleneck of the reliability of semiconductor devices, so ...

AI Technical Summary

Problems solved by technology

The PNA high-temperature annealing process used in the prior art is used to stabilize the distribution of N ions and repair the plasma damage in the gate oxide layer 20, but the high-temperature annealing process cannot timely and effectively repair the Si-H bond and S-O-H bond and Si-SiO 2 The broken bonds that occur near the interface cannot effectively improve the NBTI performance of pMOSFET semiconductor devices

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