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Method for forming self-aligned metal silicide

A technology of metal silicide and metal silicide layer, applied in the direction of electrical components, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of negative drift of threshold voltage and poor NBTI performance, so as to reduce defects and improve NBTI performance , reduce or avoid the effect of surface defects

Inactive Publication Date: 2015-02-18
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
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  • Application Information

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Problems solved by technology

In the existing manufacturing process, there are a large number of hole defects and Si-H bonds at the interface between the metal silicide and the silicon substrate. During the NBTI test, the Si-H bonds are thermally excited and broken to form Si dangling bonds. Combined with hydrogen and released in the form of hydrogen, further forming hole defects, causing a negative shift in the threshold voltage, making the NBTI performance of the device poor

Method used

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  • Method for forming self-aligned metal silicide
  • Method for forming self-aligned metal silicide
  • Method for forming self-aligned metal silicide

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Embodiment Construction

[0033] The embodiment of the present invention uses existing commonly used Ni as the material for forming metal silicide, and is based on a two-step annealing process, combined Figure 4 to Figure 5 Interprets the improvements of the technical solution of the present invention in detail, but the technical solution of the present invention is not limited thereto.

[0034] The method for forming a self-aligned metal silicide of this embodiment includes the following steps:

[0035] Step 1, such as Figure 4 As shown, a semiconductor substrate 11 is provided. The surface of the substrate 11 has a silicon region. The silicon region includes a source region 13 and a drain region 14 formed in the substrate 11 on both sides of the gate 12 and the gate 12 of the MOS transistor. The gate 12 includes a gate dielectric layer 121, a gate electrode layer 122, and sidewall spacers 123 formed on both sides of the gate dielectric layer and the gate electrode layer.

[0036] Before depositing the met...

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Abstract

The invention discloses a method for forming self-aligned metal silicide. The method has the advantages that double-step annealing processes are implemented, isotope gas of hydrogen is introduced in the second annealing process, the isotope gas of the hydrogen and trace oxygen in atmosphere react with each other, accordingly, the oxygen can be eliminated, the metal silicide can be prevented from being oxidized, surface defects (such as pyramid shapes) of the metal silicide can be reduced or prevented, and the metal silicide which has flat morphology and is excellent in uniformity can be formed; isotope atoms in the introduced isotope gas of the hydrogen can enter interfaces of the metal silicide and a silicon substrate and can be combined with Si to form new keys which are difficult to break, accordingly, defects at the interfaces can be repaired and reduced, and interface states (Dit) can be improved.

Description

Technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming self-aligned metal silicide. Background technique [0002] In semiconductor manufacturing technology, metal silicides are widely used in source / drain contacts and gate contacts to reduce contact resistance due to their low resistivity and good adhesion to other materials. The metal with high melting point reacts with silicon to form metal silicide, and metal silicide with low resistivity can be formed through one or more annealing processes. Early TiSi 2 Because of its narrow line effect is no longer suitable for 0.18um technology, it is 2 replace. CoSi 2 The formation of the same thickness of silicide needs to consume more polysilicon or silicon substrate, which can no longer meet the needs of source-drain shallow junction and ultra-shallow junction; CoSi 2 It shows obvious narrow line effect on polysilicon lines below 45 nanometers; ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/283
CPCH01L21/28
Inventor 肖天金
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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