Method of forming field effect transistor, method of adjusting electrical performance parameters, and structure

Abstract

This application discloses a method for forming a field-effect transistor (FET), a method for adjusting its electrical performance parameters, and a structure. The formation method includes: providing a semiconductor substrate and performing ion implantation on the semiconductor substrate to form an active region; forming a gate structure on the surface of the semiconductor substrate; implanting two or more types of ions on both sides of the gate structure to form a shallowly doped region; the two or more types of ions include fluoride ions; and annealing the semiconductor substrate. Furthermore, the formation method also includes: determining the fluoride ion implantation dose based on the adjustment amount of the FET's threshold voltage or on-state current. This application achieves the goal of adjusting the electrical performance of the FET using only a single ion implantation process by implanting fluoride ions into the shallowly doped region of the FET.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technology, and more specifically, to a method for forming a field-effect transistor, a method for adjusting electrical performance parameters, and a structure thereof. Background Technology

[0002] In the semiconductor manufacturing field, the metal oxide semiconductor field effect transistor (MOSFET) is the most commonly used device in semiconductor manufacturing processes, and its main structure is formed primarily through ion implantation.

[0003] To adjust the electrical performance parameters of field-effect transistors (FETs), two ion implantation processes are typically required, resulting in high production costs. On the other hand, when low-threshold voltage (LTV) FETs and non-LTV FETs share a single photomask for electrical performance adjustment, if a combination of shallow doped regions and halo region ion implantation is used, the electrical performance of both devices will drift simultaneously. Summary of the Invention

[0004] Therefore, the purpose of this application is to provide a method for forming a field-effect transistor, a method for adjusting electrical performance parameters, and a structure to alleviate the existing technical problems.

[0005] According to some embodiments, the first aspect of this application provides a method for forming a field-effect transistor, comprising: providing a semiconductor substrate and performing ion implantation on the semiconductor substrate to form an active region; forming a gate structure on the surface of the semiconductor substrate; implanting two or more ions on both sides of the gate structure to form a shallowly doped region; wherein the two or more ions include fluorine ions; and annealing the semiconductor substrate.

[0006] Optionally, the process parameters for implanting fluorine ions in the shallow doped region include: an implantation dose range of 1E14 to 1E16 atom / cm2, an implantation energy range of 5 keV to 20 keV, and an implantation tilt angle range of 5 degrees to 60 degrees.

[0007] Optionally, it also includes determining the fluoride ion implantation dose based on the adjustment amount of the threshold voltage or on-state current of the field-effect transistor.

[0008] Optionally, ions are implanted on both sides of the gate structure to form a halo region.

[0009] Optionally, fluoride ions are injected into the halo region.

[0010] Optionally, the implantation depth of fluoride ions is greater than the implantation depth of other ions besides fluoride ions in the shallow doped region.

[0011] Optionally, the annealing temperature for the annealing treatment is 1000℃-1200℃, and the duration is 9s-12s.

[0012] Optionally, the annealing process includes spike annealing.

[0013] The embodiments disclosed herein may have at least the following advantages: by implanting fluorine ions into the shallow doped region of the field-effect transistor, the purpose of regulating the electrical performance of the field-effect transistor is achieved using a single ion implantation process.

[0014] According to some embodiments, the second aspect of this application provides implanting fluorine ions into the shallow doped region and / or halo region of a field-effect transistor; and annealing the field-effect transistor.

[0015] Optionally, the process parameters for fluoride ion implantation include: an implantation dose range of 1E14 to 1E16 atom / cm2, an implantation energy range of 5 keV to 20 keV, and an implantation tilt angle range of 5 degrees to 60 degrees.

[0016] Optionally, it also includes determining the fluoride ion implantation dose based on the adjustment amount of the threshold voltage or on-state current of the field-effect transistor.

[0017] Optionally, the annealing process includes spike annealing.

[0018] The embodiments disclosed herein may have at least the following advantages: when low threshold voltage field-effect transistors and non-low threshold voltage field-effect transistors share a photomask for electrical performance adjustment, a single fluorine ion implantation process is used to achieve the purpose of adjusting the electrical performance of low threshold voltage field-effect transistors without affecting the electrical performance of non-low threshold voltage field-effect transistors.

[0019] According to some embodiments, a third aspect of this application provides a field-effect transistor structure, including: a semiconductor substrate, a gate structure, and a shallowly doped region; an active region is located in the semiconductor substrate; a gate structure is formed on the surface of the semiconductor substrate; the shallowly doped region is formed on both sides of the gate structure by implanting two or more ions using an ion implantation process; the two or more ions include fluorine ions.

[0020] Optionally, it also includes: a halo region, which is formed on both sides of the gate structure using an ion implantation process.

[0021] Optionally, the implantation depth of fluoride ions is greater than the implantation depth of other ions besides fluoride ions in the shallow doped region. Attached Figure Description

[0022] Figure 1 This is a schematic flowchart of a field-effect transistor formation method according to an embodiment of this application;

[0023] Figures 2 to 5This is a schematic diagram of a field-effect transistor formation process according to an embodiment of this application;

[0024] Figure 6 This is a schematic flowchart of a method for adjusting the electrical performance parameters of a field-effect transistor according to an embodiment of this application;

[0025] Figure 7 This is a schematic diagram of a field-effect transistor structure, illustrating a method for adjusting the electrical performance parameters of a field-effect transistor according to an embodiment of this application.

[0026] Figures 8(a) and 8(b) are schematic diagrams of the adjustment parameters of the electrical performance parameters of the low threshold voltage type field-effect transistor in the embodiments of this application;

[0027] Figures 9(a) and 9(b) are schematic diagrams of the adjustment parameters of the electrical performance parameters of the non-low threshold voltage type field-effect transistor in the embodiments of this application;

[0028] Figure 10 This is a schematic diagram of a field-effect transistor structure according to an embodiment of this application;

[0029] Figure 11 This is a schematic diagram of another field-effect transistor structure according to an embodiment of this application.

[0030] Figure label:

[0031] 10: Low threshold voltage field-effect transistor; 20: Non-low threshold voltage field-effect transistor; 100: Semiconductor substrate; 200: Gate structure; 210: Gate electrode layer; 220: Gate oxide layer; 300: Other ion distribution in the shallow doped region; 400: Fluorine ion distribution in the shallow doped region; 500: Ion distribution implanted in the halo region; 600: Source; 700: Drain. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to specific embodiments and accompanying drawings. It should be understood that these descriptions are merely exemplary and not intended to limit the scope of this application. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0033] The accompanying drawings illustrate layer structure diagrams according to embodiments of this application. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0035] Figure 1 This is a schematic diagram of a method for forming a field-effect transistor according to an embodiment of this application.

[0036] like Figure 1 As shown, the field-effect transistor formation method provided in this application mainly includes four steps, which are described in detail below.

[0037] Step S1: Provide a semiconductor substrate and perform ion implantation on the semiconductor substrate to form an active region.

[0038] Taking PMOS (P-Metal-Oxide-Semiconductor) as an example, N-type ions are implanted into the semiconductor substrate 100 to form an active region of a certain depth, such as arsenic ions. Arsenic is a pentavalent element, and other pentavalent impurity elements include phosphorus and antimony. When a pentavalent impurity is doped into the semiconductor substrate 100, its four valence electrons form covalent bonds with the valence electrons of its four adjacent main atoms, while its fifth valence electron cannot form a covalent bond and becomes a free electron. This doping method results in a surplus of free electrons, thus forming an N-type semiconductor from pentavalent impurity elements. Ion implantation utilizes an electric field to accelerate impurity ions and implant them into the semiconductor substrate.

[0039] In other embodiments, p-type ions can be implanted into the semiconductor substrate to form an active region, such as boron ions. Boron is a trivalent impurity element; its three valence electrons form covalent bonds with the valence electrons of its three neighboring host atoms. The absence of one valence electron creates a vacancy, resulting in p-type semiconductor doping. It should be noted that the semiconductor substrate 100 can be, but is not limited to, commonly used semiconductor substrate materials such as silicon, germanium, and germanium-silicon, and the type of implanted ions is selected according to actual requirements.

[0040] Step S2: A gate structure is formed on the surface of the semiconductor substrate.

[0041] Figure 2 A schematic diagram illustrating the formation of a gate structure on the surface of a semiconductor substrate is shown below. Figure 2A gate structure 200 is formed on the surface of a semiconductor substrate 100. The gate structure 200 includes a gate electrode layer 210 on the surface of the semiconductor substrate 100 and a gate oxide layer 220 on the surface of the gate electrode layer 210. The gate electrode layer 210 is made of polysilicon, doped polysilicon, or a metal, and the gate oxide layer 220 is made of silicon oxide or a high-dielectric material. In other embodiments, a silicon oxide layer or a silicon nitride layer is formed on the surface of the gate structure. The use of a silicon oxide layer or a silicon nitride layer can prevent subsequent ion implantation processes from implanting impurity ions into the gate oxide layer or the gate electrode, thus affecting the electrical performance of the gate structure.

[0042] In some embodiments, the gate structure 200 is formed by polysilicon exposure etching.

[0043] Step S3: Ion implantation to form a shallowly doped region. Specifically, two or more types of ions are implanted on both sides of the gate structure to form a shallowly doped region.

[0044] Figure 3 A schematic diagram of the shallowly doped region structure is shown; in Figure 3 On this basis, Figure 4 A schematic diagram illustrating the structure after fluorine ion implantation in the lightly doped region is shown. (Reference) Figure 3 and Figure 4 In the figure, the shallow doped region contains two or more types of ions. There are other ion distributions 300 and fluorine ion distributions 400 in the shallow doped region. The other ion distributions 300 in the shallow doped region contain at least one ion; for example, boron ions, boron difluoride, or a combination of both are used for doping in the other ion distributions 300. Therefore, the shallow doped region contains two or more types of ions. It should be noted that there is no restriction on the order in which the other ion distributions 300 and fluorine ion distributions 400 in the shallow doped region are formed; fluorine ions can be implanted first to form the fluorine ion distribution 400, or ions from the other ion distributions 300 in the shallow doped region can be implanted first to form the other ion distributions 300 in the shallow doped region.

[0045] It's important to note that doping in the shallow doped region can mitigate the short-channel effect and the hot carrier effect. The short-channel effect occurs when the channel length of a MOSFET transistor becomes comparable to the width of the depletion layer between the source and drain. In this short-channel effect, the charge in the depletion region under the MOSFET gate is no longer entirely controlled by the gate; a portion is controlled by both the source and drain, resulting in charge sharing in the depletion region. Furthermore, as the channel length decreases, the gate-controlled depletion region charge continuously decreases. As the gate-controlled depletion region charge decreases, less gate charge is needed to achieve inversion, thus lowering the threshold voltage of the field-effect transistor. When carriers gain significant energy from external sources, they become hot carriers. For example, under a strong electric field, carriers drift and accelerate along the field direction, gaining substantial kinetic energy and thus becoming hot carriers. The hot carrier effect is a major cause of device and integrated circuit failures in the semiconductor field.

[0046] Implanting fluorine ions into shallowly doped regions can improve the threshold voltage and on-state current of field-effect transistors (FETs). For example, if the other ion distribution 300 in the shallowly doped region contains boron ions, the fluorine ions in the fluorine ion distribution 400 in the shallowly doped region can enhance the diffusion of boron ions in the semiconductor substrate. Furthermore, from an atomic structure perspective, fluorine is heptodactyl, readily gaining electrons and providing holes, thereby increasing the on-state current of the FET. It should be noted that ion implantation requires first ionizing atoms to charge them and form ions; for example, B+ ions can be formed by ionizing boron atoms or boron fluoride. An electric field is then used to accelerate the ions, allowing them to penetrate the semiconductor substrate. If the atoms are neutral, ion implantation cannot be achieved using an electric field for acceleration.

[0047] In some embodiments, the process parameters for implanting fluorine ions into the shallow doped region include: an implantation dose range of 1E14 to 1E16 atom / cm. 2 The implantation energy ranges from 5 keV to 20 keV, and the implantation tilt angle ranges from 5 degrees to 60 degrees. For example, the fluorine ion implantation energy is 15 keV, and the implantation tilt angle is 21 degrees. It should be noted that the fluorine ion implantation dose determines the doping concentration; that is, a larger implantation dose results in a higher doping concentration, and a higher doping concentration results in a higher concentration of majority carriers in the semiconductor. The fluorine ion implantation energy and tilt angle determine the depth and shape of the doping distribution. Ion implantation can precisely control low-concentration doping distributions that are difficult to obtain using diffusion methods, i.e., it achieves precise control of the implantation dose. For example, the ion implantation amount can be precisely controlled by measuring the current flowing through the substrate.

[0048] In some embodiments, the implantation depth of fluoride ions is greater than the implantation depth of other ions besides fluoride ions in the shallow doped region. The deeper penetration of fluoride ions compared to other ions implanted in the shallow doped region further increases the on-state current of the field-effect transistor. Exemplarily, the energy and tilt angle of the fluoride ion implantation are adjusted so that the implantation depth of fluoride ions is greater than the implantation depth of other ions besides fluoride ions in the shallow doped region.

[0049] In some embodiments, the fluoride ion implantation dose is determined based on the adjustment amount of the field-effect transistor's threshold voltage or on-state current. Exemplarily, increasing the fluoride ion implantation dose can decrease the threshold voltage of the field-effect transistor and increase its on-state current. For example, an increase of 1E15 atom / cm² in the fluoride ion implantation dose... 2 The threshold voltage of the field-effect transistor (FET) decreases by 50 mV, while the on-state current increases by 26 μA / µm. Therefore, the fluoride ion implantation dose can be determined based on the adjustment of the FET's threshold voltage or on-state current.

[0050] Step S4: Anneal the semiconductor substrate. For example, after ion implantation in the shallow doped region, annealing is required to repair damage to the semiconductor substrate caused by the implantation of dopant atoms. It should be noted that the implanted fluorine ions do not require separate annealing; they can be annealed together with the ions implanted in the shallow doped region.

[0051] It's important to note that the process of fluoride ions entering the semiconductor substrate is destructive, ionizing some substrate atoms or breaking their valence bonds. Semiconductor substrate atoms have small radii, resulting in low energy barriers to transitioning to a stable state. Upon heating, the semiconductor substrate atoms automatically repair themselves; incorrect valence bond arrangements are corrected, and fixed charges are replenished by external electrons. After treatment with appropriate temperature and time, the semiconductor substrate atoms are restored, as if neutral atoms had diffused into them. This thermal repair process is called annealing. Illustratively, boron and fluoride ions implanted in the shallowly doped region are annealed together to repair the semiconductor substrate atoms.

[0052] In some embodiments, the annealing temperature for the annealing process is 1000℃-1200℃, and the duration is 9s-12s.

[0053] In some embodiments, the annealing process includes peak annealing. It should be noted that peak annealing is a type of immersion annealing. In peak annealing, the wafer is heated to a set temperature at an extremely rapid rate, up to nearly 250°C / s, and then cooled to below 600°C at a relatively rapid rate, up to nearly 90°C / s. Peak annealing is mainly used in the manufacturing process of field-effect transistors (FETs) with diameters below 0.13µm, following ion implantation at lightly doped drain and source / drain electrodes. It repairs lattice damage and defects caused by ion implantation while forming an ultra-shallow junction. For example, the peak annealing process involves heating to 1020°C at a rate of 220°C / s, holding for 10s, and then cooling to below 600°C at a rate of 90°C / s.

[0054] In some embodiments, reference Figure 5 The field-effect transistor formation method provided in this application involves implanting ions on both sides of the gate structure to form a halo region. To further alleviate the short-channel effect and suppress the drain-induced barrier reduction effect, an ion distribution 500 of the halo region implantation is formed in the substrate 100 by implanting dopant ions of the same type as the substrate.

[0055] It should be noted that the halo region is a heavily doped region of the substrate near the source and drain. For example, if substrate 100 is an N-type substrate, then the doping type of the halo region is N+, which narrows the depletion region or space charge region of the PN junction, preventing the depletion regions at the source and drain from connecting and causing source-drain conduction. Besides preventing source-drain conduction, the doping in the halo region also suppresses the drain-induced barrier lowering effect. The drain-induced barrier lowering effect (DIBL) is an important physical effect in very large-scale MOSFET devices, manifested as a decrease in the threshold voltage caused by the drain voltage, leading to an increase in drain-source current.

[0056] For example, the ion implantation angle in the halo region is greater than that in the shallowly doped region to suppress subthreshold current degradation in the field-effect transistor. (Reference) Figure 5 The ion implantation depth in the ion distribution 500 of the halo region is greater than the ion implantation depth in other ion distributions 300 and fluorine ion distribution 400 of the shallow doped region. It should be noted that the ions implanted in the halo regions on both sides of the gate structure 200 can be implanted symmetrically or asymmetrically; there are no restrictions on the implantation method.

[0057] In some embodiments, fluoride ions are implanted into the halo region. (Reference) Figure 4 and Figure 5The distributions of other ions in the shallow doped region (300), the fluorine ion distribution in the shallow doped region (400), and the ion distribution implanted in the halo region (500) overlap. For example, the tilt angle of the ions implanted in the halo region is 40 to 50 degrees, and the tilt angle of the fluorine ions implanted ranges from 5 to 60 degrees. The tilt angle range of the fluorine ions implanted includes the tilt angle range of the ions implanted in the halo region; therefore, fluorine ions can be implanted in the halo region.

[0058] It should be noted that there are no restrictions on the formation order of other ion distributions 300 in the shallow doped region, fluorine ion distribution 400 in the shallow doped region, and ion distribution 500 implanted in the halo region.

[0059] Furthermore, the formation process of the field-effect transistor also includes the formation of the source and drain, which can be formed by ion implantation. For example, if the substrate 100 is a P-type substrate, the doping type of the ion distribution 500 implanted in the halo region is P+, and the source and drain are formed with N+ type doping by ion implantation; similarly, if the substrate 100 is an N-type substrate, the doping type of the source and drain is P+; there are no restrictions on the doping type and the doped ions.

[0060] Figure 6 This is a schematic flowchart of a method for adjusting the electrical performance parameters of a field-effect transistor according to an embodiment of this application.

[0061] like Figure 1 As shown, the method for adjusting the electrical performance parameters of a field-effect transistor in this application mainly includes two steps, which are described in detail below.

[0062] Step S31: Implant fluoride ions into the shallow doped region and / or halo region.

[0063] Figure 7 This is a schematic diagram of a field-effect transistor structure, illustrating a method for adjusting the electrical performance parameters of a field-effect transistor according to an embodiment of this application.

[0064] refer to Figure 7 Low threshold voltage field-effect transistor 10 and non-low threshold voltage field-effect transistor 20 have their electrical performance parameters adjusted under the same photomask. If the adjustment is performed by combining shallow doping region with halo region ion implantation, the electrical performance of both devices will drift simultaneously.

[0065] Figures 8(a) and 8(b) are schematic diagrams illustrating the adjustment of electrical performance parameters of the low threshold voltage field-effect transistor (FET) according to embodiments of this application. Figure 8(a) shows the threshold voltage parameter adjustment, and Figure 8(b) shows the on-state current parameter adjustment. Referring to Figures 8(a) and 8(b), "none" indicates the case without fluorine ion doping, and "F" indicates the case with fluorine ion doping. In Figure 8(a), without fluorine ion doping, the threshold voltage Vt of the FET is approximately 0.29V; with fluorine ion doping, the threshold voltage Vt is approximately 0.24V. In Figure 8(b), without fluorine ion doping, the on-state current IDS of the FET is approximately 272µA / µm; with fluorine ion doping, the on-state current IDS is approximately 298µA / µm. Therefore, by implanting fluorine ions into the shallow doped region and / or the halo region, the threshold voltage Vt and the on-state current IDS of the low threshold voltage field-effect transistor 10 can be significantly reduced compared to the case without fluorine ion implantation.

[0066] Figures 9(a) and 9(b) are schematic diagrams illustrating the adjustment of electrical performance parameters of the non-low threshold voltage field-effect transistor (FET) according to embodiments of this application. Figure 9(a) shows the threshold voltage parameter adjustment, and Figure 9(b) shows the on-state current parameter adjustment. Referring to Figures 9(a) and 9(b), "none" indicates the case without fluorine ion doping, and "F" indicates the case with fluorine ion doping. In Figure 9(a), the threshold voltage Vt of the FET is approximately 0.55V for both the case without and with fluorine ion doping. In Figure 9(b), the on-state current IDS of the FET is approximately 510µA / µm for both the case without and with fluorine ion doping. Therefore, for the non-low threshold voltage FET 20, there is no significant change in the threshold voltage Vt and the on-state current IDS compared to the case without fluorine ion implantation. This achieves the technical effect of adjusting the electrical performance parameters of the low threshold voltage FET 10 using only one fluorine ion implantation process, without affecting the non-low threshold voltage FET 20.

[0067] The table below summarizes the changes in electrical performance parameters of a low threshold voltage field-effect transistor 10 and a non-low threshold voltage field-effect transistor 20 under two conditions: with and without fluorine ion implantation.

[0068]

[0069] As shown in the table above, the electrical performance parameters of the low threshold voltage field-effect transistor 10 are significantly improved after fluorine ion implantation in the shallow doped region and / or halo region.

[0070] It should be noted that when implanting fluorine ions into the shallow doped region and / or halo region, fluorine ions can be implanted first, followed by the implantation of other ions into the shallow doped region and / or halo region. Alternatively, other ions can be implanted into the shallow doped region and / or halo region to form the shallow doped region or halo region, and then fluorine ions can be implanted.

[0071] In some embodiments, the process parameters for implanting fluorine ions into the shallow doped region include: an implantation dose range of 1E14 to 1E16 atom / cm. 2 The implantation energy ranges from 5 keV to 20 keV, and the implantation tilt angle ranges from 5 degrees to 60 degrees. For example, the fluoride ion implantation energy is 15 keV, and the implantation tilt angle is 21 degrees.

[0072] In some embodiments, the fluoride ion implantation dose is determined based on the adjustment amount of the field-effect transistor's threshold voltage or on-state current. Exemplarily, increasing the fluoride ion implantation dose can decrease the threshold voltage of the field-effect transistor and increase its on-state current. For example, an increase of 1E15 atom / cm² in the fluoride ion implantation dose... 2 The threshold voltage of the field-effect transistor decreases by 50mV, and the on-state current of the field-effect transistor increases by 26uA / um.

[0073] Step S41: Perform annealing. It should be noted that the implanted fluorine ions do not require separate annealing; they can be annealed together with the ions implanted in the shallow doped region and / or halo region.

[0074] In some embodiments, the annealing process includes peak annealing. For example, the peak annealing process involves heating to 1020°C at a heating rate of 220°C / s, holding for 10s, and then cooling to below 600°C at a cooling rate of 90°C / s.

[0075] Figure 10 This is a schematic diagram of a field-effect transistor structure according to an embodiment of this application.

[0076] like Figure 10 The field-effect transistor structure shown includes: a semiconductor substrate 100, a gate structure 200, and a lightly doped region; the active region is located in the semiconductor substrate 100; the gate structure 200 is formed on the surface of the semiconductor substrate; the lightly doped region is formed on both sides of the gate structure by implanting two or more types of ions using an ion implantation process; the two or more types of ions include fluorine ions. (Reference) Figure 10 The ion distribution in the shallow doped region includes other ion distributions 300 and fluorine ion distributions 400. Furthermore, the field-effect transistor also includes a source 600 and a drain 700, which optionally are formed by ion implantation.

[0077] For example, the doped ions in the shallow doped region other ion distribution 300 are boron ions. The boron ions can be ionized from boron fluoride and then implanted into the field effect transistor structure through an ion implantation process to form the shallow doped region other ion distribution 300. Similarly, fluorine ions can also be ionized from elemental fluorine or its compounds and then implanted to form the shallow doped region fluorine ion distribution 400.

[0078] In some embodiments, the implantation depth of fluoride ions is greater than the implantation depth of other ions besides fluoride ions in the shallow doped region, so as to further improve the on-state current of the field-effect transistor.

[0079] Figure 11 This is a schematic diagram of another field-effect transistor structure according to an embodiment of this application.

[0080] and Figure 10 compared to, Figure 11 The field-effect transistor structure embodiment shown also includes a halo region, which is formed on both sides of the gate structure using an ion implantation process. The ion distribution 500 implanted in the halo region is shown in the figure, thereby further mitigating the short-channel effect and suppressing the drain-induced barrier reduction effect.

[0081] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this application and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this application should be included within the protection scope of this application. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.

Claims

1. A method for forming a field-effect transistor, characterized in that, include: A semiconductor substrate is provided and ion implantation is performed on the semiconductor substrate to form an active region; A gate structure is formed on the surface of the semiconductor substrate; Ions are implanted on both sides of the gate structure to form a halo region and a lightly doped region, wherein the ion implantation angle in the halo region is greater than the ion implantation angle in the lightly doped region. Fluorine ions are implanted in the shallow doped region and the halo region. The shallow doped region includes other ion distributions in the shallow doped region and fluorine ion distributions in the shallow doped region. The implantation depth of the fluorine ions is greater than the implantation depth of the other ion distributions in the shallow doped region, and the implantation depth of the fluorine ions in the halo region is greater than the implantation depth of the fluorine ions in the fluorine ion distributions in the shallow doped region. The semiconductor substrate is annealed.

2. The forming method according to claim 1, characterized in that, The process parameters for implanting fluorine ions into the shallow doped region include: an implantation dose range of 1E14 to 1E16 atom / cm2, an implantation energy range of 5 keV to 20 keV, and an implantation tilt angle range of 5 degrees to 60 degrees.

3. The forming method according to claim 1, characterized in that, Also includes: The fluoride ion implantation dose is determined based on the adjustment amount of the threshold voltage or on-state current of the field-effect transistor.

4. The forming method according to claim 1, characterized in that, The annealing temperature for the annealing process is 1000℃-1200℃, and the duration is 9s-12s.

5. The forming method according to claim 1, characterized in that, The annealing process includes spike annealing.

6. A field-effect transistor structure, characterized in that, include: A semiconductor substrate, an active region located within the semiconductor substrate, and a gate structure located on the surface of the semiconductor substrate; The shallow doped region and the halo region are both formed on both sides of the gate structure by ion implantation process, and the ion implantation angle of the halo region is greater than that of the shallow doped region. The shallow doped region includes other ion distributions in the shallow doped region and fluorine ion distributions in the shallow doped region. Fluorine ions are implanted in the shallow doped region and the halo region. The implantation depth of the fluorine ions is greater than the implantation depth of the other ion distributions in the shallow doped region, and the implantation depth of the fluorine ions in the halo region is greater than the implantation depth of the fluorine ions in the fluorine ion distributions in the shallow doped region.

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