Irregular display effect display control method and device, equipment and storage medium
By combining an HDMI signal input module, an impedance adjustment module, and an FPGA processing module, the output timing of the HDMI signal is disrupted and reorganized, solving the problem of irregular display effects in existing technologies and enabling diverse display effect applications.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN MAITUOSI ELECTRONIC INFORMATION TECH CO LTD
- Filing Date
- 2022-07-28
- Publication Date
- 2026-06-16
AI Technical Summary
Existing technologies are insufficient to achieve diverse irregular display effects and cannot meet the display needs of different application scenarios.
By combining an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module, the output timing is received and disrupted, and timing reordering is performed to produce irregular display effects.
It enables the generation of irregular display effects, meets the application needs of various occasions, and improves the stability and reliability of display effects.
Smart Images
Figure CN115834812B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display control technology, and in particular to a method, apparatus, device, and storage medium for controlling irregular display effects. Background Technology
[0002] A display system is an electronic system used to provide visual information. Depending on the application, a display system uses one or more display devices to provide the visual information needed by a single person or a group of people, receives signals from different electronic devices or systems, and generally needs to be equipped with appropriate input devices to enable human-machine interaction and necessary recording equipment.
[0003] In the current technological landscape, diverse needs exist across various industries, ushering in an era of diversified demands. In the video display industry, various video creative ideas can generate diverse artistic value. For example, the various patterns required during video production provide special video effects, meeting the display needs of different applications. Therefore, inventing a method for controlling irregular display effects has become an urgent problem for technicians in this field. Summary of the Invention
[0004] To address the above-mentioned deficiencies, this invention provides a method, apparatus, device, and storage medium for controlling irregular display effects, thereby resolving the problems existing in the prior art.
[0005] To address the aforementioned technical problems, this invention provides a method for controlling irregular display effects. The method is applied to an irregular display effect control device, which includes an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module. The HDMI signal input module, impedance adjustment module, FPGA processing module, and HDMI signal output module are connected sequentially. The method includes:
[0006] Receives HDMI signals with the first output timing set according to the CTA-861-G video standard;
[0007] Based on a preset impedance change value, the output timing of the HDMI signal is disrupted;
[0008] Receive the HDMI signal after its timing is corrupted, and perform timing restoration on the HDMI signal;
[0009] The timing-reformed HDMI signal is acquired and output to the display terminal to produce an irregular display effect.
[0010] Preferably, receiving the HDMI signal after its timing has been disrupted and then performing timing restoration on the HDMI signal includes:
[0011] Receive the HDMI signal after the output timing is corrupted, and perform a first-level buffering on the HDMI signal;
[0012] Read the HDMI signal from the first-level cache and scale the HDMI signal.
[0013] The scaled HDMI signal is then buffered at a second level.
[0014] Obtain user instructions and adjust the second output timing of the HDMI signal according to the user instructions;
[0015] The second output timing is output through the internal phase-locked loop of the FPGA processing module according to a preset clock.
[0016] Preferably, receiving the HDMI signal with the first output timing set according to the video standard CTA-861-G includes:
[0017] The HDMI signals include a first HDMI signal TMDS data0, a second HDMI signal TMDS data1, a third HDMI signal TMDS data2, and a fourth HDMI signal TMDS clk.
[0018] Preferably, the irregular display effect display control method further includes;
[0019] In the second-level buffer, the frame rate of the HDMI signal is obtained according to a preset clock.
[0020] Based on the frame rate of the HDMI signal, the HDMI signal is subjected to variable detection processing to adapt to the input / output processing rate.
[0021] Preferably, reading the HDMI signal from the first-level buffer and scaling the HDMI signal includes:
[0022] The scaling algorithm is implemented using the LANCZOS algorithm.
[0023] To address the aforementioned technical problems, embodiments of the present invention provide an irregular display effect display control device, the device comprising:
[0024] An HDMI signal input module is used to receive HDMI signals with the first output timing set according to the CTA-861-G video standard.
[0025] An impedance adjustment module is used to disrupt the output timing of the HDMI signal based on a preset impedance change value.
[0026] The FPGA processing module is used to receive the HDMI signal after the output timing is corrupted and to perform timing restoration on the HDMI signal.
[0027] An HDMI signal output module is used to acquire the timing-reformed HDMI signal and output it to a display terminal to produce an irregular display effect.
[0028] Preferably, the impedance adjustment module includes a first impedance adjustment unit, a second impedance adjustment unit, a third impedance adjustment unit, and a fourth impedance adjustment unit;
[0029] The first impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; the second impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; the third impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; and the fourth impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively.
[0030] Preferably, the first impedance adjustment unit includes a first sliding rheostat and a second sliding rheostat;
[0031] The first end of the first sliding rheostat is electrically connected to the HDMI signal input module, the second end of the first sliding rheostat is left floating, and the third end of the first sliding rheostat is electrically connected to the FPGA processing module. The first end of the second sliding rheostat is electrically connected to the HDMI signal input module, the second end of the second sliding rheostat is left floating, and the third end of the second sliding rheostat is electrically connected to the FPGA processing module.
[0032] To address the aforementioned technical problems, this invention provides an irregular display effect display control device, comprising: at least one processor, at least one memory, and computer program instructions stored in the memory, wherein when the computer program instructions are executed by the processor, the method of the first aspect described above is implemented.
[0033] To address the aforementioned technical problems, embodiments of the present invention provide a storage medium storing computer program instructions, which, when executed by a processor, implement the method of the first aspect described above.
[0034] In summary, the present invention provides a method, apparatus, device, and storage medium for controlling irregular display effects. This invention is applied to an irregular display effect control device, which includes an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module, wherein the HDMI signal input module, the impedance adjustment module, the FPGA processing module, and the HDMI signal output module are connected sequentially. The method includes receiving an HDMI signal with an output timing set according to the video standard CTA-861-G; disrupting the output timing of the HDMI signal according to a preset impedance change value; receiving the HDMI signal with disrupted output timing and performing timing realignment on the HDMI signal; acquiring the timing realigned HDMI signal and outputting it to a display terminal to generate an irregular display effect. Therefore, this invention can generate irregular display effects, has a wide range of applications, and meets the needs of various application scenarios. Attached Figure Description
[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a flowchart of the irregular display effect display control method according to an embodiment of the present invention.
[0037] Figure 2 This is a flowchart of the irregular display effect display control method of the present invention, which receives the HDMI signal after the timing of the output is disrupted and performs timing reordering on the HDMI signal.
[0038] Figure 3 This is a flowchart illustrating the second-level buffering of the scaled HDMI signal in the irregular display effect display control method of this invention.
[0039] Figure 4 This is a schematic diagram of the irregular display effect display control device according to an embodiment of the present invention.
[0040] Figure 5 This is a schematic diagram of an impedance adjustment module according to an embodiment of the present invention.
[0041] Figure 6 This is a schematic diagram of the structure of the irregular display effect display control device according to an embodiment of the present invention. Detailed Implementation
[0042] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.
[0043] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.
[0044] Please see Figure 1 , Figure 1 This application provides a method for controlling irregular display effects. The method is applied to an irregular display effect control device, which includes an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module. The HDMI signal input module, the impedance adjustment module, the FPGA processing module, and the HDMI signal output module are connected sequentially. The method includes:
[0045] S1. Receive HDMI signal with the first output timing set according to video standard CTA-861-G;
[0046] Specifically, the video standard CTA-861-G is an existing video signal timing standard, officially named VESA Display Monitor Timing Standard, which includes CVT, CVT-RB, and CTA-861. In this embodiment, the output timing of the HDMI signal is first preset according to the video standard CTA-861-G, and then input through the HDMI signal input module.
[0047] S2. Disrupt the output timing of the HDMI signal according to the preset impedance change value;
[0048] Specifically, by adjusting the impedance of the impedance circuit through a preset impedance change value, the impedance change will cause the first output timing to reflect, thereby causing problems such as overshoot, ringing, and jitter, which will disrupt the timing in the HDMI signal transmission and cause the video signal to be interfered with to varying degrees, so as to produce irregular display effects in the future.
[0049] S3. Receive the HDMI signal after the output timing is corrupted, and perform timing restoration on the HDMI signal;
[0050] S4. Obtain the timing-reformed HDMI signal and output it to the display terminal to produce an irregular display effect.
[0051] Specifically, a normal receiving system cannot receive a damaged HDMI signal, resulting in interruption or complete failure to display. In order to receive damaged HDMI signals, this application adds an FPGA processing module to the back end to buffer the damaged HDMI signal for timing reordering.
[0052] Specifically, the FPGA processing module receives the corrupted video signal and performs timing reordering on the HDMI signal in order to obtain an irregular display effect based on the new output timing.
[0053] In summary, this application provides a method for controlling irregular display effects. This invention is applied to an irregular display effect control device, which includes an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module. The HDMI signal input module, impedance adjustment module, FPGA processing module, and HDMI signal output module are connected sequentially. The method includes receiving an HDMI signal with an output timing set according to the CTA-861-G video standard; disrupting the output timing of the HDMI signal according to a preset impedance change value; receiving the HDMI signal with disrupted output timing and performing timing realignment on the HDMI signal; acquiring the timing realigned HDMI signal and outputting it to a display terminal to generate an irregular display effect. Therefore, this invention can generate irregular display effects, has a wide range of applications, and meets the needs of various application scenarios.
[0054] Based on the above embodiments:
[0055] Please refer to Figure 2 , Figure 2 This application provides a flowchart for receiving an HDMI signal whose output timing has been disrupted and for performing timing reordering on the HDMI signal.
[0056] As a preferred embodiment, receiving the HDMI signal after its timing has been disrupted, and then performing timing restoration on the HDMI signal, includes:
[0057] S31. Receive the HDMI signal after the output timing is corrupted, and buffer the HDMI signal in the first level.
[0058] Specifically, the FPGA processing module receives the corrupted HDMI video signal and caches it in DDR3 for the first-level cache. In this embodiment, the DDR3 for the first-level cache can be implemented using a W631GG6MB, and no specific limitation is made here.
[0059] S32. Read the HDMI signal from the first-level buffer and perform scaling processing on the HDMI signal;
[0060] Specifically, the first-level cache is stored in DDR3, so that when the scaling factor is large, the image scaling module can utilize the time of the blanking region. Otherwise, the image scaling module may not be able to process it in time, thus improving the reliability of the scaling process.
[0061] S33. The scaled HDMI signal is buffered at a second level.
[0062] Specifically, the first-level cache is read, the HDMI signal is scaled, and then the HDMI signal is stored again in DDR3, i.e., the second-level cache. In this embodiment, the DDR3 of the second-level cache can be implemented using a W631GG6MB, and no specific limitation is made here.
[0063] S34. Obtain user instructions and adjust the second output timing of the HDMI signal according to the user instructions;
[0064] Specifically, in this embodiment, after the HDMI signal is stored in the second-level buffer, the user can input user commands through the host computer, and the FPGA processing module adjusts the timing of the HDMI signal according to the user commands to obtain the second output timing.
[0065] S35. The second output timing is output through the internal phase-locked loop of the FPGA processing module according to the preset clock.
[0066] Specifically, the preset clock is newly generated by the FPGA phase-locked loop. The timing stability generated by this preset clock is high, thereby ensuring the stability of the second output timing and improving the stability and reliability of the display effect.
[0067] As a preferred embodiment, receiving the HDMI signal with the first output timing set according to the video standard CTA-861-G includes:
[0068] The HDMI signals include a first HDMI signal TMDS data0, a second HDMI signal TMDS data1, a third HDMI signal TMDS data2, and a fourth HDMI signal TMDS clk.
[0069] Specifically, the HDMI signal in this application is a differential signal. It is understood that a differential signal differs from a traditional signal with one signal line and one ground line. Differential transmission transmits the signal on both lines, with the two signals having the same amplitude but opposite phase. Differential signals offer high precision and strong anti-interference capabilities.
[0070] Please refer to Figure 3 , Figure 3 This application provides a flowchart for performing a second-level buffering of the scaled HDMI signal.
[0071] As a preferred embodiment, the irregular display effect display control method further includes;
[0072] S331. In the second-level buffer, the frame rate of the HDMI signal is obtained according to a preset clock.
[0073] S332. Based on the frame rate of the HDMI signal, perform variable detection processing on the HDMI signal to adapt to the input / output processing rate.
[0074] Specifically, the second-level buffer of this application uses 4-frame processing to perform simple frame-changing processing without the need for complex frame-changing mechanisms for control. For example, if the input HDMI signal has a frame rate of 60 FPS and the output HDMI signal has a frame rate of 24 FPS, since there is space to buffer 3 frames, even if the input signal rate is faster than the output signal rate, no read / write conflict will occur, resulting in high reliability.
[0075] As a preferred embodiment, reading the HDMI signal from the first-level buffer and scaling the HDMI signal includes:
[0076] The scaling algorithm is implemented using the LANCZOS algorithm. In another preferred embodiment, the scaling algorithm is not specifically limited.
[0077] Please see Figure 4 This invention provides an irregular display effect display control device, the device comprising:
[0078] HDMI signal input module 1 is used to receive HDMI signals with the first output timing set according to the video standard CTA-861-G;
[0079] Impedance adjustment module 2 is used to disrupt the output timing of the HDMI signal according to a preset impedance change value;
[0080] FPGA processing module 3 is used to receive the HDMI signal after the output timing is corrupted and to perform timing restoration on the HDMI signal;
[0081] The HDMI signal output module 4 is used to acquire the timing-reformed HDMI signal and output it to the display terminal to produce an irregular display effect.
[0082] Please refer to Figure 5 , Figure 5 The schematic diagram of an impedance adjustment module 2 provided in this application.
[0083] In a preferred embodiment, the impedance adjustment module 2 includes a first impedance adjustment unit 21, a second impedance adjustment unit 22, a third impedance adjustment unit 23, and a fourth impedance adjustment unit 24;
[0084] The first impedance adjustment unit 21 is electrically connected to the HDMI signal input module 1 and the FPGA processing module 3 respectively; the second impedance adjustment unit 22 is electrically connected to the HDMI signal input module 1 and the FPGA processing module 3 respectively; the third impedance adjustment unit 23 is electrically connected to the HDMI signal input module 1 and the FPGA processing module 3 respectively; and the fourth impedance adjustment unit 24 is electrically connected to the HDMI signal input module 1 and the FPGA processing module 3 respectively.
[0085] In a preferred embodiment, the first impedance adjustment unit 21 includes a first sliding rheostat R1 and a second sliding rheostat R2;
[0086] The first end of the first sliding rheostat R1 is electrically connected to the HDMI signal input module 1, the second end of the first sliding rheostat R1 is left floating, and the third end of the first sliding rheostat R1 is electrically connected to the FPGA processing module 3. The first end of the second sliding rheostat R2 is electrically connected to the HDMI signal input module 1, the second end of the second sliding rheostat R2 is left floating, and the third end of the second sliding rheostat R2 is electrically connected to the FPGA processing module 3.
[0087] In a preferred embodiment, the second impedance adjustment unit 22 includes a third sliding rheostat R3 and a fourth sliding rheostat R4;
[0088] The first end of the third sliding rheostat R3 is electrically connected to the HDMI signal input module 1, the second end of the third sliding rheostat R3 is left floating, and the third end of the third sliding rheostat R3 is electrically connected to the FPGA processing module 4. The first end of the fourth sliding rheostat R4 is electrically connected to the HDMI signal input module 1, the second end of the fourth sliding rheostat R4 is left floating, and the third end of the fourth sliding rheostat R4 is electrically connected to the FPGA processing module 3.
[0089] In a preferred embodiment, the third impedance adjustment unit 23 includes a fifth sliding rheostat R5 and a sixth sliding rheostat R6;
[0090] The first end of the fifth sliding rheostat R5 is electrically connected to the HDMI signal input module, the second end of the fifth sliding rheostat R5 is left floating, and the third end of the fifth sliding rheostat R5 is electrically connected to the FPGA processing module 3. The first end of the sixth sliding rheostat R6 is electrically connected to the HDMI signal input module 1, the second end of the sixth sliding rheostat R6 is left floating, and the third end of the sixth sliding rheostat R6 is electrically connected to the FPGA processing module 3.
[0091] In a preferred embodiment, the fourth impedance adjustment unit 24 includes a seventh sliding rheostat R7 and an eighth sliding rheostat R8;
[0092] The first end of the seventh sliding rheostat R7 is electrically connected to the HDMI signal input module, the second end of the seventh sliding rheostat R7 is left floating, and the third end of the seventh sliding rheostat R7 is electrically connected to the FPGA processing module. The first end of the eighth sliding rheostat R8 is electrically connected to the HDMI signal input module, the second end of the eighth sliding rheostat R8 is left floating, and the third end of the eighth sliding rheostat R8 is electrically connected to the FPGA processing module 3.
[0093] In addition, combined Figure 1 The irregular display effect display control method described in this embodiment of the invention can be implemented by an irregular display effect display control device. Figure 6 A schematic diagram of the hardware structure of the irregular display effect control device provided in an embodiment of the present invention is shown.
[0094] The irregular display effect display control device may include a processor 401 and a memory 402 storing computer program instructions.
[0095] Specifically, the processor 401 may include a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of the present invention.
[0096] Memory 402 may include mass storage for data or instructions. For example, and not limitingly, memory 402 may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be internal or external to a data processing device. In a particular embodiment, memory 402 is a non-volatile solid-state memory. In a particular embodiment, memory 402 includes read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically rewritable ROM (EAROM), or flash memory, or a combination of two or more of these.
[0097] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement any of the irregular display effect display control methods in the above embodiments.
[0098] In one example, the irregular display effect control device may further include a communication interface 403 and a bus 410. For example, Figure 6 As shown, the processor 401, memory 402, and communication interface 403 are connected through bus 410 and complete communication with each other.
[0099] The communication interface 403 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of the present invention.
[0100] Bus 410 includes hardware, software, or both, that couples components of an irregular display effect control device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 410 may include one or more buses. While specific buses are described and illustrated in embodiments of the invention, the invention contemplates any suitable bus or interconnect.
[0101] Furthermore, in conjunction with the irregular display effect display control method in the above embodiments, this invention can be implemented using a computer-readable storage medium. This computer-readable storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the irregular display effect display control methods in the above embodiments.
[0102] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.
[0103] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.
Claims
1. A method for controlling irregular display effects, characterized in that, The method is applied to an irregular display effect display control device, which includes an HDMI signal input module, an impedance adjustment module, an FPGA processing module, and an HDMI signal output module, wherein the HDMI signal input module, the impedance adjustment module, the FPGA processing module, and the HDMI signal output module are connected sequentially, and the method includes: Receives HDMI signals with the first output timing set according to the CTA-861-G video standard; Based on a preset impedance change value, the output timing of the HDMI signal is disrupted; Receive the HDMI signal after its timing is corrupted, and perform timing restoration on the HDMI signal; The timing-reformed HDMI signal is acquired and output to the display terminal to produce an irregular display effect; The timing restoration of the HDMI signal after receiving the output timing is disrupted includes: Receive the HDMI signal after the output timing is corrupted, and perform a first-level buffering on the HDMI signal; Read the HDMI signal from the first-level cache and scale the HDMI signal. The scaled HDMI signal is then buffered at a second level. Obtain user instructions and adjust the second output timing of the HDMI signal according to the user instructions; The second output timing is output through the internal phase-locked loop of the FPGA processing module according to a preset clock.
2. The irregular display effect display control method according to claim 1, characterized in that, The reception of the HDMI signal with the first output timing set according to the CTA-861-G video standard includes: The HDMI signals include a first HDMI signal TMDS data0, a second HDMI signal TMDS data1, a third HDMI signal TMDS data2, and a fourth HDMI signal TMDS clk.
3. The irregular display effect display control method according to claim 1, characterized in that, The irregular display effect display control method further includes; In the second-level buffer, the frame rate of the HDMI signal is obtained according to a preset clock. Based on the frame rate of the HDMI signal, the HDMI signal is subjected to variable detection processing to adapt to the input / output processing rate.
4. The irregular display effect display control method according to claim 1, characterized in that, The step of reading the HDMI signal from the first-level cache and scaling the HDMI signal includes: The scaling algorithm is implemented using the LANCZOS algorithm.
5. An irregular display effect display control device, characterized in that, The device includes: An HDMI signal input module is used to receive HDMI signals with the first output timing set according to the CTA-861-G video standard. An impedance adjustment module is used to disrupt the output timing of the HDMI signal based on a preset impedance change value. The FPGA processing module is used to receive the HDMI signal after its timing has been corrupted and to perform timing restoration on the HDMI signal; specifically, it includes: Receive the HDMI signal after the output timing is corrupted, and perform a first-level buffering on the HDMI signal; Read the HDMI signal from the first-level cache and scale the HDMI signal. The scaled HDMI signal is then buffered at a second level. Obtain user instructions and adjust the second output timing of the HDMI signal according to the user instructions; The second output timing is output through the internal phase-locked loop of the FPGA processing module according to a preset clock. An HDMI signal output module is used to acquire the timing-reformed HDMI signal and output it to a display terminal to produce an irregular display effect.
6. The irregular display effect display control device according to claim 5, characterized in that, The impedance adjustment module includes a first impedance adjustment unit, a second impedance adjustment unit, a third impedance adjustment unit, and a fourth impedance adjustment unit; The first impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; the second impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; the third impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively; and the fourth impedance adjustment unit is electrically connected to the HDMI signal input module and the FPGA processing module respectively.
7. The irregular display effect display control device according to claim 6, characterized in that, The first impedance adjustment unit includes a first sliding rheostat and a second sliding rheostat; The first end of the first sliding rheostat is electrically connected to the HDMI signal input module, the second end of the first sliding rheostat is left floating, and the third end of the first sliding rheostat is electrically connected to the FPGA processing module. The first end of the second sliding rheostat is electrically connected to the HDMI signal input module, the second end of the second sliding rheostat is left floating, and the third end of the second sliding rheostat is electrically connected to the FPGA processing module.
8. An irregular display effect display control device, characterized in that, include: At least one processor, at least one memory, and computer program instructions stored in the memory, which, when executed by the processor, implement the method as described in any one of claims 1-4.
9. A storage medium storing computer program instructions thereon, characterized in that, The method as described in any one of claims 1-4 is implemented when the computer program instructions are executed by the processor.