Integrated circuit with contact jumper

Abstract

An integrated circuit is disclosed. The integrated circuit includes a first active region and a second active region extending along a first direction, a first gate line extending along a second direction substantially perpendicular to the first direction and crossing the first active region and the second active region, and a first conductive pattern intersecting the first gate line above the first active region, and a first contact jumper line including a second conductive pattern extending along the second direction above the first gate line and connected to the first conductive pattern.

Description

[0001] This application is a divisional application of invention patent application No. 201810131037.6 entitled "Integrated Circuit with Contact Jumper", filed on February 8, 2018.

[0002] Priority Statement

[0003] This application claims priority to Korean Patent Application No. 10-2017-0017676, filed with the Korean Intellectual Property Office on February 8, 2017, and Korean Patent Application No. 10-2017-0081831, filed with the Korean Intellectual Property Office on June 28, 2017, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The present invention relates to integrated circuits, and more particularly to standard cells, a standard cell library including standard cells, integrated circuits, and computer implementation methods and computing systems for designing integrated circuits. Background Technology

[0005] Integrated circuits can be designed based on standard cells. Specifically, the layout of an integrated circuit can be generated by arranging and routing the standard cells that define the standard cells (the standard cell "layout"). As the design rules of semiconductor processes become smaller, aspects of the layout, such as pattern size, can become smaller to meet the design rules. Specifically, in examples of integrated circuits including fins such as FinFETs, the pitch of the fins may have to be reduced, which in turn results in a smaller footprint for the active regions in the standard cells. Therefore, the "height" of the standard cells (the size of the standard cells in the layout) can be reduced. Summary of the Invention

[0006] According to one aspect of the present invention, an integrated circuit is provided, comprising: a first active region and a second active region, both extending along a first direction; a first gate line extending longitudinally across the first active region and the second active region along a second direction substantially perpendicular to the first direction; and a first contact jumper including a first conductive pattern crossing the first gate line above the first active region and a second conductive pattern extending longitudinally along the second direction above the first gate line and connected to the first conductive pattern.

[0007] According to another aspect of the present invention, an integrated circuit is provided, comprising: a first active region and a second active region, both extending along a first direction; a first gate line and a second gate line spaced apart from each other along the first direction, each of the first gate line and the second gate line extending longitudinally across the first active region and the second active region along a second direction substantially perpendicular to the first direction; and a first contact jumper including a first conductive pattern crossing the first gate line and the second gate line above the first active region and a second conductive pattern extending longitudinally between the first gate line and the second gate line along the second direction and connected to the first conductive pattern when viewed in a top view of the integrated circuit.

[0008] According to another aspect of the present invention, an integrated circuit is provided, comprising: a first active region and a second active region extending along a first direction and spaced apart along a second direction substantially perpendicular to the first direction, such that an intermediate region exists along the second direction between the first active region and the second active region; a first gate line and a second gate line spaced apart from each other along the first direction, each of the first gate line and the second gate line extending longitudinally along the second direction across the first active region and the second active region and the intermediate region; a contact jumper including a first conductive pattern crossing the first gate line above the first active region and a second conductive pattern extending longitudinally along the second direction above the first gate line and connected to the first conductive pattern; a first via and a second via aligned with each other along the first direction in the intermediate region between the first and second active regions, the first via disposed on the second conductive pattern and the second via located above the second gate line; and a first metal layer including a first metal pattern extending along the first direction above the first active region, a second metal pattern extending along the first direction above the second active region, and a plurality of third metal patterns extending along the second direction in the intermediate region and respectively disposed on the first via and the second via.

[0009] According to another aspect of the present invention, an integrated circuit is provided, comprising: a substrate having a first active region and a second active region, both extending along a first direction and spaced apart along a second direction substantially perpendicular to the first direction; and an intermediate region situated between the first and second active regions along the second direction, with gate lines spaced apart from each other along the first direction, each of the gate lines extending longitudinally across the first and second active regions and the intermediate region along the second direction; and a contact layer on the substrate and having an upper surface substantially coplanar at a horizontal plane above the substrate, the contact layer including contact jumpers, the contact jumpers including those extending along the first direction and in the first active region of the substrate. The via layer comprises a first conductive pattern extending over at least one of the gate lines along the first direction and a second conductive pattern extending longitudinally from the first conductive pattern over at least a portion of the intermediate region of the substrate along the second direction, a via layer on the contact layer, each of the vias extending on the upper surface of a corresponding one of the contacts, and the via layer comprising a plurality of vias disposed over the intermediate region of the substrate and aligned with each other along the first direction, and a first metallization layer on the via layer, wherein only one metal trace in the first metallization layer extends over the first active region, only one metal trace in the first metallization layer extends over the second active region, and each metal trace extends over the gate line along the first direction. Attached Figure Description

[0010] The inventive concept will be more clearly understood from the following detailed description of examples of the inventive concept, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 The first and second standard units with different heights are shown;

[0012] Figure 2A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0013] Figure 2B This is a plan view of another example of an integrated circuit based on the concept of the present invention;

[0014] Figure 3 It is along Figure 2A The lines X1a-X1a′ and X1b-X1b′ in the middle intercept the Figure 2A Cross-sectional views of the various parts of an integrated circuit;

[0015] Figure 4 This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0016] Figure 5 It is along Figure 4 Cross-sectional views taken from lines X2a-X2a′ and X2b-X2b′ in the diagram;

[0017] Figure 6 This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0018] Figure 7 It is along Figure 6 Cross-sectional views taken from lines X3a-X3a′ and X3b-X3b′ in the diagram;

[0019] Figure 8 This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0020] Figure 9 It is along Figure 8 Cross-sectional views taken from lines X4a-X4a′ and X4b-X4b′ in the diagram;

[0021] Figure 10 yes Figure 8 A perspective view of an integrated circuit;

[0022] Figure 11 This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0023] Figure 12 It is along Figure 11 The cross-sectional view taken by lines X5a-X5a′ and X5b-X5b′ in the diagram.

[0024] Figure 13 , 14 15, 16, 17, 18 and 19 are plan views of examples of integrated circuits conceived according to the present invention;

[0025] Figure 20A The symbol for an example of a standard cell is shown;

[0026] Figure 20B yes Figure 20A The circuit diagram of the standard unit;

[0027] Figure 21A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0028] Figure 21B Is with Figure 21A The example also includes a plan view of an integrated circuit with a first metal layer;

[0029] Figure 21C Is with Figure 21B The example also includes a plan view of an integrated circuit example with a second metal layer;

[0030] Figure 22 It is along Figure 21C Cross-sectional views taken from lines X6a-X6a′ and X6b-X6b′ in the diagram;

[0031] Figure 23A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0032] Figure 23B This is a plan view of an example of an integrated circuit based on the concept of the present invention.

[0033] Figure 24A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0034] Figure 24B It is based on the concept of the present invention and Figure 24A The example is a plan view compared to an example of an integrated circuit that includes a first metal layer.

[0035] Figure 24C It is based on the concept of the present invention and Figure 24B The example also includes a plan view of an integrated circuit example with a second metal layer;

[0036] Figure 25 It is along Figure 24C Cross-sectional views taken from lines X7a-X7a′ and X7b-X7b′ in the diagram;

[0037] Figure 26A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0038] Figure 26B It is based on the concept of the present invention and Figure 26A The example also includes a plan view of an integrated circuit with a first metal layer;

[0039] Figure 26C It is based on the concept of the present invention and Figure 26B The example also includes a plan view of an integrated circuit example with a second metal layer;

[0040] Figure 27 It is along Figure 26C Cross-sectional views taken from lines X8a-X8a′ and X8b-X8b′ in the diagram;

[0041] Figure 28A The symbol for the adder is shown;

[0042] Figure 28B It is a logic circuit diagram that includes an adder with standard units;

[0043] Figure 29A This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0044] Figure 29B It is based on the concept of the present invention and Figure 29A The example also includes a plan view of an integrated circuit with a first metal layer;

[0045] Figure 29C It is based on the concept of the present invention and Figure 29B The example also includes a plan view of an integrated circuit example with a second metal layer;

[0046] Figure 30 This is a plan view of an example of an integrated circuit based on the concept of the present invention;

[0047] Figure 31 This is a block diagram of a storage medium that may include an integrated circuit, according to the present invention.

[0048] Figure 32 This is a flowchart illustrating an example of a method for manufacturing a semiconductor device according to a concept conceived in this invention; and

[0049] Figure 33 This is a block diagram of an integrated circuit design system configured to design integrated circuits according to the present invention. Detailed Implementation

[0050] Figure 1 The first standard unit and the second standard unit SC1 and SC2, which have different heights, are shown.

[0051] refer to Figure 1 The first standard cell SC1 has a first height H, and the second standard cell SC2 has a second height H′, where the second height H′ is smaller than the first height H. Therefore, the term "height" refers to the size of the laid-out standard cells, that is, the size in the layout of the standard cells or the size seen in the planar view of the cells in the integrated circuit. The first height H and the second height H′ can be determined, respectively, based on the number of traces (hereinafter referred to as "trace count") above the first standard cell SC1 and the second standard cell SC2. Here, the traces are conductive lines extending along a first direction (e.g., the X direction) and arranged parallel to each other, and the traces can correspond to, for example, discrete metal line patterns of a metal layer in a semiconductor device. The metal patterns of the metal layer can constitute a so-called metallization layer.

[0052] Each of the first standard unit and the second standard units SC1 and SC2 may include a first power region and a second power region PWR1 and PWR2 to which a power supply voltage and a ground voltage are respectively applied, a first active region and a second active region AR1 and AR2, and an intermediate region MR. The first height H of the first standard unit SC1 may correspond to the sum of the heights H1 to H5 of the aforementioned regions of unit SC1 (i.e., H = H1 + H2 + H3 + H4 + H5) (described in more detail later), and the second height H′ of the second standard unit SC2 may correspond to the sum of the heights H1′ to H5′ of the aforementioned regions of unit SC2 (i.e., H′ = H1′ + H2′ + H3′ + H4′ + H5′).

[0053] Active fins AF extending along a first direction and parallel to each other are arranged in the first active region and the second active regions AR1 and AR2, and fins DF extending along the first direction and parallel to each other are arranged in the intermediate region MR. Recent developments in semiconductor process technology have allowed for a gradual reduction in fin pitch. Therefore, regarding the size of a standard cell placed in the layout of an integrated circuit, the height of the first active region AR1 gradually decreases from H2 to H2′, for example, and the height of the second active region AR2 gradually decreases from H4 to H4′, for example. That is, it is now possible to implement a standard cell with a relatively small height, like the second standard cell SC2, in terms of designing the layout of an integrated circuit.

[0054] When scaling down from a standard cell with a relatively large height to a relatively small height, for example, when implementing a standard cell SC2 instead of a standard cell SC1, the reduction in metal pitch (the pitch of the metal traces) is relatively small compared to the reduction in fin pitch. For example, two traces MTa and MTb can be arranged above the first active region AR1 of the first standard cell SC1. On the other hand, if the same two traces MTa and MTb are arranged above the first active region AR1 of the second standard cell SC2, the lower trace MTb of the two traces MTa and MTb can be outside the first active region AR1. Here, the term "lower" can refer to a trace closer to the origin of the XY coordinate system, where the origin is located at the "bottom" of the standard cell, and the Y-axis travels in the height direction of the cell. As a result, the lower trace MTb may affect the position of contacts or vias arranged in the middle region MR of the second standard cell SC2, i.e., the design freedom of the metal pattern generated by the wiring process is smaller.

[0055] Figure 2A The layout of an example of an integrated circuit 10 conceived according to the present invention is shown.

[0056] refer to Figure 2A Integrated circuit 10 may include a first active region and second active regions AR1 and AR2, multiple gate lines GL, a first contact jumper CJ1, and a via V0. Here, a "contact jumper" refers to a relatively short conductor connecting any two points or terminals in integrated circuit 10, and can also be simply referred to as a "jump wire". Integrated circuit 10 can be designed using a standard cell library, and the first active region and second active regions AR1 and AR2, multiple gate lines GL, and the first contact jumper CJ1 can be standard cells (e.g., corresponding to...). Figure 1 The second standard unit (SC2) in the text.

[0057] The first active region AR1 and the second active region AR2 may extend along a first direction (e.g., they may extend along a first direction corresponding to the X direction in the figure) and may be arranged parallel to each other. The first active region AR1 and the second active region AR2 may be spaced apart from each other along a second direction substantially perpendicular to the first direction (e.g., the Y direction) and may have different conductivity types. The first active region AR1 and the second active region AR2 may be referred to as diffusion regions. The region between the first active region AR1 and the second active region AR2 along the second direction may be defined as an intermediate region MR. The intermediate region MR may be referred to as a dummy region or line intermediate (MOL) region. Active fins extending along the first direction (e.g., Figure 1 The active fins (AF) of the standard unit SC2 in the standard unit SC2 can be arranged in the first active region AR1 and the second active region AR2, and the dummy fins (e.g., the standard unit SC2) extending along the first direction Figure 1 The virtual fin (DF) in the middle region (MR) can be arranged.

[0058] Multiple gate lines GL may include a first gate line GL1 and a second gate line GL2. Each gate line GL may extend along a second direction and may cross a first active region AR1 and a second active region AR2. Additionally, the gate lines GL may be spaced apart from each other at regular intervals along a first direction. In this case, the multiple gate lines GL may correspond to the gate electrodes of a semiconductor device. A first contact jumper CJ1 above the first gate line GL1 will be described in detail below. However, the inventive concept is not limited thereto, and the first contact jumper CJ1 may be arranged above any conductive trace to achieve a skip device. Moreover, the term "above" refers to the direction perpendicular to the Z direction, which is perpendicular to the X and Y directions in the figure, when implemented in the integrated circuit 10. Therefore, when one element is "above" another element, the layout diagram shows the elements as stacked.

[0059] The first contact jumper CJ1 may include a first conductive pattern PT1 and a second conductive pattern PT2 connected to each other. The first conductive pattern PT1 may extend along a first direction, and the second conductive pattern PT2 may extend along a second direction. Specifically, the first conductive pattern PT1 may cross the first gate line GL1 over the first active region AR1, and the second conductive pattern PT2 may extend over the first gate line GL1 along the second direction and be connected to the first conductive pattern PT1. In this way, the first contact jumper CJ1 may have a T-shape, and accordingly, the first contact jumper CJ1 may be referred to as a T-shaped jumper. Note that in the preceding and following description, and as the context will become clear, the term "extend" generally refers to the longitudinal or elongated direction of an element or feature, particularly when the element or feature is a line element or feature.

[0060] If the second conductive pattern PT2 is arranged between the first gate line GL1 and the second gate line GL2, such that the first contact bridge CJ1 has an L-shape, then the gate contact to be arranged on the second gate line GL2 can interfere with the first contact bridge CJ1. As a result, this may complicate the shape and position of the gate contacts, vias, and metal patterns to be arranged in the intermediate region MR, and therefore the height of the intermediate region MR along the second direction may need to be increased. Therefore, despite reducing the fin pitch, it may be difficult to keep the height of the standard cell to a minimum.

[0061] However, according to this example, because the second conductive pattern PT2 is disposed above the first gate line GL1 and the first contact bridge CJ1 has a T-shape, the interference between the first contact bridge CJ1 and the gate contact to be disposed on the second gate line CJ2 can be reduced. Therefore, the gate contacts, vias, and metal patterns in the intermediate region MR can be easily formed (i.e., easy to lay out) and the shape of the gate contacts, vias, and metal patterns aligned with each other can be achieved. As a result, an increase in the height of the intermediate region MR along the second direction can be prevented. Therefore, as the fin pitch decreases, the height of the standard cell can be reduced, and the overall size of the integrated circuit 10 including the standard cell can be reduced.

[0062] The first conductive pattern PT1 can electrically connect the regions on both sides of the first gate line GL1 in the first active region AR1. Therefore, the first gate line GL1 can be a dummy gate line, i.e., a skipped gate line that is not an actual gate line. However, the location of the first contact jumper CJ1 according to this example is not limited to the region above the first active region AR1 and the intermediate region MR. Reference will be made below. Figure 2B Describe a modified example of the first contact jumper CJ1.

[0063] Figure 2B The layout of integrated circuit 10′ according to another example is shown.

[0064] refer to Figure 2BThe integrated circuit 10' may include a first active region and second active regions AR1 and AR2, a plurality of gate lines GL, and a first contact bridge CJ1a. The first contact bridge CJ1a may include a first conductive pattern PT1a and a second conductive pattern PT2a connected to each other. The first conductive pattern PT1a may extend along a first direction (e.g., the X direction), and the second conductive pattern PT2a may extend along a second direction (e.g., the Y direction). Specifically, the first conductive pattern PT1a may cross the first gate line GL1 over the second active region AR2, and the second conductive pattern PT2a may extend over the first gate line GL1 along the second direction and connect to the first conductive pattern PT1a. In this way, the first contact bridge CJ1a may have an inverted T shape. The first conductive pattern PT1a of the first contact bridge CJ1a may electrically connect the regions on both sides of the first gate line GL1 in the second active region AR2. Therefore, the first gate line GL1 may be a dummy gate line.

[0065] Return to reference Figure 2A The via V0 can be disposed on the second conductive pattern PT2 of the first contact jumper CJ1. In one example, the via V0 can be disposed on the second conductive pattern PT2 in the intermediate region MR. Therefore, the wiring interconnects to be disposed on the via V0 (e.g., the first metal layer (e.g., ...) Figure 21B The metal layer M1 can be disposed above the intermediate region MR instead of the first active region AR1. However, the location of the via V0 is not limited to the intermediate region MR, and in some examples, the via V0 can be disposed on the second conductive pattern PT2 in the first active region AR1 or the second active region AR2, depending on the length of the second conductive pattern PT2.

[0066] In one example, the first contact jumper CJ1 can be formed using a single mask. For instance, the first contact jumper CJ1 can be formed using a mask used to form active contacts such as source / drain contacts. As another example, the first contact jumper CJ1 can be formed using a mask used to form gate contacts. Reference will be made below. Figure 3 Describe an example of forming the first contact jumper CJ1 using a single mask.

[0067] Figure 3 It is along Figure 2A The cross-sectional view taken by lines X1a-X1a′ and X1b-X1b′ in the diagram.

[0068] refer to Figure 3 Integrated circuit 10 can be based on Figure 2AThis is an example of an integrated circuit device (i.e., a semiconductor device) manufactured using this layout. In this example, the first conductive pattern PT1 and the second conductive pattern PT2 of the first contact jumper CJ1 can be implemented as the first contact CA. The first contact CA can also be referred to as an active contact.

[0069] The substrate SUB can be a semiconductor substrate, and for example, it can include silicon, silicon-on-insulator (SOI), silicon-on-sapphire, germanium, silicon-germanium, or gallium arsenide. The substrate SUB can include a first active region AR1, a second active region AR2, and an intermediate region MR. For example, shallow trench isolation (STI) can be arranged in the substrate SUB to separate the intermediate region MR from the first active region AR1 and the second active region AR2.

[0070] Multiple gate insulating films GI and multiple gate lines GL can extend on a substrate SUB along a second direction (e.g., the Y direction). The multiple gate insulating films GI can include silicon oxide films, high-k films, or combinations thereof. The multiple gate lines GL can include metallic materials such as tungsten (W), tantalum (Ta), cobalt (Co), or copper (Cu), their nitrides, their silicides, and doped polysilicon, and can be formed, for example, using a deposition process. The upper surface and two sidewall surfaces of each gate line GL are covered by insulating spacers SP. The insulating spacers SP can extend parallel to the gate lines GL in the second direction. The insulating spacers SP can include silicon nitride films, SiOCN films, SiCN films, or combinations thereof. The gate insulating films GI, gate lines GL, and insulating spacers SP can constitute a gate structure GS.

[0071] The first contact CA can be formed on a substrate SUB on which the gate structure GS is formed. The first contact CA can span the first gate line GL1 in the first active region AR1 and can be disposed above the first gate line GL1 in the intermediate region MR. The first contact CA can include any conductive material, such as tungsten. A via V0 can be disposed on the first contact CA, which is disposed above the first gate line GL1 in the intermediate region MR.

[0072] Figure 4 The layout of integrated circuit 10a according to the example is shown, and Figure 5 It is along Figure 4 The cross-sectional view taken by lines X2a-X2a′ and X2b-X2b′ in the diagram.

[0073] refer to Figure 4 and Figure 5The first conductive pattern PT1 of the first contact jumper CJ1 can be implemented as the first contact CA, and the second conductive pattern PT2 of the first contact jumper CJ1 can be implemented as the second contact CB. Therefore, the first contact jumper CJ1 can be formed using a first mask for the first contact CA and a second mask for the second contact CB.

[0074] In one example, the first contact CA can correspond to an active contact such as a source / drain contact, and the second contact CB can correspond to a gate contact. In this case, the first contact CA and the second contact CB can overlap each other in some regions. The upper surface horizontal planes of the first contact CA and the second contact CB can be substantially equal to each other. The lower surface horizontal plane of the first contact CA can be equal to the upper surface horizontal plane of the substrate SUB, and the lower surface horizontal plane of the second contact CB can be lower than the upper surface horizontal plane of the gate structure GS, so that the second contact CB can be connected to the first gate line GL1.

[0075] Figure 6 The layout of integrated circuit 10b according to the example is shown, while Figure 7 It is along Figure 6 The cross-sectional view taken by lines X3a-X3a′ and X3b-X3b′ in the diagram.

[0076] refer to Figure 6 and 7 Integrated circuit 10b and Figure 4 The integrated circuit 10a shown is similar, but also includes trench silicides TS. The trench silicides TS can be disposed between two adjacent gate lines GL in the first active region AR1. The trench silicides TS can extend along a second direction (e.g., the Y direction), and the length of the trench silicides TS along the second direction can be substantially equal to the length of the first active region AR1 along the second direction. Each trench silicide TS can include a conductive material such as tungsten (W), cobalt (Co), or copper (Cu).

[0077] In one example, the height of the trench silicide TS along a third direction (e.g., the Z direction) can be greater than the height of the gate structure GS along a third direction. A first contact CA can be disposed on the trench silicide TS. Therefore, the first contact CA may not be connected to the gate structure GS.

[0078] Figure 8 The layout of integrated circuit 10c according to the example is shown. Figure 9 It is along Figure 8 The cross-sectional views taken by lines X4a-X4a′ and X4b-X4b′ in the diagram, and Figure 10 yes Figure 8 A perspective view of an integrated circuit.

[0079] refer to Figures 8 to 10 The integrated circuit 10c is similar to Figure 2A The integrated circuit 10 shown is different from the one shown. Figure 2A The integrated circuit 10 includes a first contact CA. The first contact CA can be disposed between two adjacent gate lines GL in the first active region AR1. The first contact CA can extend along a second direction (e.g., the Y direction), and the length of the first contact CA along the second direction can be substantially equal to the length of the first active region AR1 along the second direction. The height of the first contact CA along a third direction (e.g., the Z direction) can be greater than the height of the gate structure GS along the third direction. An interlayer dielectric layer ILD can be disposed above the gate structure GS. The interlayer dielectric layer ILD can include an insulating material, such as an oxide, nitride, or oxynitride.

[0080] Furthermore, the first conductive pattern PT1 and the second conductive pattern PT2 of the first contact jumper CJ1 can be implemented as a third contact CM. For example, the third contact CM can correspond to a merged contact and can merge the first contacts CA that are spaced apart from each other. The third contact CM can be disposed above the first contacts CA and the interlayer dielectric layer ILD. Therefore, the distance from the substrate SUB to the lower surface of the third contact CM can be greater than the height of the gate structure GS along the third direction, thereby ensuring an insulating space between the third contact CM and the gate structure GS (especially the gate line GL). A via V0 can be disposed on the third contact CM in the intermediate region MR.

[0081] Figure 11 The layout of integrated circuit 10d according to the example is shown, while Figure 12 It is along Figure 11 The cross-sectional view taken by lines X5a-X5a′ and X5b-X5b′ in the diagram.

[0082] refer to Figure 11 and 12 Integrated circuit 10d is similar to Figure 8 The example of integrated circuit 10c shown also includes a trench silicide TS. The trench silicide TS can be disposed between two adjacent gate lines GL in the first active region AR1. The trench silicide TS can extend along a second direction (e.g., the Y direction), and the length of the trench silicide TS along the second direction can be substantially equal to the length of the first active region AR1 along the second direction. Additionally, the first contact CA can be shorter than the trench silicide TS in the second direction.

[0083] Figure 13 The layout of an integrated circuit 20 according to an example is shown.

[0084] refer to Figure 13 Integrated circuit 20 is similar to Figure 2AAn example of integrated circuit 10, but including a second contact jumper CJ2. The second contact jumper CJ2 may extend along a first direction (e.g., the X direction) and cross the first gate line GL1 over the second active region AR2. In this case, the second contact jumper CJ2 is separated from the first contact jumper CJ1. The first contact jumper CJ1 and the second contact jumper CJ2 may be in any form and use the reference above. Figures 2A to 12 Any of the corresponding technologies described can be implemented.

[0085] In one example, the first contact jumper and the second contact jumpers CJ1 and CJ2 can be implemented using three masks. For example, the first contact jumper CJ1 can be formed by the first contact CA and the third contact CM, and the second contact jumper CJ2 can be formed by the second contact CB. In another example, the first contact jumper CJ1 and the second contact jumper CJ2 can be implemented using two masks. For example, the first contact jumper CJ1 can be formed by the first contact CA, and the second contact jumper CJ2 can be formed by the second contact CB. In yet another example, the first contact jumper CJ1 and the second contact jumper CJ2 can be implemented using a single mask. For example, the first contact jumper CJ1 and the second contact jumper CJ2 can be formed by the first contact CA.

[0086] Figure 14 The layout of an integrated circuit 30 according to an example is shown.

[0087] refer to Figure 14 Integrated circuit 30 is similar to Figure 13 An example of integrated circuit 20 is provided, but in this example, the lengths of the first contact jumper CJ1 and the second contact jumper CJ2' along the first direction (e.g., the X direction) are different from each other. The second contact jumper CJ2' may extend along the first direction and cross the first gate line GL1 and the second gate line GL2 over the second active region AR2. In this way, the length of the second contact jumper CJ2' along the first direction is greater than... Figure 13 The length of the second contact jumper CJ2 along the first direction. The inventive concept is not limited thereto; in some examples, the length of the second contact jumper CJ2′ along the first direction can extend further than in the example shown, that is, the second contact jumper CJ2′ can span three or more gate lines GL.

[0088] Figure 15 The layout of an integrated circuit 40 according to an example is shown.

[0089] refer to Figure 15 Integrated circuit 40 is similar to Figure 13An example of integrated circuit 20, but the lengths of the first contact jumper CJ1′ and the second contact jumper CJ2 along the first direction (e.g., the X direction) are different from each other. The first conductive pattern PT1′ of the first contact jumper CJ1′ may extend along the first direction and cross the first gate line GL1 and the second gate line GL2 over the first active region AR1. In this way, the length of the first conductive pattern PT1′ of the first contact jumper CJ1′ along the first direction is greater than... Figure 13 The length of the first conductive pattern PT1 of the first contact jumper CJ1 along the first direction. However, the inventive concept is not limited thereto. In some examples, the length of the first conductive pattern PT1' of the first contact jumper CJ1' along the first direction can extend further than in the illustrated example, that is, the first contact jumper CJ1' can span three or more gate lines GL.

[0090] Figure 16 The layout of an integrated circuit 50 according to an example is shown.

[0091] refer to Figure 16 The integrated circuit 50 may include a first active region and second active regions AR1 and AR2, a plurality of gate lines GL, and a third contact jumper CJ3. The third contact jumper CJ3 may include first to third conductive patterns PT1, PT2', and PT3 connected to each other. The first conductive pattern PT1 and the third conductive pattern PT3 may extend along a first direction (e.g., the X direction), and the second conductive pattern PT2' may extend along a second direction (e.g., the Y direction). Specifically, the first conductive pattern PT1 may cross the first gate line GL1 over the first active region AR1, the second conductive pattern PT2' may extend along the second direction over the first gate line GL1 and be connected to the first conductive pattern PT1, and the third conductive pattern PT3 may cross the first gate line GL1 over the second active region AR2. In this way, the third contact jumper CJ3 may have an I-shape or an H-shape.

[0092] The first conductive pattern PT1 can electrically connect the regions on both sides of the first gate line GL1 in the first active region AR1. The third conductive pattern PT3 can electrically connect the regions on both sides of the first gate line GL1 in the second active region AR2. In addition, the second conductive pattern PT2' can connect the first conductive pattern PT1 and the third conductive pattern PT3 to each other. Therefore, the first gate line GL1 can be a dummy gate line, that is, a skipped gate line as a non-actual gate line (i.e., it is inactive in integrated circuit 50).

[0093] In one example, three masks can be used to implement the first to third conductive patterns PT1, PT2′, and PT3. For example, the first to third conductive patterns PT1, PT2′, and PT3 can be implemented as a first contact CA, a second contact CB, and a third contact CM, respectively. In one example, the first to third conductive patterns PT1, PT2′, and PT3 can be implemented using two masks. For example, the first to third conductive patterns PT1, PT2′, and PT3 can be implemented as a first contact CA and a third contact CM. In one example, the first to third conductive patterns PT1, PT2′, and PT3 can be implemented using a single mask. For example, the first to third conductive patterns PT1, PT2′, and PT3 can be implemented as a first contact CA or a second contact CB.

[0094] Figure 17 The layout of an integrated circuit 60 according to an example is shown.

[0095] refer to Figure 17 Integrated circuit 60 is similar to Figure 16 An example of integrated circuit 50. However, in this example, the third conductive pattern PT3' of the third contact jumper CJ3' may extend along a first direction (e.g., the X direction) and cross the first gate line GL1 and the second gate line GL2 over the second active region AR2. In this way, the length of the third conductive pattern PT3' of the third contact jumper CJ3' along the first direction is greater than... Figure 16 The length of the third conductive pattern PT3 of the third contact jumper CJ3 along the first direction. The inventive concept is not limited thereto. In some examples, the length of the third conductive pattern PT3' of the third contact jumper CJ3' along the first direction can be much longer than in the illustrated example. That is, the third contact jumper CJ3' can span three or more gate lines GL.

[0096] Figure 18 The layout of an integrated circuit 70 according to an example is shown.

[0097] refer to Figure 18 Integrated circuit 70 is similar to Figure 14 An example of integrated circuit 30, but including a first active region and second active regions AR1 and AR2, a plurality of gate lines GL, a fourth contact jumper CJ4 and a second contact jumper CJ2'. The fourth contact jumper CJ4 may include a first conductive pattern PT1' and a second conductive pattern PT2' connected to each other. The first conductive pattern PT1' may extend along a first direction (e.g., the X direction), and the second conductive pattern PT2' may extend along a second direction (e.g., the Y direction).

[0098] Specifically, the first conductive pattern PT1′ may span the first gate line and the second gate lines GL1 and GL2 over the first active region AR1, and the second conductive pattern PT2′ may extend along a second direction between the first gate line GL1 and the second gate line GL2 and may be connected to the first conductive pattern PT1′. In this way, the fourth contact jumper CJ4 may have a T-shape. In the first active region AR1, the first conductive pattern PT1′ of the fourth contact jumper CJ4 may electrically connect the region to the left of the first gate line GL1 to the region to the right of the second gate line GL2. Therefore, the first gate line and the second gate lines GL1 and GL2 in the PMOS region may be dummy gate lines, i.e., skipped gate lines that are not actual gate lines. In some examples, the first conductive pattern PT1′ may span three or more gate lines GL, and in this case, the second conductive pattern PT2′ may extend along a second direction over any one of the three or more gate lines GL or between the gate lines GL.

[0099] Additionally, the second contact jumper CJ2′ can cross the first gate line GL1 and the second gate line GL2 over the second active region AR2, and can be spaced apart from the fourth contact jumper CJ4. In the second active region AR2, the second contact jumper CJ2′ can electrically connect the region to the left of the first gate line GL1 to the region to the right of the second gate line GL2. Therefore, the first gate line and the second gate lines GL1 and GL2 in the NMOS region can be dummy gate lines, i.e., skipped gate lines that are not actual gate lines. In some examples, the second contact jumper CJ2′ can cross three or more gate lines GL.

[0100] Additionally, integrated circuit 70 may also include a via V0'. The via V0' may be disposed on the second conductive pattern PT2" of the fourth contact jumper CJ4. In one example, the via V0' may be disposed on the second conductive pattern PT2" in the intermediate region MR. Therefore, the wiring interconnect (e.g., the first metal layer) to be disposed on the via V0' may be disposed above the intermediate region MR rather than above the first active region AR1. However, the location of the via V0' is not limited to the intermediate region MR, and in some examples, the via V0 is disposed on the second conductive pattern PT2" in either the first active region AR1 or the second active region AR2, depending on the length of the second conductive pattern PT2".

[0101] Figure 19 The layout of an integrated circuit 80 according to an example is shown.

[0102] refer to Figure 19 Integrated circuit 80 is similar to Figure 16An example of an integrated circuit 50, but including first and second active regions AR1 and AR2, a plurality of gate lines GL, and a fifth contact jumper CJ5. The fifth contact jumper CJ5 may include first to third conductive patterns PT1′, PT2′″ and PT3′ connected to each other. The first conductive pattern and the third conductive patterns PT1′ and PT3′ may extend along a first direction (e.g., the X direction), and the second conductive pattern PT2″′ may extend along a second direction (e.g., the Y direction).

[0103] Specifically, the first conductive pattern PT1′ may cross the first gate line GL1 and the second gate line GL2 over the first active region AR1, and the third conductive pattern PT3′ may cross the first gate line GL1 and the second gate line GL2 over the second active region AR2. The second conductive pattern PT2′ may extend along a second direction between the first gate line GL1 and the second gate line GL2, and may be connected to the first conductive pattern PT1′ and the third conductive pattern PT3′. In this way, the fifth contact jumper CJ5 may have an I-shape or an H-shape.

[0104] In the first active region AR1, the first conductive pattern PT1′ of the fifth contact jumper CJ5 can electrically connect the region to the left of the first gate line GL1 to the region to the right of the second gate line GL2. In the second active region AR2, the third conductive pattern PT3′ of the fifth contact jumper CJ5 can electrically connect the region to the left of the first gate line GL1 to the region to the right of the second gate line GL2. Therefore, the first gate line GL1 and the second gate line GL2 can be dummy gate lines, that is, skipped gate lines that are not actual gate lines.

[0105] Additionally, integrated circuit 80 may also include a via V0'. The via V0' may be disposed on the second conductive pattern PT2"' of the fifth contact jumper CJ5. In one example, the via V0' may be disposed on the second conductive pattern PT2"' in the intermediate region MR. Therefore, the wiring interconnect (e.g., the first metal layer) to be disposed on the via V0' may be disposed above the intermediate region MR rather than above the first active region AR1 or the second active region AR2. However, the location of the via V0' is not limited to the intermediate region MR, and in some examples, the via V0 is disposed on the second conductive pattern PT2"' in the first active region AR1 or the second active region AR2.

[0106] Figure 20A The symbol for the standard unit SCa is shown according to an example, while Figure 20B yes Figure 20A The circuit diagram of the standard unit SCa.

[0107] refer to Figure 20AThe standard unit SCa can be an AOI22 unit, and can receive the first to fourth input signals A0, A1, B0, and B1 and output a single output signal Y. (Reference) Figure 20B The standard unit SCa may include first to fourth PMOS transistors PM1 to PM4 and first to fourth NMOS transistors NM1 to NM4.

[0108] The first PMOS transistor PM1 may include a gate to which a first input signal A0 is applied, and the second PMOS transistor PM2 may include a gate to which a second input signal A1 is applied. The third PMOS transistor PM3 may include a gate to which a third input signal B0 is applied, and the fourth PMOS transistor PM4 may include a gate to which a fourth input signal B1 is applied. In this case, the drain of the first PMOS transistor PM1, the drain of the second PMOS transistor PM2, the source of the third PMOS transistor PM3, and the source of the fourth PMOS transistor PM4 can be electrically connected via an input or an internal wiring pattern IRT in the PMOS region. In one example, the internal wiring pattern IRT can be utilized in the first active region (e.g., Figure 21B The horizontal metal pattern extending along a first direction (e.g., the X direction) in the active region AR1) of the active region (e.g., Figure 21B The first active region is achieved by using a metal pattern M1a, and the first to fourth PMOS transistors PM1 to PM4 are arranged in the first active region.

[0109] The first NMOS transistor NM1 may include a gate to which a first input signal A0 is applied, and the second NMOS transistor NM2 may include a gate to which a third input signal B0 is applied. The third NMOS transistor NM3 may include a gate to which a second input signal A1 is applied, and the fourth NMOS transistor NM4 may include a gate to which a fourth input signal B1 is applied. In this case, the drains of the third PMOS transistor PM3, the fourth PMOS transistor PM4, the first NMOS transistor NM1, and the second NMOS transistor NM2 can be electrically connected via the output wiring pattern ORT connecting the PMOS and NMOS regions.

[0110] In one example, the output wiring pattern ORT may include a T-shaped contact jumper disposed above the first active area (e.g., Figure 21A The contact jumper 110 in the middle), the contact arranged above the second active area, and the upper metal pattern connecting the T-shaped contact jumper and the contact (e.g., Figure 21B The metal pattern M1b in the diagram. Therefore, only one horizontal metal pattern can be arranged above the first active region. Reference will be made below. Figures 21A to 27The layout of an integrated circuit including the standard cell SCa is described. Specifically, various examples of T-shaped contact jumpers used to implement the output wiring pattern ORT of the standard cell SCa will be described.

[0111] Figure 21A The layout of an integrated circuit 100 according to an example is shown.

[0112] refer to Figure 21A The integrated circuit 100 may include components corresponding to Figure 20A and 20B The standard cell SCa_1 in the standard cell SCa is described above, and the standard cell SCa_1 may include a first active region and second active regions AR1 and AR2, a plurality of gate lines GL, and a contact layer including a first contact CA and a second contact CB. The first contact CA may be disposed between the gate lines GL in the first active region AR1 and the second active region AR2, respectively. The second contact CB may be disposed on the gate lines GL in the intermediate region MR, respectively. The upper surfaces of the first contact CA and the second contact CB may be substantially coplanar at a horizontal plane above the substrate.

[0113] The standard cell SCa_1 may include first contact jumpers and second contact jumpers 110 and 120. For example, the first contact jumper 110 and the second contact jumper 120 may be implemented by a first contact CA. The first contact jumper 110 may include a first portion that crosses the first gate line 130 over the first active region AR1 and a second portion that extends along a second direction (e.g., the Y direction) over the first gate line 130 in the intermediate region MR. The second contact jumper 120 may cross the first gate line 130 over the second active region AR2. For example, the first contact jumper 110 may correspond to Figure 2A or Figure 13 The first contact jumper CJ1, and the second contact jumper 120 can correspond to Figure 13 The second contact jumper wire CJ2. See above for reference. Figure 2A and 13 Other features / aspects described can also be applied to this example.

[0114] In one example, the integrated circuit 100 may further include a diced region CT. The diced region CT may be disposed above the first gate line 130 in the intermediate region MR. Therefore, even if a short circuit occurs between the first contact jumper 110 and the first gate line 130, the first gate line above the first active region AR1 (i.e., the PMOS gate line) may be insulated from the second gate line above the second active region AR2 (i.e., the NMOS gate line).

[0115] Figure 21B The example shows the relationship with Figure 21ACompared to the layout of the integrated circuit 100′ which also includes the first metal layer M1.

[0116] refer to Figure 21B The integrated circuit 100' may further include a first via V0 and a first metal layer M1 on the first via V0. The first via V0 may be part of a first via layer disposed on a contact layer including a first contact CA and a second contact CB. The first vias V0 may be aligned with each other in an intermediate region MR. For example, the first vias V0 may be arranged in a straight line in the intermediate region MR along a first direction (e.g., the X direction).

[0117] A first metal layer M1 is disposed on the first via layer and may be referred to as a first metallization layer. The first metal layer M1 may include: a first metal pattern M1a connecting the first vias V0 disposed in the first active region AR1 to each other; a second metal pattern M1b connecting the first vias V0 disposed in the second active region AR2 to each other; and a third metal pattern M1c, respectively connected to the first vias V0 disposed in the intermediate region MR. The first metal layer M1 may also include a power supply voltage pattern VDD and a ground voltage pattern VSS.

[0118] According to this example, only one horizontal metal trace, namely the first metal pattern M1a, can be arranged above the first active region AR1, and only one horizontal metal trace, namely the second metal pattern M1b, can be arranged above the second active region AR2. Since there is no horizontal metal trace extending beyond the first active region AR1, the second contact CB and the first via V0 arranged in the intermediate region MR can be aligned. Furthermore, the second contact CB can be implemented with the same pattern, and the first via V0 can also be implemented with the same pattern. Therefore, since the pattern in the integrated circuit 100' is simplified, processing risks can be reduced, and the number of design rule violations can be reduced during the design rule checking phase.

[0119] Figure 21C Showing examples and Figure 21B Compared to the layout of "integrated circuit 100" which also includes a second metal layer. Figure 22 It is along Figure 21C The cross-sectional view taken by lines X6a-X6a′ and X6b-X6b′ in the diagram.

[0120] refer to Figure 21C and Figure 22The integrated circuit 100 may further include a second via V1 (i.e., a second via layer on the first metallization layer M1) and a second metal layer M2 (i.e., a second metallization layer) on the second via V1 (layer). The second via V1 may be disposed on a third metal pattern M1c of the first metal layer M1 in the intermediate region MR. The second vias V1 may be aligned with each other in the intermediate region MR. For example, the second vias V1 may be arranged in a straight line along a first direction (e.g., the X direction) in the intermediate region MR.

[0121] The second metal layer M2 may include multiple metal patterns M2a to M2e. In one example, the metal patterns M2a to M2e may be identical patterns, i.e., they may have the same shape and size. For example, the widths of the multiple metal patterns M2a to M2e along the first direction may be equal to each other. Additionally, for example, the lengths of the multiple metal patterns M2a to M2e along the second direction (e.g., the Y direction) may be equal to each other. For example, metal patterns M2a, M2b, M2c, and M2e may correspond to input wiring patterns, i.e., metal input terminals, to which the first to fourth input signals A0, A1, B0, and B1 are applied, and metal pattern M2d may correspond to... Figure 20B The output wiring pattern ORT in the diagram represents the metal output terminal for the output signal Y.

[0122] Figure 23A and 23B They are shown as Figure 21A Other examples of integrated circuit 100 include integrated circuits 100a and 100b.

[0123] refer to Figure 23A Integrated circuit 100a is similar to Figure 21A An example of integrated circuit 100. Integrated circuit 100a may include a standard cell SCa_1a, and the first contact CA of the standard cell SCa_1a may be arranged between the gate lines GL in the first active region and the second active regions AR1 and AR2, respectively. The length of some of the first contacts CA along the second direction (e.g., the Y direction) may be less than Figure 21A The length of the first contact CA. In one example, the cut region CT can be positioned above the first gate line 130 in the intermediate region MR. Reference Figure 23B Integrated circuit 100b is similar to Figure 23A An example of integrated circuit 100a. Integrated circuit 100b may include a standard cell SCa_1b, and the cut-out region CT′ of the standard cell SCa_1b may be arranged above the first gate line 130 in the second active region AR2.

[0124] Figure 24A The layout of an integrated circuit 200 according to an example is shown.

[0125] refer to Figure 24A The integrated circuit 200 may include components corresponding to Figure 20A and 20B The standard cell SCa_2 in the standard cell SCa is described above. The standard cell SCa_2 may include a first active region and second active regions AR1 and AR2, multiple gate lines GL, trench silicide TS, a first contact CA, and a second contact CB. The trench silicide TS may be disposed between the gate lines GL in the first active region AR1 and the second active region AR2, respectively. The length of the trench silicide TS along a second direction (e.g., the Y direction) may be substantially equal to the lengths of the first active region AR1 and the second active region AR2 along the second direction. The first contact CA may be disposed on the trench silicide TS in the first active region AR1 and the second active region AR2, respectively. The second contact CB may be disposed on the gate line GL in the intermediate region MR, respectively.

[0126] The standard cell SCa_2 may include a first contact jumper and second contact jumpers 210 and 220. For example, the first contact jumper 210 and the second contact jumper 220 may be implemented by a first contact CA. The first contact jumper 210 may include a first portion crossing the first gate line 230 in the first active region AR1 and a second portion extending in a second direction above the first gate line 230 in the intermediate region MR. The second contact jumper 220 may cross the first gate line 230 in the second active region AR2. For example, the first contact jumper 210 may correspond to... Figure 6 or Figure 13 The first contact jumper CJ1, and the second contact jumper 220 can correspond to Figure 13 The second contact jumper wire CJ2. (See above for reference.) Figure 6 , 7 Other features / aspects of the example described in 13 can also be applied to this example.

[0127] Figure 24B The example shows the relationship with Figure 24A Compared to the layout of the integrated circuit 200', which also includes the first metal layer M1. (See reference) Figure 24B The integrated circuit 200' may further include a first via V0 and a first metal layer M1 on the first via V0. The first via V0 and the first metal layer M1 may be aligned with a reference. Figure 21B The example shown describes essentially the same approach, so it will not be described in detail again.

[0128] Figure 24C The example shows the relationship with Figure 24B Compared to the layout of "integrated circuit 200" which also includes a second metal layer M2. Figure 25 It is along Figure 24CThe cross-sectional views taken by lines X7a-X7a′ and X7b-X7b′ are shown in the reference. Figure 24C and Figure 25 The integrated circuit 200 may further include a second via V1 and a second metal layer M2 on the second via V1. The second via V1 and the second metal layer M2 may be aligned with a reference. Figure 21C The example shown describes essentially the same approach, and therefore will not be described in detail again.

[0129] Figure 26A The layout of integrated circuit 300 according to the example is shown.

[0130] refer to Figure 26A The integrated circuit 300 may include components corresponding to Figure 20A and 20B The standard cell SCa_3 in the standard cell SCa is described above, and the standard cell SCa_3 may include a first active region and second active regions AR1 and AR2, multiple gate lines GL, a first contact CA, a second contact CB, and a third contact CM. The first contact CA may be arranged between the gate lines GL in the first active region AR1 and the second active region AR2, respectively. The second contact CB may be arranged on the gate lines GL in the intermediate region MR, respectively. The third contact CM may be arranged on some of the first contacts CA and some of the second contacts CB.

[0131] The standard cell SCa_3 may include a first contact jumper and second contact jumpers 310 and 320. For example, the first contact jumper 310 and the second contact jumper 320 may be implemented by a third contact CM. The first contact jumper 310 may include a first portion crossing the first gate line 330 in the first active region AR1 and a second portion extending over the first gate line 330 in the intermediate region MR along a second direction (e.g., the Y direction). The second contact jumper 320 may cross the first gate line 330 in the second active region AR2. For example, the first contact jumper 310 may correspond to... Figure 8 , 11 Or the first contact jumper CJ1 of 13, and the second contact jumper 320 can correspond to Figure 13 The second contact jumper wire CJ2. (See above for reference.) Figures 8 to 13 Other aspects / features of the described example can also be applied to this example.

[0132] Figure 26B The example shows the relationship with Figure 26A Compared to the layout of the integrated circuit 300', which also includes the first metal layer M1. (See reference) Figure 26B The integrated circuit 300' may further include a first via V0 and a first metal layer M1 on the first via V0. The first via V0 may be disposed on a third contact CM. The first via V0 may be connected to... Figure 21B The example shown is implemented in essentially the same way, and repeated descriptions of it are omitted.

[0133] Figure 26C The example shows the relationship with Figure 26B Compared to the layout of the integrated circuit 300" which also includes a second metal layer M2. Figure 27 It is along Figure 26C The cross-sectional views taken by lines X8a-X8a′ and X8b-X8b′ are shown in the figure. (Reference) Figure 26C and Figure 27 The integrated circuit 300 may further include a second via V1 and a second metal layer M2 on the second via V1. The second via V1 and the second metal layer M2 may be connected to a reference. Figure 21C The example shown describes essentially the same implementation and therefore will not be described in detail again.

[0134] Figure 28A The symbol for the adder ADD is shown. Figure 28B This is the logic circuit diagram of the adder ADD, which includes the standard cell SCb, based on the example.

[0135] refer to Figure 28A and 28B The adder ADD may include an execution unit, which can be executed by a standard unit SCb. The standard unit SCb can receive first to third input signals A, B, and Cin and output an output signal Cout. References will be made below. Figures 29A to 29C The layout of an integrated circuit including a standard cell SCb is described. Specifically, various examples of contact jumpers used to implement the output wiring of the standard cell SCb will be described.

[0136] Figure 29A The layout of an integrated circuit 400 according to an example is shown.

[0137] refer to Figure 29A The integrated circuit 400 may include components corresponding to Figure 28B The standard cell SCb_1 in the standard cell SCb can include a first active region and second active regions AR1 and AR2, multiple gate lines GL, a first contact CA, a second contact CB, and a third contact CM. The first contact CA can be arranged between the gate lines GL in the first active region AR1 and the second active region AR2, respectively. The second contact CB can be arranged on the gate lines GL in the intermediate region MR, respectively. The third contact CM can be arranged on some of the first contacts CA and some of the second contacts CB.

[0138] The standard cell SCb_1 may include a contact jumper 410. For example, the contact jumper 410 may be implemented by a third contact CM. The contact jumper 410 may include a first portion crossing the first gate line 420 in the first active region AR1, a second portion extending above the first gate line 420 in the intermediate region MR along a second direction (e.g., the Y direction), and a third portion crossing the first gate line 420 in the second active region AR2 and connecting to the second portion. For example, the contact jumper 410 may correspond to Figure 16 The third contact jumper wire, CJ3. (See above for reference.) Figure 16 Other aspects / features of the described example can also be applied to this example.

[0139] Figure 29B The example shows the relationship with Figure 29A Compared to the layout of the integrated circuit 400' which also includes the first metal layer M1.

[0140] refer to Figure 29B The integrated circuit 400' may further include a first via V0 and a first metal layer M1 on the first via V0. The first via V0 may be disposed on a third contact CM. The first vias V0 may be aligned with each other in an intermediate region MR. For example, the first vias V0 may be arranged in a straight line in the intermediate region MR along a first direction (e.g., the X direction).

[0141] The first metal layer M1 may include a first metal pattern M1a′ connecting the first vias V0 arranged in the first active region AR1 to each other, a second metal pattern M1b′ connecting the first vias V0 arranged in the second active region AR2 to each other, and a third metal pattern M1c′ respectively connected to the first vias V0 arranged in the intermediate region MR. The first metal layer M1 may also include a power supply voltage pattern VDD and a ground voltage pattern VSS.

[0142] According to this example, only one horizontal metal trace, namely the first metal pattern M1a′, can be arranged above the first active region AR1, and only one horizontal metal trace, namely the second metal pattern M1b′, can be arranged above the second active region AR2. Therefore, the number of horizontal metal patterns in the standard cell can be limited to two; that is, two horizontal metal patterns are sufficient. If the integrated circuit 400′ does not include the contact jumper 410, the standard cell will require four horizontal metal patterns. Furthermore, according to this example, there is no horizontal metal trace extending beyond the first active region AR1. Therefore, the second contact CB, the third contact CM, and the first via V0 arranged in the intermediate region MR can be arranged in aligned positions. The second contact CB can be implemented with the same pattern, and the first via V0 can also be implemented with the same pattern.

[0143] According to this example, the widths of the third metal patterns M1c′ along the first direction can be equal to each other. Additionally, the lengths of the third metal patterns M1c′ along the second direction can be equal to each other. In this way, the third metal patterns M1c′ can be identical patterns and can be aligned with each other. For example, the third metal patterns M1c′ can be arranged in a straight line along the first direction.

[0144] Figure 29C The example shows the relationship with Figure 29B Compared to the layout of "integrated circuit 400" which also includes a second metal layer M2.

[0145] refer to Figure 29C The integrated circuit 400 may further include a second via V1 and a second metal layer M2 on the second via V1. The second via V1 may be disposed on the first metal layer M1 in the intermediate region MR. The second vias V1 may be aligned with each other in the intermediate region MR. For example, the second vias V1 may be arranged in a straight line in the intermediate region MR along a first direction (e.g., the X direction). Alternatively, the second vias V1 may be implemented in the same manner.

[0146] The second metal layer M2 may include multiple metal patterns M2a′ to M2e′. In one example, the metal patterns M2a′ to M2e′ may be identical. For example, the widths of the multiple metal patterns M2a′ to M2e′ along a first direction may be equal to each other. Additionally, the lengths of the multiple metal patterns M2a′ to M2e′ along a second direction (e.g., the Y direction) may be equal to each other. In one example, the metal patterns M2a′, M2b′, M2c′, and M2e′ may correspond to input wiring patterns. For example, a first input signal A may be applied to metal patterns M2a′ and M2c′, a second input signal B may be applied to metal pattern M2b′, and a third input signal Cin may be applied to metal pattern M2e′. In one example, the metal pattern M2d′ may correspond to an output wiring pattern. For example, an output signal Cout may be output from the metal pattern M2d′.

[0147] The integrated circuit 400 may further include a third via V2 and a third metal layer M3 on the third via V2. The third via V2 may be disposed on metal patterns M2a′ and M2c′ of the second metal layer M2, respectively. The third metal layer M3 may extend along a first direction and may be disposed on the third via V2 such that the metal patterns M2a′ and M2c′ are electrically connected to each other.

[0148] Figure 30 The layout of an integrated circuit 500 according to an example is shown.

[0149] refer to Figure 30The integrated circuit 500 may include a first active region and second active regions AR1 and AR2, a plurality of gate lines GL, first to third contact jumpers 510 to 530, a first via V0, and a first metal layer M1. In one example, as... Figure 2A and Figure 3 As shown, the first to third contact jumpers 510 to 530 can be implemented using the first contact CA. In one example, as... Figure 4 and 5 As shown, the first to third contact jumpers 510 to 530 can be implemented using the first contact CA and the second contact CB. In one example, as... Figure 6 and Figure 7 As shown, the first to third contact jumpers 510 to 530 can be implemented using trench silicide, the first contact CA, and / or the second contact CB. In one example, as... Figures 8 to 10 As shown, the first to third contact jumpers 510 to 530 can be implemented using the first contact CA and the third contact CM.

[0150] The first contact jumper 510 may have a T-shape, comprising a first portion that crosses the first gate line 540 over the first active region AR1 and a second portion that extends over the first gate line 540 in a second direction (e.g., the Y direction) and connects to the first portion. The second contact jumper 520 may cross the first gate line 540 over the second active region AR2. Therefore, the first gate line 540 may be a dummy gate line.

[0151] The third contact jumper 530 may have an I-shape, including a first portion that crosses the second gate line 550 over the first active region AR1, a second portion that crosses the second gate line 550 over the second active region AR2, and a third portion that extends over the second gate line 550 in a second direction and connects to the first and second portions. Therefore, the second gate line 550 may be a dummy gate line.

[0152] In one example, the first contact CA, positioned above the first active region AR1, can be aligned with each other along a first line L1. In one example, the second contact CB, positioned above the intermediate region MR, can be aligned with each other along a second line L2. In one example, the first contact CA, positioned above the second active region AR2, can be aligned with each other along a third line L3.

[0153] The first via V0 can be disposed on some first contacts CA and some second contacts CB. In one example, the first via V0 can be formed with a pattern of the same shape. In one example, the first via V0 disposed above the first active region AR1 can be aligned with each other along the first line L1. In one example, the first via V0 disposed above the intermediate region MR can be aligned with each other along the second line L2. In one example, the first via V0 disposed above the second active region AR2 can be aligned with each other along the third line L3.

[0154] The first metal layer M1 may include a first metal pattern M1a” extending above the first active region AR1 along a first direction, a second metal pattern M1b” extending above the second active region AR2 along a first direction, and a third metal pattern M1c” extending above the intermediate region MR along a second direction. Therefore, the number of horizontal metal patterns in the standard cell can be limited to two. The first metal pattern M1a” can connect the first contacts CA on the first active region AR1 to each other, the second metal pattern M1b” can connect the first contacts CA on the second active region AR2 to each other, and the third metal pattern M1c” can be connected to the second contacts CB on the intermediate region MR. In one example, the third metal pattern M1c” arranged above the second contacts CB can have the same height along the second direction.

[0155] Figure 31 The image shows a storage medium 1000 as an example.

[0156] refer to Figure 31 Storage medium 1000 may store cell library 1100, placement and routing (P&R) program 1200, static timing analysis (STA) program 1300, and layout data 1400. Storage medium 1000 may be a computer-readable storage medium and may include any storage medium that can be read by a computer during use to provide instructions and / or data to the computer. For example, storage medium 1000 may include magnetic or optical media such as magnetic disks, magnetic tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, or DVD-RWs; volatile or non-volatile memories such as RAM, ROM, or flash memory; non-volatile memories accessible via a USB interface; and microelectromechanical systems (MEMS). The computer-readable storage medium may be embedded in the computer, integrated into the computer, or coupled to the computer via a communication medium such as a network and / or wireless link.

[0157] Cell library 1100 may be a standard cell library and may include information related to standard cells that constitute integrated circuits. In one example, information modified with reference to standard cells may include layout information for layout generation. In another example, information modified with reference to standard cells may include timing information for layout verification or simulation. Specifically, cell library 1100 may include information related to the above reference. Figures 1 to 30 The layout information of the standard cells described.

[0158] P&R program 1200 may include instructions for performing placement and routing of standard cells using cell library 1100. STA program 1300 may include instructions for performing STA, where STA is a simulation method for calculating the expected timing of digital circuits, and can perform timing analysis on all timing paths of the placed standard cells and output the timing analysis results. Layout data 1400 may include physical information about the layout generated by the placement and routing operations.

[0159] As is conventional in the art, the illustrated block performing one or more functions as described above can be physically implemented by analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and can optionally be driven by firmware and / or software. For example, the circuitry can be implemented in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting the block can be implemented by dedicated hardware or a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some functions of the block and a processor for performing other functions of the block. Without departing from the scope of the inventive concept, each of the illustrated blocks can be physically divided into two or more interactive and discrete blocks. Similarly, without departing from the scope of the inventive concept, the illustrated blocks can be physically combined into more complex blocks.

[0160] Figure 32 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example.

[0161] refer to Figure 32 The methods for manufacturing semiconductor devices can be divided into integrated circuit design and integrated circuit manufacturing process. Integrated circuit design includes operations S110 and S130, and integrated circuit manufacturing process includes operations S150 and S170. Operations S150 and S170 are operations for manufacturing semiconductor devices based on layout data and can be executed by a semiconductor manufacturing module.

[0162] In operation S110, a synthesis operation is performed. For example, operation 240 can be executed by the processor using a synthesis tool. Specifically, this can be done by using a standard cell library (e.g., Figure 31 The standard cell library 1100 in the system synthesizes the input data defined in the register transfer level (RTL) of the integrated circuit to generate a gate-level netlist.

[0163] In operation S130, layout data for the integrated circuit is generated by defining standard cells of the integrated circuit based on the netlist placement and routing. For example, operation S130 can be executed by a processor using P&R tools. For instance, the layout data can be data in Graphical Design System (GDS) II format. Specifically, as... Figures 1 to 30 As shown, layout data can be generated by placing standard cells with reduced (i.e., relatively small) heights and including contact jumpers, thereby minimizing the overall size (occupancy) of the integrated circuit. Following operation S130, parasitic component extraction, STA operations, etc., can be further performed.

[0164] In operation S150, one or more masks are generated based on the layout data. Specifically, optical proximity correction (OPC) can be performed based on the layout data. OPC refers to the process of changing the layout to reflect errors caused by optical proximity effects. The mask can then be fabricated based on the layout modified according to the OPC results. In this case, the mask can be fabricated using a layout that reflects the OPC (e.g., GDS II that reflects the OPC).

[0165] In operation S170, the semiconductor device in which the integrated circuit is implemented is fabricated using a mask. Specifically, various semiconductor processes are performed on a semiconductor substrate, such as a wafer, using multiple masks to form the semiconductor device in which the integrated circuit is implemented. For example, the process using masks can refer to a patterning process via photolithography. Through the patterning process, a desired pattern can be formed on a semiconductor substrate or material layer. Semiconductor processes can include deposition processes, etching processes, ionization processes, cleaning processes, etc. Furthermore, semiconductor processes can include packaging processes where semiconductor devices are mounted on a printed circuit board (PCB) and sealed with sealing materials, and can include test processes for testing the semiconductor devices or packages.

[0166] Figure 33 This is a block diagram based on an example integrated circuit design system 2000.

[0167] refer to Figure 33The integrated circuit design system 2000 may include a processor 2100, a memory 2300, an input / output (I / O) device 2500, a storage device 2700, and a bus 2900. The integrated circuit design system 2000 may be provided as a dedicated device for designing integrated circuits for semiconductor devices, but it may also be a computer used to drive various simulation tools or design tools.

[0168] Processor 2100 can be configured to execute instructions for performing at least one of various operations for designing an integrated circuit. Processor 2100 can communicate with memory 2300, I / O device 2500, and storage device 2700 via bus 2900. Processor 2100 can perform operations to generate layout data for the integrated circuit by driving P&R module 2310 loaded in memory 2300. Memory 2300 can store P&R module 2310. Additionally, memory 2300 can also store synthesis module, parasitic component extraction module, and / or timing analysis module. P&R module 2310 can be loaded from storage device 2700 into memory 2300. Memory 2300 can be a volatile memory such as SRAM or DRAM, or a non-volatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

[0169] I / O device 2500 can control user input and output from the user interface device. For example, I / O device 2500 may include input devices such as a keyboard, mouse, or touchpad to receive input data defining the integrated circuit. Storage device 2700 can store various data related to P&R module 2310. Storage device 2700 may include memory cards (MMC, eMMC, SD, MicroSD, etc.), solid-state drives (SSDs), and / or hard disk drives (HDDs).

[0170] Although the inventive concept has been specifically shown and described with reference to examples thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. An integrated circuit, comprising: A first active region and a second active region in a substrate, the first active region and the second active region extending along a first direction, separated from each other along a second direction, and located on a first horizontal plane; The first contact is disposed on the first active region and located on a second horizontal plane different from the first horizontal plane; as well as The second contact extends along the first and second directions, overlaps with the first contact and the first active region, is electrically coupled to the first contact, and is located on a third horizontal plane different from the first and second horizontal planes.

2. The integrated circuit according to claim 1, further comprising: The third contact is disposed on the second active region, located on the second horizontal plane, and electrically coupled to the second contact.

3. The integrated circuit according to claim 1, wherein the first active region comprises: The first active portion corresponds to the drain of the first transistor of the first type; as well as The second active portion corresponds to the drain of the second transistor of the first type or the source of the first transistor of the first type, and The second active region includes an active portion corresponding to the drain or source of a third transistor of a second type different from the first type.

4. The integrated circuit of claim 1, wherein the second contact comprises: The first part extends along the first direction and overlaps with the first contact and the first active region; as well as The second part extends along the second direction and is electrically coupled to the first part.

5. The integrated circuit according to claim 4, further comprising: The third contact is disposed on the second active region, located on the second horizontal plane, and electrically coupled to the second contact. The second contact further includes: The third part extends along the first direction, separates from the first part along the second direction, is electrically coupled to the first part and the second part, and overlaps with the second active region and the third contact.

6. The integrated circuit according to claim 4, further comprising: A first gate line and a second gate line extend along the second direction and are located on the second horizontal plane, wherein the first gate line and the second gate line are separated from each other at regular intervals along the first direction; as well as The through hole on the second contact, The second portion of the second contact is disposed between the first gate line and the second gate line.

7. The integrated circuit of claim 6, wherein the first contact is one of the source contact or the drain contact of a transistor, and The first gate line is a PMOS gate line, and the second gate line is an NMOS gate line.

8. The integrated circuit according to claim 4, further comprising: A first gate line extends along the second direction and is located on the second horizontal plane; as well as The through hole on the second contact, The second portion of the second contact is disposed above the first gate line.

9. The integrated circuit of claim 1, wherein the integrated circuit is part of an AND-OR-NOT logic circuit.

10. The integrated circuit of claim 1, wherein the second contact has an L-shape, an H-shape, a T-shape, or an I-shape.

11. The integrated circuit according to claim 1, further comprising: The first metal pattern extends at least along the first direction, is located on a fourth horizontal plane that is different from the first horizontal plane, the second horizontal plane and the third horizontal plane, and overlaps at least with the first contact or the second contact.

12. The integrated circuit according to claim 11, further comprising: A first through-hole couples the first metal pattern to the first contact, the first through-hole being located between the first metal pattern and the first contact; as well as A second through-hole couples the first metal pattern to the second contact, the second through-hole being located between the first metal pattern and the second contact.

13. The integrated circuit according to claim 1, further comprising: The power rail extends at least along the first direction, is located on a fourth horizontal plane that is different from the first horizontal plane, the second horizontal plane and the third horizontal plane, and overlaps with the first contact. as well as A first through-hole couples the power rail to the first contact, the first through-hole being located between the power rail and the first contact.

14. An integrated circuit, comprising: A first active region in a substrate, the first active region being located on a first horizontal plane, the first active region comprising a first active portion and a second active portion; A first gate line is disposed on the first active region, extends along a second direction, and is located on a second horizontal plane different from the first horizontal plane. The first active portion is disposed on one side of the first gate line, and the second active portion is disposed on the other side of the first gate line. The first set of contacts is disposed on the first active portion, extends along the first direction, and is located on the second horizontal plane; as well as The second contact extends along the first and second directions, overlaps with the first group of contacts and the second active portion, is electrically coupled to the first contact in the first group of contacts, and is located on a third horizontal plane different from the first horizontal plane and the second horizontal plane.

15. The integrated circuit of claim 14, wherein the second contact comprises: The first part extends along the first direction and overlaps with the first contact, the first active part, and the second active part; as well as The second part extends along the second direction and is electrically coupled to the first part.

16. The integrated circuit of claim 14, further comprising: The second active region in the substrate, located on the first horizontal plane, includes a third active portion. The first group of contacts includes: The third contact is disposed on the third active portion of the second active region and electrically coupled to the second contact.

17. The integrated circuit according to claim 14, wherein the second contact has an L-shape, an H-shape, a T-shape, or an I-shape.

18. The integrated circuit according to claim 14, further comprising: The second gate line extends along the second direction and is located on the second horizontal plane, and the first gate line and the second gate line are separated from each other at regular intervals along the first direction.

19. The integrated circuit according to claim 14, further comprising: The first group of metal patterns extends at least along the first direction, is located on a fourth horizontal plane different from the first horizontal plane, the second horizontal plane and the third horizontal plane, and is at least in contact with or overlaps with the first group or the second contact.

20. The integrated circuit according to claim 19, further comprising: The first set of through holes couples the first set of metal patterns to the first set of contacts. The first set of through holes is located between the first set of metal patterns and the first set of contacts, and the through holes in the first set of through holes are located at the position where the metal patterns in the first set of metal patterns overlap with the first contact in the first set of contacts. as well as The second set of through holes couples the first set of metal patterns to the second contact. The second set of through holes is located between the first set of metal patterns and the second contact, and the through holes in the second set of through holes are located at the position where another metal pattern in the first set of metal patterns overlaps with the second contact.

21. The integrated circuit according to claim 14, further comprising: A set of power rails, extending at least along the first direction, is located on a fourth horizontal plane different from the first horizontal plane, the second horizontal plane, and the third horizontal plane, and contacts and overlaps with the first set; as well as The first set of through holes couples the set of power rails to the first set of contacts. The first set of through holes is located between the set of power rails and the first set of contacts, and the through holes in the first set of through holes are located at the position where the power rails in the set of power rails overlap with the fourth contact in the first set of contacts.

22. The integrated circuit of claim 14, wherein the first contact is one of the source contact or the drain contact of a transistor, and The first gate line is either a PMOS gate line or an NMOS gate line.

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