Integrated circuit and method of forming the same

Abstract

An integrated circuit comprising a first pair of power rails and a second pair of power rails arranged in a first layer; electrically conductive lines arranged in a second layer above the first layer; and a first active region arranged in a third layer above the second layer. The first active region is disposed to overlap the first pair of power rails. The first active region is coupled to the first pair of power rails by a first one of the electrically conductive lines and a first set of vias, and the first active region is coupled to the second pair of power rails by at least a second one of the electrically conductive lines and a second set of vias different from the first set of vias. Embodiments of the invention also relate to methods of forming an integrated circuit.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuits and methods for forming the same. Background Technology

[0002] In semiconductor manufacturing, the scaling of integrated circuits is limited by critical dimensions associated with back-to-line (BEOL) processes. BEOL scaling has slowed down along with current semiconductor manufacturing processes. Summary of the Invention

[0003] According to one aspect of the present invention, an integrated circuit is provided, comprising: a first pair of power rails and a second pair of power rails disposed in a first layer and extending in a first direction; a plurality of conductive lines disposed in a second layer above the first layer, wherein the plurality of conductive lines extend in a second direction different from the first direction and cross the first pair of power rails and the second pair of power rails; a first active region disposed in a third layer above the second layer and extending in a second direction, wherein the first active region is configured to overlap with the first pair of power rails; a first gate disposed above the first active region; and conductive traces disposed above the first gate and coupled to the first gate, wherein the first active region is coupled to the first pair of power rails through a first line of the plurality of conductive lines and a first set of vias, and the first active region is coupled to the second pair of power rails through at least one second conductive line of the plurality of conductive lines and a second set of vias different from the first set of vias.

[0004] According to another aspect of the present invention, an integrated circuit is provided, comprising: a first transistor, including: a first active region; a plurality of first conductive portions and a plurality of second conductive portions disposed in a first layer and above the first active region, wherein the plurality of first conductive portions correspond to the source of the first transistor and the plurality of second conductive portions correspond to the drain of the first transistor; and a plurality of first gates, corresponding to the gates of the first transistor, disposed above the first active region and interposed between one of the plurality of first conductive portions and one of the plurality of second conductive portions; and a plurality of conductive lines disposed in a second layer below the first active region, wherein the plurality of conductive lines include first conductive lines and a plurality of second conductive lines; wherein, in response to an input signal received at the gate of the first transistor, the source of the first transistor is coupled to an external voltage through the first conductive lines, and the drain of the first transistor is coupled to a first power supply voltage through the plurality of second conductive lines.

[0005] According to another aspect of the present invention, a method for forming an integrated circuit is provided, comprising: forming a plurality of power rails in a first layer, wherein the plurality of power rails extend in a first direction and are separated from each other in a second direction; forming a plurality of conductive lines in a second layer above the first layer, wherein the plurality of conductive lines extend in the second direction; forming a plurality of active regions in a third layer above the second layer; forming a plurality of conductive portions above the plurality of active regions in the third layer, wherein a first active region of the plurality of active regions is coupled to at least a first conductive line and a second conductive line among the plurality of conductive lines; forming a plurality of gates above the plurality of active regions, wherein the gates are interposed between the plurality of conductive portions; forming a plurality of conductive traces in a fourth layer above the third layer, wherein the plurality of conductive traces extend in the second direction; and forming a conductive pattern in a fifth layer above the fourth layer, wherein the conductive pattern is coupled to the plurality of conductive traces. Attached Figure Description

[0006] Various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings.

[0007] Figure 1A It is an equivalent circuit of a portion of an integrated circuit according to various embodiments.

[0008] Figure 1B Based on the various embodiments Figure 1A The equivalent circuit portion of the power gate circuit is represented by the transistor.

[0009] Figure 2A It is an equivalent circuit of a portion of an integrated circuit according to various embodiments.

[0010] Figure 2B Based on the various embodiments Figure 2A The equivalent circuit portion of the power gate circuit is represented by the transistor.

[0011] Figure 3A According to various embodiments Figure 1B The layout diagram of a portion of an integrated circuit.

[0012] Figures 3B-3C According to various embodiments Figure 3A A cross-sectional view of a portion of an integrated circuit.

[0013] Figure 4A According to various embodiments Figure 3A The layout diagram of a portion of an integrated circuit.

[0014] Figure 4B According to various embodiments Figure 4A A cross-sectional view of a portion of an integrated circuit.

[0015] Figure 5A According to various embodiments Figure 1B The layout diagram of a portion of an integrated circuit.

[0016] Figure 5B According to various embodiments Figure 4A A cross-sectional view of a portion of an integrated circuit.

[0017] Figure 6 According to various embodiments Figure 5A A schematic diagram of a portion of an integrated circuit.

[0018] Figure 7 According to various embodiments Figure 2B The layout diagram of a portion of an integrated circuit.

[0019] Figure 8 It is a layout diagram of a portion of an integrated circuit according to various embodiments.

[0020] Figure 9 It is a layout diagram of a portion of an integrated circuit according to various embodiments.

[0021] Figure 10 It is a layout diagram of a portion of an integrated circuit according to various embodiments.

[0022] Figure 11 This is a flowchart of a method for operating an integrated circuit according to various embodiments.

[0023] Figure 12 This is a flowchart of a method for manufacturing an integrated circuit according to various embodiments.

[0024] Figure 13 It is a block diagram of an integrated circuit device design system according to various embodiments.

[0025] Figure 14 It is a block diagram of an integrated circuit manufacturing system and its associated integrated circuit manufacturing process according to various embodiments. Detailed Implementation

[0026] The following disclosure provides various embodiments or examples for implementing different components of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, indicate relationships between the various embodiments and / or configurations discussed.

[0027] The terms used in this specification have their common meanings in the art and in the specific text in which each term is used. The examples used in this specification, including examples of any terms discussed herein, are merely illustrative and are in no way intended to limit the scope and meaning of the invention or any exemplary terminology. Similarly, the invention is not limited to the various embodiments given in this specification.

[0028] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. The term “and / or” as used herein includes any and all combinations of one or more of the listed related items.

[0029] As used herein, “approximately,” “about,” “approximately,” or “substantially” should generally refer to any approximation of a given value or range, within which any approximation varies according to the respective fields to which it pertains, and whose range is subject to the broadest interpretation understood by those skilled in the art to encompass all such modifications and similar structures. In some embodiments, the given value or range should generally be within 20%, preferably within 10%, and more preferably within 5%. The numerical quantities given herein are approximate quantities, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “roughly,” or “approximately” can be inferred to mean other approximations.

[0030] For reference Figure 1A According to various embodiments, Figure 1A It is an equivalent circuit that is part of integrated circuit 10. For example... Figure 1AAs exemplarily shown, integrated circuit 10 includes a power gate circuit 100 having inverters 110-120 and a P-type transistor M1. The power gate circuit 100 is configured to be connected to an external power supply (not shown) to receive an external voltage, i.e., voltage TVDD, from the external power supply to integrated circuit 10. In response to the signal NSLEEPIN, the power gate circuit 100 is configured to output a power supply voltage (i.e., voltage VDD) to a cell circuit (not shown) included in integrated circuit 10. In some embodiments, the power gate circuit 100 is also referred to as a connector in integrated circuit 10.

[0031] For illustration, inverter 110 is configured to invert the signal NSLEEPIN and output the input signal IN to inverter 120 and transistor M1. Inverter 120 is configured to invert the signal IN to output the signal NSLEEPOUT. In response to the input signal IN received at the gate of transistor M1, transistor M1 is configured to output a voltage VDD in response to an external signal TVDD received at the source end of the transistor. In some embodiments, the signal NSLEEPIN has a high logic (i.e., logic 1), and correspondingly, inverter 110 outputs the input signal IN with a low logic (i.e., logic 0). Transistor M1 is turned on and outputs the power supply voltage VDD.

[0032] For reference Figure 1B According to various embodiments, Figure 1B yes Figure 1A Detailed circuit diagram of the equivalent circuit portion of the power gate circuit 100. For example... Figure 1B As exemplarily shown, inverter 110 includes a P-type transistor M2 and an N-type transistor M3. Inverter 120 includes a P-type transistor M4 and an N-type transistor M5. The gates of transistors M2-M3 are coupled together to receive the signal NSLEEPIN. A first terminal of transistor M2 is coupled to the first terminal of transistor M3 at the gate of transistor M1. The gates of transistors M4-M6 are coupled together at the gate of transistor M1. A first terminal of transistor M4 is coupled to the first terminal of transistor M5 to output the signal NSLEEPOUT.

[0033] For reference Figure 2A According to various embodiments, Figure 2A It is an equivalent circuit that is part of integrated circuit 10. Relative to... Figure 1A-Figure 1B The embodiments are provided for ease of understanding. Figure 2A Similar elements in the same text are assigned the same reference numerals. For the sake of brevity, unless otherwise specified... Figure 2A The cooperative relationships of the components shown are omitted here, as the specific operations of similar components discussed in detail above are not described.

[0034] For illustration, integrated circuit 10 includes a power gate circuit 200. (The last sentence appears to be incomplete and possibly refers to a different circuit.) Figure 1A Compared to the power gate circuit 100, the power gate circuit 200 includes an N-type transistor M6 instead of a P-type transistor M1. The power gate circuit 200 is configured to couple to an external power supply (not shown) to allow the integrated circuit 10 to receive an external voltage, i.e., voltage TVSS, from the external power supply. In response to the signal NSLEEPIN, the power gate circuit 200 is configured to output a power supply voltage (i.e., voltage VSS) to a cell circuit (not shown) included in the integrated circuit 10. In some embodiments, the power gate circuit 200 is referred to as a footer of the integrated circuit 10.

[0035] For reference Figure 2B According to various embodiments, Figure 2B yes Figure 2A Detailed circuit diagram of the equivalent circuit portion of the power gate circuit 200. (Compared to...) Figures 1A-2A The embodiments are provided for ease of understanding. Figure 2B Similar elements in the same text are assigned the same reference numeral.

[0036] For illustration, in response to the input signal IN received at the gate of transistor M6, transistor M6 is configured to output a voltage VSS in response to an external signal TVSS received at the source end of the transistor. In some embodiments, the signal NSLEEPIN has low logic (i.e., logic 0), and correspondingly, inverter 110 outputs the input signal IN with high logic (i.e., logic 1). Transistor M6 turns on and outputs the power supply voltage VSS.

[0037] For illustrative purposes, the following is given: Figure 1A-Figure 2B The configuration is as follows. Various embodiments are within the scope of this invention. For example, in some embodiments, the power gate circuits 100 and 200 do not include inverters 110-120 and only include transistors M1 and M6, respectively.

[0038] For reference Figure 3A According to various embodiments, Figure 3A yes Figure 1B The layout diagram of a portion of the integrated circuit 10.

[0039] For the purpose of explanation, such as Figure 3AAs shown, integrated circuit 10 includes power rails 201-202, conductive lines 301-303, active regions 401-405, conductive portions 501-510, gates 601-608, and vias VD1-VD6 and VM1-VM2 on a substrate (not shown). In some embodiments, power rails 201-202 are disposed in a first layer. Conductive lines 301-303 are disposed in a second layer above the first layer. Active regions 401-405 are disposed in a third layer above the second layer. Conductive portions 501-510 and gates 601-608 are disposed above the active regions. Vias VM1-VM2 are disposed between the first and second layers. Vias VD1-VD6 are disposed between the second and third layers.

[0040] refer to Figure 1B and Figure 3A In the formation of transistors M1-M5, source regions 401-405 are configured. Conductive portion 501 corresponds to the second terminal of transistor M4, and conductive portion 502 corresponds to the first terminal of transistors M4-M5. Gate 602 corresponds to the gate of transistors M4-M5. Conductive portion 503 corresponds to the second terminal of transistor M5. Conductive portion 504 corresponds to the second terminal of transistor M3, and conductive portion 505 corresponds to the first terminal of transistors M2-M3. Gate 603 corresponds to the gate of transistors M2-M3. Conductive portion 506 corresponds to the second terminal of transistor M2. Conductive portions 507 and 509 together correspond to the source of transistor M1, and conductive portions 508 and 510 together correspond to the drain of transistor M1. Gates 605-607 together correspond to the gate of transistor M1. According to some embodiments, since conductive portions 507 and 509 are coupled to the source of transistor M1, conductive portions 508 and 510 are coupled to the drain of transistor M1, and gates 605-607 are coupled together to form the gate of transistor M1, transistor M1 is formed in a parallel structure based on these elements. In some embodiments, gates 601, 604, and 608 are referred to as dummy gates. In some embodiments, these "dummy" gates are referred to as gates for unconnected MOS devices, which do not function in the circuit.

[0041] For illustration, power rails 201-202 extend in the y-direction and are separated from each other in the x-direction. In some embodiments, power rail 202 outputs an external voltage TVDD to the power gate circuit 100, and power rail 201 outputs a power supply voltage VDD from the power gate circuit 100. This will be discussed in detail in the following paragraphs. In some embodiments, power rails 201-202 are referred to as metal-2 (M-2) layers.

[0042] Conductive lines 301-303 extend in the x-direction and are separated from each other in the y-direction. Conductive lines 302-303 are further separated from each other in the x-direction. In the layout diagram, conductive lines 301-303 cross power rails 201-202. In some embodiments, the width of conductive line 303 is smaller than the width of conductive line 301. In some embodiments, conductive lines 301-303 are referred to as a metal-1 (M-1) layer.

[0043] Active regions 401-405 extend in the x-direction. Active regions 402-405 are separated from each other in the y-direction. Active region 401 overlaps with conductive lines 301 and 303. Active region 402 overlaps with conductive line 301. Active regions 403-404 overlap with conductive line 302. In some embodiments, active region 401 further includes, for example, Figure 3A The active regions shown are 401a-401d.

[0044] In some embodiments, active regions 401-402 and 405 are doped with P-type dopants such as boron, indium, aluminum, gallium, or combinations thereof. Active regions 403-404 are doped with N-type dopants such as phosphorus, arsenic, or combinations thereof.

[0045] Gates 601-608 extend in the y-direction and are separated from each other in the x-direction. For example... Figure 3A As shown, gate 602 spans active regions 402-403. Gate 603 spans active regions 404-405. Gates 605-607 span active region 401. Gate 604 is disposed between active regions 401 and active regions 402-405.

[0046] In some embodiments, each of gates 601-608 includes an interface layer (not shown) and one or more polysilicon (or multiple) layers (not shown) above the interface layer. In some embodiments, gates 601-608 further include a gate dielectric layer (not shown) and a metal gate layer (not shown) disposed between the interface layer and the multiple layers. In some embodiments, gates 601-608 include one or more metal layers instead of multiple layers. In various embodiments, the interface layer includes a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some embodiments, the polysilicon layer is formed by a suitable deposition process, including, for example, low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD). In some embodiments, the gate dielectric layer uses a high-k dielectric material, including, for example, hafnium oxide (HfO2), Al2O3, lanthanide oxides, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, and combinations thereof, or other materials. The gate dielectric layer is formed by ALD and / or other suitable methods. The metal gate layer includes a p-type work function metal or an n-type work function metal and is formed by CVD, PVD, and / or other suitable processes. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TaAlN, TaC, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. One or more metal layers are formed using aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), and / or other suitable materials, by CVD, PVD, electroplating, and / or other suitable processes. For illustrative purposes, the morphologies and / or materials associated with gates 601-608 are given. Various morphologies and / or materials associated with gates 601-608 are within the scope of this invention.

[0047] Via VM1 couples power rail 202 to conductive line 303. Via VM2 couples power rail 201 to conductive line 301. Vias VD1-VD2 couple conductive line 303 to active region 401. Vias VD3-VD4 couple active region 401 to conductive line 301. Via VD5 couples active region 403 to conductive line 302, and via VD6 couples active region 404 to conductive line 302.

[0048] For reference Figures 3B-3C According to various embodiments, Figure 3B yes Figure 3AA cross-sectional view of a portion of integrated circuit 10 along line AA'. Figure 3C yes Figure 3A A cross-sectional view of a portion of integrated circuit 10 along line BB'.

[0049] like Figure 3B As shown, the power rail 202 is coupled to the active region 401, the conductive line 303, and the via VD1 through the via VM1. The conductive part 509 is coupled to the active region 401 and covers the active region 401.

[0050] like Figure 3C As shown, power rail 202 is coupled to conductive line 303. Conductive part 508 is coupled to and covers active region 401. Active region 401 is coupled to conductive line 301 through via VD4.

[0051] For illustrative purposes, the following is given: Figures 3A-3C The configuration is as follows. Various embodiments are within the scope of this invention. For example, in some embodiments, the power gate circuit 100 does not include conductive portions 509-510, gates 606-608, and vias VD1 and VD3. In some alternative embodiments, the integrated circuit 10 includes other conductive lines configured relative to and adjacent to conductive lines 302-303, and the integrated circuit 10 also includes vias coupled to the other conductive lines and the conductive portion 508.

[0052] For reference Figure 4A According to various embodiments, Figure 4A yes Figure 3A The layout diagram of a portion of the integrated circuit 10. Relative to... Figures 1A-3C The embodiments are provided for ease of understanding. Figure 4A Similar elements in the same text are assigned the same reference numeral.

[0053] like Figure 4A As shown, the integrated circuit 10 also includes conductive traces 701-706, a conductive pattern 801, and vias VD7-VD12, VG1-VG5, and VM3-VM4. In some embodiments, conductive traces 701-706 are disposed in a fourth layer above the third layer. The conductive pattern 801 is disposed in a fifth layer above the fourth layer. The vias VD7-VD12 and VG1-VG5 are disposed between the third and fourth layers. The vias VM3-VM4 are disposed between the fourth and fifth layers.

[0054] For illustration, conductive traces 701-706 extend in the x-direction and are separated from each other. In some embodiments, conductive traces 701-706 are also referred to as a metal-O (MO) layer. Specifically, conductive trace 701 spans conductive portions 501-502 and 507 and gate 602. Conductive trace 702 spans conductive portions 502 and 507-510 and gates 604-607. Conductive trace 703 spans conductive portions 502 and 507 and gate 604. Conductive trace 704 spans conductive portions 505 and 507 and gate 604. Conductive trace 705 spans conductive portion 505 and gate 603. Conductive trace 706 spans conductive portions 505-507 and gates 603-604.

[0055] The conductive pattern 801 extends in the y direction and crosses the conductive traces 702-704.

[0056] Via VG1 couples conductive trace 705 to gate 603. Via VD7 couples conductive portion 505 to conductive trace 704. Via VM3 couples conductive trace 704 to conductive pattern 801. Via VM4 couples conductive pattern 801 to conductive trace 702. Vias VG2-VG5 couple conductive trace 702 to gates 605-607 and 602, respectively.

[0057] Based on the above configuration, in some embodiments... Figure 1A The signal NSLEEPIN is transmitted to the gate 603 via trace 705 and via VG1. Figure 1AThe input signal IN is output to the gates 605-607 through conductive portion 505, via VD7, conductive trace 704, via VM3, conductive pattern 801, via VM4, conductive trace 702, and vias VG2-VG4. Correspondingly, when the conducting transistor M1 responds to the input signal IN, conductive channels are established between active regions 401a-401b, between active regions 401b-401c, and other conductive channels between active regions 401c-401d. For example, a portion of the current input from power rail 202 flows to power rail 201 through a path including via VM1, conductive line 303, via VD2, active region 401a, conductive channel between active regions 401a-401b, active region 401b, via VD4, conductive line 301, and via VM2. Similarly, another portion of the current flows to power rail 201 via a different path, including via VM1, conductive line 303, via VD1, active region 401c, other conductive channels between active regions 401b and 401c, active region 401b, via VD4, conductive line 301, and via VM2. The remaining portion of the current flows to power rail 201 via via VM1, conductive line 303, via VD1, active region 401c, conductive channels between active regions 401c and 401d, active region 401d, via VD3, conductive line 301, and via VM2. In other words, through... Figure 4A With this configuration, power rail 201 further outputs a power supply voltage VDD corresponding to the external voltage TVDD input from power rail 202.

[0058] Continue to refer to Figure 4A Vias VD7 and VD8 couple conductive portions 501 and 507 to conductive trace 701, respectively. Vias VD11 and VD12 couple conductive portions 506 and 507 to conductive trace 706, respectively. Accordingly, in some embodiments, conductive portions 501 and 506 corresponding to the second terminal of transistor M4 are coupled to an external voltage TVDD.

[0059] Through-hole VD8 couples conductive portion 502 to conductive trace 703. In some embodiments, Figure 1A The signal NSLEEPOUT is output from the conductive part 502 corresponding to the first end of transistors M4-M5.

[0060] In some embodiments, the conductive line 302 is the voltage received by the integrated circuit 10, i.e., VSS. For illustrative purposes, as follows Figure 4A As shown, corresponding to the second terminals of transistors M3 and M5, conductive parts 503-504 are coupled to conductive lines 302 through vias VD5-VD6 to receive voltage VSS.

[0061] For reference Figure 4BAccording to various embodiments, Figure 4B yes Figure 4A A cross-sectional view of a portion of integrated circuit 10 along line CC'. For illustration, conductive trace 702 is coupled to gate 606 through via VG3. Gate 606 covers active region 401.

[0062] In some methods, the power rails corresponding to power rails 201-202 are arranged in a layer above the circuitry, such as the power gate circuitry 100 and / or the computing circuitry. In other words, in these methods, these power rails of the front-side power distribution network occupy front-side wiring resources and negatively impact the reduction of integrated circuit size.

[0063] According to the configuration of the present invention, conductive rails 201-202 are arranged below the power gate circuit 100 (and / or computing circuit) to input external voltage and output power supply voltage. Accordingly, in the power distribution network implemented by power rails 201-202, front-side wiring resources are maximized and the impact of power IR voltage drop caused by the power rails is minimized.

[0064] For illustrative purposes, the following is given: Figures 4A-4B The configuration is as follows. Various embodiments are within the scope of this invention. For example, in some embodiments, other power rails configured relative to power rail 201 are arranged adjacent to power rail 202 and coupled to conductor 301. These other power rails output voltage VDD along power rail 201.

[0065] For reference Figure 5A According to various embodiments, Figure 5A yes Figure 1B The layout diagram of a portion of the integrated circuit 10. Relative to... Figures 1A-4B The embodiments are provided for ease of understanding. Figure 5A Similar elements in the same text are assigned the same reference numerals. For the sake of brevity, unless otherwise specified... Figure 5A The cooperative relationships of the components shown are omitted here, as the specific operations of similar components discussed in detail above are not described.

[0066] Compared to Figure 4AThe integrated circuit 10 also includes power rails 203-204, conductive lines 304-305, active regions 406-409, conductive portions 511-515, gates 609-613, and vias VD13-VD18, VG6-VG8, and VM5-VM8. In some embodiments, for example, power rails 203-204 are configured relative to power rails 202 and 201, respectively. Power rails 201 and 204 are also referred to as a pair of power rails, and power rails 202-204 are also referred to as another pair of power rails. For example, conductive lines 304-305 are configured relative to conductive lines 302 and 305, respectively. For example, active regions 406-409 are configured relative to active regions 402-405, respectively. For example, conductive portions 511-515 are configured relative to conductive portions 510, respectively. For example, gates 609-613 are configured relative to gate 608. For example, vias VD13-VD16 are configured relative to via VD3. For example, through holes VD17-VD18 are configured relative to through hole VD2. For example, through holes VD6-VD8 are configured relative to through hole VD4. For example, through holes VM5-VM8 are configured relative to through hole VM1.

[0067] In some embodiments, conductive segments 511 and 513 together correspond to the source of transistor M1, and conductive portions 510 and 512 together correspond to the drain of transistor M1. Gates 608-610 together correspond to the gate of transistor M1. In some embodiments, gates 611-613 are also referred to as dummy gates.

[0068] For illustration, power rails 203-204 extend in the y-direction and are separated from each other in the x-direction. In some embodiments, power rails 202-203 output an external voltage TVDD to the power gate circuit 100, and power rails 201 and 204 output a power supply voltage VDD from the power gate circuit 100. In some embodiments, power rails 203-204 are referred to as metal-2 (M-2) layers.

[0069] Conductive lines 302-304 are arranged in the same row. Conductive line 303 further crosses power rail 203, and conductive line 304 crosses power rail 204. Conductive line 305 is arranged adjacent to conductive lines 302-304 and extends in the x-direction. In the layout diagram, conductive line 305 crosses power rails 201-204. In some embodiments, conductive lines 304-305 are referred to as the metal-1 (M-1) layer.

[0070] Compared to Figure 3A The active zone 401 also includes, for example, Figure 5A The active regions shown are 401e-401g.

[0071] For illustration, active regions 406-409 extend in the x-direction. Active regions 406-409 are separated from each other in the y-direction. Active region 406 overlaps with conductive line 301. Active regions 407-408 overlap with conductive lines 303-304. Active region 409 overlaps with conductive line 305.

[0072] In some embodiments, active regions 406 and 409 are doped with P-type dopants such as boron, indium, aluminum, gallium, or combinations thereof. Active regions 407-408 are doped with N-type dopants such as phosphorus, arsenic, or combinations thereof.

[0073] Gates 609-613 extend in the y-direction and are separated from each other in the x-direction. For example... Figure 5A As shown, gates 608-610 span the active region 401. Gate 611 is disposed between the active regions 401 and the active regions 406-409. Gate 612 spans the active regions 406-409.

[0074] Via VM5 couples power rail 203 to conductive line 303. Via VM6 couples power rail 201 to conductive line 305. Vias VM7-VM8 couple power rail 204 to conductive lines 301 and 305 respectively. Vias VD13, VD14, and VD16 couple active region 401 to conductive line 305. Via VD15 couples active region 401 to conductive line 301. Vias VD17-VD18 couple conductive line 303 to active region 401.

[0075] Compared to Figure 4A The conductive trace 702 is also coupled to the gate 608-610 through vias VG6-VG8.

[0076] For reference Figure 5B According to various embodiments, Figure 5B yes Figure 5A A cross-sectional view of a portion of integrated circuit 10 along line BB'. (Relative to...) Figure 3C A through-hole VD13 is arranged and coupled between the active region 401 and the conductive line 405.

[0077] For reference Figure 6 According to various embodiments, Figure 6 yes Figure 5A A schematic diagram of the operation corresponding to a portion of integrated circuit 10. Relative to... Figures 1A-5B The embodiments are provided for ease of understanding. Figure 6 Similar elements in the text are assigned the same reference numeral. For the sake of brevity, Figure 6 The metal layers corresponding to metal-0 and metal-1 layers and some vias are not shown.

[0078] In some embodiments, when the conducting transistor M1 responds to the input signal IN, it establishes a conductive channel between active regions 401a-401b, other conductive channels between active regions 401c-401d, other conductive channels between active regions 401d-401e, and other conductive channels between active regions 401f-401g.

[0079] For the purpose of explanation, Figure 6 The arrows in the diagram indicate the current flowing through the components in the power gate circuit 100. In some embodiments, a portion of the current input from the power rail 202 flows to the power rail 201 via a path including via VM1, conductive line 303, via VD2, active region 401a, conductive channel between active regions 401a-401b, active region 401b, vias VD4 and VD13, conductive lines 301 and 305, and vias VM2 and VM6. The current also flows to the power rail 204 via conductive lines 301 and 305 and vias VM7-VM8.

[0080] Similarly, other portions of the current input to power rail 202 flow to power rail 201 through other paths, including via VM1, conductor 303, via VD1, active region 401c, conductive channel between active regions 401c and 401d, active region 401d, vias VD3 and VD14, conductors 301 and 305, and vias VM2 and VM6. The current also flows to power rail 204 through conductors 301 and 305 and vias VM7-VM8.

[0081] Part of the current input to power rail 203 flows to power rail 201 through via VM5, conductive line 303, via VD17, active region 401e, conductive channel between active regions 401d and 401e, active region 401d, vias VD3 and VD14, conductive lines 301 and 305, and vias VM2 and VM6. The current also flows to power rail 204 through conductive lines 301 and 305 and vias VM7-VM8.

[0082] Other portions of the current input to power rail 203 flow to power rail 201 through via VM5, conductor 303, via VD18, active region 401g, conductive channel between active regions 401f and 401g, active region 401f, vias VD15 and VD16, conductors 301 and 305, and vias VM2 and VM6. The current also flows to power rail 204 through conductors 301 and 305 and vias VM7-VM8.

[0083] based on Figure 6 With the above configuration, power rails 201 and 204 output power supply voltage VDD corresponding to the external voltage TVDD input from a pair of power rails 202-203.

[0084] For illustrative purposes, the following is given: Figure 6 Configurations are described. Various embodiments are within the scope of this invention. For example, in some embodiments, a conductive channel is created between active regions 401b-401c to transmit current input from power rail 202. Another conductive channel is created between active regions 401e-401f to transmit current input from power rail 203. In alternative embodiments, active regions 406-409 are not included in the power gate circuit 100.

[0085] For reference Figure 7 According to various embodiments, Figure 7 yes Figure 2B The layout diagram of a portion of the integrated circuit 10. Relative to... Figures 1A-6 The embodiments are provided for ease of understanding. Figure 7 Similar elements in the same text are assigned the same reference numeral.

[0086] Compared to Figure 5A In the power gate circuit 200 of integrated circuit 10, the active regions 401, 402, 405-406 and 409 are N-type doped regions, and the active regions 403-404 and 407-408 are P-type doped regions.

[0087] In some embodiments, referencing Figure 2B and Figure 7 In the formation of transistor M6, a source region 401 is provided. Source regions 402-405 are provided in the formation of transistors M5, M4, M2, and M3, respectively. Conductive portion 501 corresponds to the second terminal of transistor M5, and conductive portion 502 corresponds to the first terminal of transistors M4-M5. Gate 602 corresponds to the gate of transistors M4-M5. Conductive portion 503 corresponds to the second terminal of transistor M4. Conductive portion 504 corresponds to the second terminal of transistor M2, and conductive portion 505 corresponds to the first terminal of transistors M2-M3. Gate 603 corresponds to the gate of transistors M2-M3. Conductive portion 506 corresponds to the second terminal of transistor M3. Conductive portions 507, 509, 511, and 513 simultaneously correspond to the drain of transistor M6, and conductive portions 508, 510, and 512 simultaneously correspond to the source of transistor M6. Gates 605-610 correspond to the gate of transistor M6. According to some embodiments, conductive portions 507, 509, 511, and 513 are coupled to the drain of transistor M6, conductive portions 508, 510, and 512 are coupled to the source of transistor M6, and gates 605-610 are coupled together to form the gate of transistor M6, transistor M6 being formed in a parallel structure based on these elements. In some embodiments, gates 601, 604, and 613 are referred to as dummy gates.

[0088] Configuration of power gate circuit 200 and Figure 5A The power gate circuit 100 is similar. Additionally, power rails 202-203 will use the external voltage TVSS instead of... Figure 5A The external voltage TVDD shown is input to the power gate circuit 200. Accordingly, when the turn-on transistor M6 responds to the input signal IN, the power gate circuit 200 receives the external voltage TVSS through power rail pairs 202-203 and outputs the power supply voltage VSS through power rail pairs 201 and 204.

[0089] In some embodiments, conductive lines 302 and 304, instead of receiving voltage VSS from integrated circuit 10, receive voltage (i.e., VDD). Correspondingly, corresponding to the second ends of transistors M2 and M4, conductive portions 503-504 are coupled to conductive line 302 through vias VD5-VD6 to receive voltage VDD.

[0090] For reference Figure 8 According to various embodiments, Figure 8 This is a layout diagram of a portion of the integrated circuit 80. Relative to... Figures 1A-7 The embodiments are provided for ease of understanding. Figure 8 Similar elements in the same text are assigned the same reference numerals. For the sake of brevity, unless otherwise specified... Figure 8 The cooperative relationships of the components shown are omitted here, as the specific operations of similar components discussed in detail above are not described.

[0091] like Figure 8 As exemplarily shown, integrated circuit 80 includes power rails 211-218, conductive lines 311-315 and 320-329, and power gate circuits 100A-100D. Power rails 211-218 are arranged in a first layer and, for example, relative to, Figure 4A The power rails 201-202 are configured. Conductive lines 311-315 are arranged in the second layer above the first layer and relative to, for example, Figure 4A Conductive wire 301 is configured. Conductive wires 320-329 are arranged in the second layer and, for example, relative to, Figure 4A Conductive lines 302-303 are configured. Power gate circuits 100A-100D are arranged in a third layer above the second layer and, for example, relative to... Figure 4A The power gate circuit 100 is configured. Through-holes are arranged between the first and second layers, and relative to, for example, Figure 4A The through-hole VM1 configuration. For simplicity, Figure 8 The metal layers corresponding to metal-0 and metal-1 are not shown in the diagram, nor are the corresponding vias.

[0092] For illustration, power rails 211-218 extend in the y-direction and are separated from each other in the x-direction. In some embodiments, power rails 212 and 217 receive an external voltage TVDD. Power rails 214-215 receive a voltage VSS. Power rails 211, 213, 216, and 218 are configured to output a power supply voltage VDD corresponding to the external voltage TVDD.

[0093] Conductive lines 311-315 and 320-329 extend in the x-direction. For example... Figure 8 As shown, conductors 320-324 are arranged in the same row and interspersed between conductors 311-312. Conductors 325-329 are arranged in the same row and interspersed between conductors 314-315. Conductors 311-315 cross power rails 211-218. Conductors 320 and 325 overlap with power rail 211. Conductor 321 overlaps with power rails 211-213. Conductors 322 and 327 overlap with power rails 213-216. Conductors 323 and 328 overlap with power rail 217. Conductors 324 and 329 overlap with power rail 218.

[0094] Conductors 311-312 and 314-315 are coupled to power rails 211, 213, 216, and 218 via vias. Conductors 313, 322, and 327 are coupled to power rails 214-215 via vias. Conductors 321 and 326 are coupled to power rail 212 via vias, and conductors 323 and 328 are coupled to power rail 217 via vias. In some embodiments, conductors 320, 324, 325, and 329 are coupled to voltage VSS.

[0095] Power gate circuit 100A is coupled to power rail 212 via conductive line 321 and via, and to power rail 211 via conductive lines 311-312 and via. In some embodiments, power gate circuit 100A is coupled to conductive line 320. Similarly, power gate circuit 100B is coupled to power rail 212 via conductive line 326 and via, and to power rail 211 via conductive lines 314-315 and via. In some embodiments, power gate circuit 100B is coupled to conductive line 325. Power gate circuit 100C is coupled to power rail 217 via conductive line 323 and via, and to power rail 216 via conductive lines 311-312 and via. In some embodiments, power gate circuit 100C is coupled to conductive line 322. Power gate circuit 100D is coupled to power rail 217 via conductive line 328 and via, and to power rail 216 via conductive lines 314-315 and via. In some embodiments, the power gate circuit 100D is coupled to the conductive line 327.

[0096] In some embodiments, the conductive lines that couple the power gate circuit to the power rail with an external voltage (i.e., conductive lines 321, 323, 326, and 328) are shorter than the conductive lines that couple the power gate circuit to the power rail with the output power supply voltage (i.e., conductive lines 311-312 and 314-315).

[0097] For illustrative purposes, the following is given: Figure 8 The configuration is as follows. Various embodiments are within the scope of this invention. For example, in some embodiments, the number of power rails receiving external voltage TVDD (i.e., power rail 212) is greater than one, and the length of the conductive line coupled between the power gate circuit and the power rails receiving external voltage is related to the number of power rails. In an alternative embodiment, the power gate circuit 100 overlaps with power rail 213. In an alternative embodiment, the power gate circuit 100C overlaps with power rail 218 instead of power rail 216. In an alternative embodiment, the power gate circuit 100D is not coupled to conductive line 315.

[0098] For reference Figure 9 According to various embodiments, Figure 9 This is a layout diagram of a portion of the integrated circuit 80. Relative to... Figures 1A-8 The embodiments are provided for ease of understanding. Figure 9 Similar elements in the same text are assigned the same reference numerals. For the sake of brevity, unless otherwise specified... Figure 9 The cooperative relationships of the components shown are omitted here, as the specific operations of similar components discussed in detail above are not described.

[0099] Compared to Figure 8 The integrated circuit 80, rather than the power gate circuits 100A-100D, includes power gate circuits 200A-200D in the third layer. In some embodiments, for example, the power gate circuits 200A-200D are configured relative to... Figure 6 The power gate circuit 200.

[0100] Power rails 212 and 217 receive the external voltage TVSS, not the external voltage TVDD. Power rails 214-215 receive voltage VDD. Power rails 211, 213, 216, and 218 are configured to output a power supply voltage VSS corresponding to the external voltage TVSS.

[0101] In some embodiments, conductors 320, 324, 325, and 329 are coupled to the power supply VDD instead of the receiving voltage VSS.

[0102] Configuration of power gate circuit 200A-200D and Figure 8 The configuration of the power gate circuits 100A-100D is similar. Therefore, repeated descriptions are omitted here.

[0103] For illustrative purposes, the following is given: Figure 9 Configurations. Various embodiments are within the scope of this invention. For example, integrated circuit 80 includes fewer than four power gate circuits.

[0104] For reference Figure 10 According to various embodiments, Figure 10 This is a layout diagram of a portion of the integrated circuit 80. Relative to... Figures 1A-9 The embodiments are provided for ease of understanding. Figure 10 Similar elements in the same text are assigned the same reference numerals. For the sake of brevity, unless otherwise specified... Figure 10 The cooperative relationships of the components shown are omitted here, as the specific operations of similar components discussed in detail above are not described.

[0105] Compared to Figure 9 , Figure 10 Power rail 212 receives external voltage TVDD, not power rail 212 that receives external voltage TVSS.

[0106] Additionally, integrated circuit 80 includes conductive lines 312a-312c and 315a-315c but does not have conductive lines 312 and 315. For example... Figure 10 As shown, conductor 320 also crosses power rails 211-216. Conductor 321a overlaps with power rail 211, conductor 312b crosses power rail 212, and conductor 312c overlaps with conductors 213-218. Conductor 325 crosses power rails 211-216. Conductor 315a overlaps with power rail 211, conductor 315b crosses power rail 212, and conductor 315c overlaps with conductors 213-218.

[0107] For illustrative purposes, conductor 320 is coupled to power rails 214-215 via a via. Conductor 312b is coupled to power rail 212 via a via. Conductor 312c is coupled to power rails 216 and 218 via vias. Conductor 325 is coupled to power rails 214-215 via vias. Conductor 315c is coupled to power rail 212 via a via. Conductor 315c is coupled to power rails 216 and 218 via vias. In some embodiments, conductors 324 and 329 are coupled to voltage VDD, and conductors 312a and 315a are coupled to voltage VSS.

[0108] In addition, relative to Figure 9 The integrated circuit 80 also includes Figure 8 The power gate circuit 100A-100B does not have a power gate circuit 200A-200B.

[0109] Power gate circuit 100A is coupled to power rail 212 via conductive line 312b and via, and to power rails 214-215 via conductive lines 320 and 313. In some embodiments, power gate circuit 100A is coupled to conductive line 312a or power gate circuit 100A overlaps with and is coupled to conductive line 312c to receive voltage VSS from power gate circuit 200C. Accordingly, power gate circuit 100A is configured to output power supply voltage VDD to power rails 214-215. Similarly, power gate circuit 100B is coupled to power rail 212 via conductive line 315b and via, and to power rails 214-215 via conductive line 325 and via. In some embodiments, power gate circuit 100B is coupled to conductive line 315c to receive voltage VSS from power gate circuit 200D. Accordingly, the power gate circuit 100B is configured to output the power supply voltage VDD to the power rails 214-215.

[0110] Power gate circuit 200C is coupled to power rail 217 via conductive line 323 and via, and to power rails 216 and 218 via conductive lines 311 and 312c. In some embodiments, power gate circuit 200C is coupled to conductive line 320 to receive voltage VDD. Accordingly, power gate circuit 200C is configured to output power voltage VSS to power rails 216 and 218. Similarly, power gate circuit 200D is coupled to power rail 217 via conductive line 328 and via, and to power rail 218 via conductive lines 314 and 315c. In some embodiments, power gate circuit 200D overlaps with and is coupled to conductive line 325 to receive voltage VDD. Accordingly, power gate circuit 200D is configured to output power voltage VSS to power rail 218.

[0111] For illustrative purposes, the following is given: Figure 10 The configuration is as follows. Various embodiments are within the scope of this invention. For example, in some embodiments, the power gate circuit 200D overlaps with and is coupled to the power rail 216. In various embodiments, the power gate circuit 200C overlaps with the conductive line 324 to receive the voltage VDD.

[0112] For reference Figure 11 According to various embodiments, Figure 11 This is a flowchart of a method 1100 for operating integrated circuit 10 or 80. It should be understood that it is possible to... Figure 11 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or removed for additional embodiments of method 1100. Method 1100 includes the following Figure 4A and Figure 8Operations 1110-1140 are described above.

[0113] In operation 1110, the signal NSLEEPIN is transmitted via... Figure 8 The conductive trace 801 in the first layer of each of the power gate circuits 100A-100D is received.

[0114] In operation 1120, in response to the signal NSLEEPIN, Figure 8 The inverter (i.e., 110) of each of the power gate circuits 100A-100D generates an input signal IN and transmits the input signal IN to a transistor M1 in the second layer below the first layer. In some embodiments, the transistor M1 of each of the power gate circuits 100A-100D is turned on in response to the input signal IN.

[0115] In operation 1130, when the transistor M1 of each of the power gate circuits 100A-100D is turned on, the power gate circuits 100A-100D receive the external voltage TVDD from the power rails 212 and 217 through the conductive lines 321, 323, 326 and 328 in the third layer below the second layer.

[0116] In operation 1140, after receiving the external voltage TVDD, power gate circuits 100A-100D output the power supply voltage VDD to power rails 211, 213, 216, and 218 through conductive lines 311, 312, 314, and 315. Power gate circuits 100C-100D output the power supply voltage VDD to power rails 211, 213, 216, and 218 through conductive lines 311, 312, 314, and 315. In some embodiments, power rails 211-218 are arranged in a fourth layer below the third layer.

[0117] For reference Figure 12 According to various embodiments, Figure 11 This is a flowchart of a method 1200 for manufacturing integrated circuit 10 or 80. It should be understood that it is possible to... Figure 12 Additional operations are provided before, during, and after the process shown, and some of the operations described below may be replaced or removed for additional embodiments of method 1200. Method 1200 includes the following Figure 5A Operations 1210-1260 are described above.

[0118] In operation 1210, power rails 201-204 are formed in the first layer. Power rails 201-204 extend in the y-direction and are separated from each other in the x-direction. In some embodiments, power rails 202-203 are coupled to an external voltage (i.e., TVDD or TVSS), which is arranged below and coupled to power rails 202-203 via pins (not shown).

[0119] In operation 1220, conductive lines 301-305 are formed in a second layer above the first layer. Conductive lines 301-305 extend in the x-direction. As shown in... Figure 5A In the described embodiment, conductive line 303 is coupled to power rails 202-203, and conductive lines 301 and 305 are coupled to power rails 201 and 204.

[0120] In operation 1230, conductive portions 501-513 are formed above a plurality of active regions 401-409 in a third layer above the second layer. Active region 401 is coupled to conductive line 303 through vias VM1 and VM5 and to conductive lines 301 and 305 through vias VD3-VD4 and VD13-16.

[0121] In operation 1240, gates 602-612 are formed across active regions 401-109 and interspersed between conductive portions 501-515.

[0122] In operation 1250, conductive traces 701-706 are formed in a fourth layer above the third layer. Conductive traces 701-706 extend in the x-direction.

[0123] In operation 1260, a conductive pattern 801 is formed in a fifth layer above the fourth layer. The conductive pattern 801 extends in the y-direction and is coupled to conductive traces 702 and 704.

[0124] For reference Figure 13 According to some embodiments of the present invention, Figure 13 This is a block diagram of an Electronic Design Automation (EDA) system 1300 for designing integrated circuit layouts. The EDA system 1300 is configured to perform… Figures 11-12 The disclosed method 1100-1200 includes one or more operations, and further combines them. Figures 1A-10 This will be explained. In some embodiments, the EDA system 1300 includes an APR system.

[0125] In some embodiments, the EDA system 1300 is a general-purpose computing device that includes a hardware processor 1302 and a non-volatile computer-readable storage medium 1304. The storage medium 1304, among other uses, stores, i.e., computer program code (instructions) 1306, i.e., a set of executable instructions. The instructions 1306, executed by the software processor 1302, represent (at least partially) an EDA tool, for example, a portion or all of the EDA tool execution method 1200.

[0126] Processor 1302 is electrically coupled to computer-readable storage medium 1304 via bus 1308. Processor 1302 is also electrically coupled to input / output (I / O) interface 1310 and fabrication tool 1316 via bus 1308. Network interface 1313 is also electrically connected to processor 1302 via bus 1308. Network interface 1313 is coupled to network 1314, allowing processor 1302 and computer-readable storage medium 1304 to be coupled to external components via network 1314. Processor 1302 is configured to execute computer program code 1306 encoded in computer-readable storage medium 1304 to enable electronic design automation system 1300 to be used in part or all of the described process and / or method. In one or more embodiments, processor 1302 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0127] In one or more embodiments, the computer-readable storage medium 1304 is an electronic, magnetic, optical fiber, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1304 includes semiconductor or solid-state memory, magnetic tape, portable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1304 includes an optical disc read-only memory (CD-ROM), an optical disc read / write memory (CD-R / W), and / or a digital video optical disc (DVD).

[0128] In one or more embodiments, the storage medium 1304 storing the computer program code 1306 is configured to cause the electronic design automation system 1300 (wherein such execution represents (at least partially) electronic design automation tools) to be used to perform part or all of the described processes and / or methods. In one or more embodiments, the storage medium 1304 also stores information that helps to perform part or all of the described processes and / or methods. In one or more embodiments, the storage medium 1304 stores an IC layout diagram 1320 of standard cells, including the standard cells described herein, such as those with… Figures 1A-10The units corresponding to the multi-bit trigger circuits 31-36, 41-42, 61-63, 71-72, 91-93 and 101.

[0129] EDA system 1300 includes an I / O interface 1310. The I / O interface 1310 is coupled to external circuitry. In one or more embodiments, the I / O interface 1310 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 1302.

[0130] EDA system 1300 also includes a network interface 1313 coupled to processor 1302. Network interface 1313 allows EDA system 1300 to communicate with a network 1314 connected to one or more other computer systems. Network interface 1313 includes a wireless network interface such as Bluetooth, Wireless Local Area Network (WIFI), Access Control (WIMAX), General Packet Radio Service (GPRS), or Mobile Communications (WCDMA), or a wired network interface such as Ethernet, Universal Serial Bus (USB), or IEEE-1364. In one or more embodiments, some or all of the process and / or method are implemented in two or more systems 1300.

[0131] The electronic design automation system 1300 also includes a manufacturing tool 1316 coupled to the processor 1302. Based on design documents processed by the processor 1302, the manufacturing tool 1316 is configured to manufacture integrated circuits, for example... Figures 1A-10 The integrated circuits 10 and 80 are shown.

[0132] The EDA system 1300 is configured to receive information via I / O interface 1310. The information received via I / O interface 1310 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1302. The information is transferred to processor 1302 via bus 1308. The electronic design automation system 1300 is configured to receive information relating to the user interface (UI) via I / O output interface 1310. This information is stored as design specifications 1322 on computer-readable medium 1304.

[0133] In some embodiments, a portion or all of the process and / or method is implemented by a processor as an execution of a separate software application. In some embodiments, a portion or all of the process and / or method is implemented as a software application, which is part of an additional software application. In some embodiments, a portion or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application, which is part of an EDA tool. In some embodiments, a portion or all of the process and / or method is implemented as a software application, which is used by the EDA system 1300. In some embodiments, a layout diagram including standard cells is generated using a suitable layout generation tool.

[0134] In some embodiments, the processor functions as a program stored on a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), and semiconductor memories (e.g., ROMs, RAMs, and memory cards).

[0135] According to some embodiments, Figure 14 This is a block diagram of IC manufacturing system 1400 and its associated IC manufacturing process. In some embodiments, based on the layout diagram, IC manufacturing system 1400 is used to manufacture at least one of the following two: (A) one or more semiconductor masks, or (B) at least one element in a semiconductor integrated circuit layer.

[0136] exist Figure 14 In this system, manufacturing system 1400 includes entities such as design room 1420, mask room 1430, and IC manufacturer / fab (“fab”) 1450, which interact in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1460. The entities of IC manufacturing system 1400 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 are owned by a single entity. In some embodiments, two or more of design room 1420, mask room 1430, and IC fab 1450 coexist in a common facility and use common resources.

[0137] Design studio (or design team) 1420 generates IC design layout 1422. IC design layout 1422 includes various set patterns, for example, Figures 3A-10 The IC device 1460 shown is, for example Figures 3A-10 The integrated circuits 100 and 700 shown are designed using IC layout design. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1460 to be manufactured. The various layers are combined to form various IC components. For example, a portion of the IC design layout 1422 includes various IC components to be formed on a semiconductor substrate (such as a silicon wafer), such as active regions for interlayer interconnects, gate electrodes, source and drain electrodes, conductive portions or vias, and various metal layers disposed on the semiconductor substrate. Design room 1420 performs appropriate design processes to form the IC design layout 1422. The design processes include one or more of logic design, physical design, or placement and routing. The IC design layout 1422 exists in one or more data files containing information about the geometric patterns. For example, the IC design layout 1422 can be expressed in Layout Data (GDSII) file format or DFII file format.

[0138] Mask chamber 1430 includes data preparation 1432 and mask fabrication 1444. Mask chamber 1430 fabricates one or more masks 1445 using an IC design layout 1422 for fabricating various layers of an IC device 1460 according to the IC design layout 1422. Mask chamber 1430 performs mask data preparation 1432, where the IC design layout 1422 is translated into a representative data file (“RDF”). Mask data preparation 1432 provides the RDF to mask fabrication 1444. Mask fabrication 1444 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (intermediate mask) 1445 or a semiconductor wafer 1453. The IC design layout 1422 is manipulated by mask data preparation 1432 to comply with the specific performance requirements of the mask writer and / or the requirements of the IC fab 1450. Figure 14 In this context, data preparation 1432 and mask manufacturing 1444 are described as independent elements. In some embodiments, data preparation 1432 and mask manufacturing 1444 can be collectively referred to as mask data preparation.

[0139] In some embodiments, data preparation 1432 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image distortions, such as those caused by diffraction, interference, and other process effects. OPC adjusts the IC design layout diagram 1422. In some embodiments, data preparation 1432 also includes resolution enhancement techniques (RET), such as off-axis illumination, resolution-aided patterning, phase-shift masks, and other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0140] In some embodiments, data preparation 1432 includes a mask rule checker (MRC) that checks an IC design layout 1422 that has undergone processes in the OPC and has a set of mask generation rules. These rules include geometric and / or connectivity constraints to ensure sufficient space, taking into account variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1422 to compensate for limitations in mask fabrication 1444 devices. To satisfy the mask creation rules, this may involve removing some modifications performed by the OPC.

[0141] In some embodiments, data preparation 1432 includes a Lithography Process Check (LPC), a simulation of which is performed by the IC fab 1450 to fabricate an IC device 1460. The Lithography Process Check simulates this process based on the IC design layout 1422 to create a simulated fabricated device, such as the IC device 1460. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The Lithography Process Check takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), and other suitable factors, or combinations thereof. In some embodiments, after the simulated fabricated device has been created by the LPC, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the integrated circuit design layout 1422.

[0142] It should be understood that, for the sake of brevity, the foregoing description of data preparation 1432 has been simplified. In some embodiments, data preparation 1432 includes additional components, such as logic operations (LOPs), to modify the IC design layout 1422 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1422 during data preparation 1432 can be performed in various different sequences.

[0143] Following data preparation 1432 and during mask fabrication 1444, a mask 1445 or a set of masks 1445 is fabricated based on an IC design layout 1422. In some embodiments, mask fabrication 1444 includes performing one or more photolithographic exposures based on the IC design layout 1422. In some embodiments, a mechanism of electron beams (e-beams) or multiple electron beams is used to pattern the mask (photomask or intermediate mask) 1445 based on the modified IC design layout 1422. The mask 1445 can be formed using various techniques. In some embodiments, a binary stencil technique is used to form the mask 1445. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary intermediate mask of mask 1445 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1445 is formed using a phase-shifting technique. In a phase-shifting mask (PSM) version of mask 1445, various components in the pattern formed on the PSM are configured to have suitable phase differences to enhance resolution and imaging quality. In various examples, the phase-shifting mask may be a decaying PSM or an alternating PSM. One or more masks generated by mask fabrication 1444 are used in various processes. For example, such one or more masks are used in ion implantation processes to form various doped regions in semiconductor wafer 1453, in etching processes to form various etched regions in semiconductor wafer 1453, and / or in other suitable processes.

[0144] IC fab 1450 includes wafer fabrication 1452. IC fab 1450 is an IC manufacturing operation, which includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC fab 1450 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (FEOL) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (BEOL) for IC product interconnection and packaging, and a third manufacturing facility can provide other services for the foundry operation.

[0145] IC fab 1450 uses one or more masks 1445 fabricated in mask chamber 1430 to fabricate IC device 1460. Therefore, IC fab 1450 uses IC design layout 1422 at least indirectly to fabricate IC device 1460. In some embodiments, using mask 1445, semiconductor wafer 1453 is fabricated through IC fab 1450 to form IC device 1460. In some embodiments, IC fabrication includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1422. Semiconductor wafer 1453 includes a silicon substrate or other suitable substrate on which multiple material layers are formed. Semiconductor wafer 1453 also includes one or more of various doped regions, dielectric components, and multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0146] As discussed above, the integrated circuit of the present invention includes a power gate circuit disposed above the rear power distribution network. By directly receiving and outputting voltage through a power rail disposed below the power gate circuit, metal wiring resources on the front side of the integrated circuit are saved for subsequent connections. Consequently, integrated circuit design becomes possible.

[0147] In some embodiments, an integrated circuit is disclosed, comprising a first pair of power rails and a second pair of power rails disposed in a first layer and extending in a first direction; a plurality of conductive lines disposed in a second layer above the first layer, the conductive lines extending in a second direction different from the first direction and crossing the first and second pairs of power rails; a first active region disposed in a third layer above the second layer and extending in a second direction, the first active region being disposed overlapping the first pair of power rails; a first gate disposed above the first active region; and a conductive trace disposed above the first gate and coupled to the first gate. The first active region is coupled to the first pair of power rails through a first conductive line and a first set of vias in the conductive lines, and the first active region is coupled to a second pair of power rails through at least one third conductive line and a second set of vias different from the first set of vias. In some embodiments, the first active region and the first gate are configured to be included in a transistor, and the conductive trace is configured to receive an input signal for the first gate. In some embodiments, the integrated circuit further includes a first pair of active regions and a second pair of active regions extending in a second direction and separated from each other in a first direction, wherein the first pair of active regions and the second pair of active regions are arranged above a second pair of power rails; a second gate and a third gate extending in the first direction; and a first conductive portion and a second conductive portion, wherein the first conductive portion and the second gate cross the first pair of active regions, and the second conductive portion and the third gate cross the second pair of active regions. In some embodiments, one of the first pair of active regions and one of the second pair of active regions adjacent to each other have the same conductivity type as the first active regions. In some embodiments, the power rails of the second pair of power rails are arranged on opposite sides of the first pair of power rails. In some embodiments, the length of the first conductive line in the conductive lines is less than the length of at least one of the second conductive lines in the conductive lines, wherein the first conductive line is adjacent to at least one of the second conductive lines in the conductive lines. In some embodiments, the first active region includes a plurality of first active regions coupled to the first pair of power rails through a first set of vias and a plurality of second active regions coupled to the second pair of power rails through a second set of vias. In some embodiments, the conductive line further includes a third conductive line aligned with and separated from the first conductive line in the conductive line in a second direction.

[0148] An integrated circuit including a first transistor and a plurality of conductive lines is also disclosed. The first transistor includes a first active region; a plurality of first conductive portions and a plurality of second conductive portions, disposed in a first layer and above the first active region, wherein the first conductive portions correspond to the source of the first transistor and the second conductive portions correspond to the drain of the first transistor; and a plurality of first gates, corresponding to the gates of the first transistor, disposed above the first active region and interposed between a first conductive portion and a second conductive portion. A plurality of conductive lines are disposed in a second layer below the first active region, the conductive lines including first conductive lines and a plurality of second conductive lines. In response to an input signal received at the gate of the first transistor, the source of the first transistor is coupled to an external voltage through the first conductive lines, and the drain of the first transistor is coupled to a first power supply voltage through the second conductive lines. In some embodiments, the integrated circuit further includes at least one first power rail and at least one second power rail, disposed in a third layer below the second layer, wherein at least one first power rail transmits an external voltage to the first conductive line, and at least one second power rail receives the first power supply voltage from the second conductive line. In some embodiments, the first conductive line crosses at least one first power rail, and the second conductive line crosses the first conductive line and at least one second power rail. In some embodiments, a first active region is configured to receive current from at least one first power rail via a first conductive line and is configured to output current to at least one second power rail via a second conductive line. In some embodiments, the integrated circuit further includes a first inverter comprising a second transistor and a third transistor, the second and third transistors having gates to receive a first signal, the second transistor including a second active region overlapping the second conductive line, and the third transistor including a third active region; and a second inverter comprising a fourth transistor and a fifth transistor, the fourth and fifth transistors having gates to receive an input signal, the first transistor including another fourth active region overlapping the second conductive line, and the fifth transistor including a fifth active region. In some embodiments, the first, second, and fourth active regions have a first conductivity type, and the third and fifth active regions have a second conductivity type different from the first conductivity type. In some embodiments, the conductive line further includes a third conductive line, wherein the third and fifth active regions overlap with the third conductive line and are coupled to a second power supply voltage different from the first power supply voltage via the third conductive line.

[0149] A method is also disclosed, comprising the following operations: forming a plurality of power rails in a first layer, the power rails extending in a first direction and separated from each other in a second direction; forming a plurality of conductive lines in a second layer above the first layer, the conductive lines extending in the second direction; forming a plurality of active regions in a third layer above the second layer; forming a plurality of conductive portions above the plurality of active regions in the third layer, the first active region being coupled to a first conductive line and a second conductive line; forming a plurality of gates above the active regions, the gates being interposed between the conductive portions; forming a plurality of conductive traces in a fourth layer above the third layer, the conductive traces extending in the second direction; and forming a conductive pattern in a fifth layer above the fourth layer, the conductive pattern being coupled to the conductive traces. In some embodiments, forming the conductive lines includes coupling the first conductive line to a first power rail in the power rails and coupling the second conductive line to a second power rail in the power rails. In some embodiments, the first power rail is coupled to an external voltage, and the second power rail is coupled to a first power supply voltage. In some embodiments, the length of the first conductive line is less than the length of the second conductive line. In some embodiments, forming power rails includes forming a first power rail coupled to a first external voltage; forming a first pair of power rails coupled to the first power voltage and arranged on opposite sides of the first power rail; forming a second power rail coupled to a second external voltage; and forming a second pair of power rails coupled to the second power voltage and arranged on opposite sides of the first power rail. The voltage level of the first external voltage is different from the voltage level of the second external voltage.

[0150] The foregoing description of several embodiments enables those skilled in the art to better understand various aspects of the invention. Those skilled in the art should understand that the invention can be readily used as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit, comprising: a first pair of power rails and a second pair of power rails arranged in a first layer and extending in a first direction; a plurality of conductive lines arranged in a second layer above the first layer, wherein the plurality of conductive lines extend in a second direction different from the first direction and across the first pair of power rails and the second pair of power rails; a first active region arranged in a third layer above the second layer and extending in the second direction, wherein the first active region is disposed to overlap the first pair of power rails; a first gate arranged above the first active region; and a conductive trace arranged above and coupled to the first gate, wherein the first active region is coupled to the first pair of power rails through a first line of the plurality of conductive lines and a first set of vias, and the first active region is coupled to the second pair of power rails through at least a second conductive line of the plurality of conductive lines and a second set of vias different from the first set of vias.

2. The integrated circuit of claim 1, wherein, the first active region and the first gate are configured to be included in a transistor, and wherein the conductive trace is configured to receive an input signal for the first gate.

3. The integrated circuit of claim 1, further comprising: a first pair of active regions and a second pair of active regions extending in the second direction and separated from each other in the first direction, wherein the first pair of active regions and the second pair of active regions are arranged above the second pair of power rails; a second gate and a third gate extending in the first direction; and a first conductive portion and a second conductive portion extending in the first direction, wherein the first conductive portion and the second gate span the first pair of active regions, and the second conductive portion and the third gate span the second pair of active regions.

4. The integrated circuit of claim 3, wherein, one of the first pair of active regions and one of the second pair of active regions adjacent to each other have a same conductivity type different from a conductivity type of the first active region.

5. The integrated circuit of claim 1, wherein, a power rail of the second pair of power rails is arranged on an opposite side of the first pair of power rails.

6. The integrated circuit of claim 1, wherein, a length of the first line of the plurality of conductive lines is less than a length of at least a second line of the plurality of conductive lines, wherein the first line is adjacent to the at least a second line of the plurality of conductive lines.

7. The integrated circuit of claim 1, wherein, the first active region comprises: a plurality of first active regions coupled to the first pair of power rails through the first set of vias; and a plurality of second active regions coupled to the second pair of power rails through the second set of vias.

8. The integrated circuit of claim 1, wherein, the plurality of conductive lines further comprises a third conductive line aligned with the first line of the plurality of conductive lines and separated in the second direction.

9. An integrated circuit, comprising: a first transistor, comprising: a first active region; a plurality of first conductive portions and a plurality of second conductive portions arranged in a first layer and above the first active region, wherein the plurality of first conductive portions correspond to a source of the first transistor, and the plurality of second conductive portions correspond to a drain of the first transistor; and a plurality of first gates corresponding to gates of the first transistors above the first active region and interposed between one of the plurality of first conductive portions and one of the plurality of second conductive portions; and a plurality of conductive lines arranged in a second layer below the first active region, wherein the plurality of conductive lines includes a first conductive line and a plurality of second conductive lines; wherein, in response to an input signal received at the gate of the first transistor, the source of the first transistor is coupled to an external voltage through the first conductive line and the drain of the first transistor is coupled to a first supply voltage through the plurality of second conductive lines.

10. The integrated circuit of claim 9, further comprising: at least one first supply rail and at least one second supply rail arranged in a third layer below the second layer, wherein the at least one first supply rail transmits the external voltage to the first conductive line and the at least one second supply rail receives the first supply voltage from the plurality of second conductive lines.

11. The integrated circuit of claim 10, wherein, The first conductive line crosses the at least one first supply rail and the plurality of second conductive lines crosses the first conductive line and the at least one second supply rail.

12. The integrated circuit of claim 10, wherein, The first active region is configured to receive a current from the at least one first supply rail through the first conductive line and is configured to output the current to the at least one second supply rail through the plurality of second conductive lines.

13. The integrated circuit of claim 9, further comprising: a first inverter including a second transistor and a third transistor having gates to receive a first signal, wherein the second transistor includes a second active region overlapping the plurality of second conductive lines and the third transistor includes a third active region; a second inverter including a fourth transistor and a fifth transistor having gates to receive the input signal, wherein the fourth transistor includes a fourth active region overlapping another of the plurality of second conductive lines and the fifth transistor includes a fifth active region.

14. The integrated circuit of claim 13, wherein, The first, second, and fourth active regions have a first conductivity type and the third and fifth active regions have a second conductivity type different from the first conductivity type.

15. The integrated circuit of claim 13, wherein, The plurality of conductive lines further includes a third conductive line; wherein the third and fifth active regions overlap the third conductive line and are coupled to a second supply voltage different from the first supply voltage through the third conductive line.

16. A method of forming an integrated circuit, comprising: forming a plurality of supply rails in a first layer, wherein the plurality of supply rails extend in a first direction and are separated from each other in a second direction; forming a plurality of conductive lines in a second layer above the first layer, wherein the plurality of conductive lines extend in the second direction; forming a plurality of active regions in a third layer above the second layer; forming a plurality of conductive portions over the plurality of active regions, wherein a first active region of the plurality of active regions is coupled to at least a first conductive line and a second conductive line of the plurality of conductive lines; forming a plurality of gates over the plurality of active regions, the gates interposed between the plurality of conductive portions; forming a plurality of conductive traces in a fourth layer over the third layer, wherein the plurality of conductive traces extend in the second direction; and forming a conductive pattern in a fifth layer over the fourth layer, wherein the conductive pattern is coupled to the plurality of conductive traces.

17. The method of claim 16, wherein, forming the plurality of conductive lines includes: coupling the first conductive line to a first power rail of the plurality of power rails; and coupling the second conductive line to a second power rail of the plurality of power rails.

18. The method of claim 17, wherein, the first power rail is coupled to an external voltage, and the second power rail is coupled to a supply voltage.

19. The method of claim 17, wherein, a length of the first conductive line is less than a length of the second conductive line.

20. The method of claim 16, wherein, forming the plurality of power rails includes: forming a first power rail coupled to a first external voltage; forming a first pair of power rails coupled to a first supply voltage and arranged on opposite sides of the first power rail; forming a second power rail coupled to a second external voltage; and forming a second pair of power rails coupled to a second supply voltage and arranged on the opposite sides of the first power rail, wherein a voltage level of the first external voltage is different from a voltage level of the second external voltage.

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