Test instruction processing method and device, and electronic device

Abstract

Embodiments of the present application provide a test instruction processing method, device and electronic equipment, in which, in the generation process of a test program, if a virtual page meeting first preset requirements appears, the virtual page meeting the first preset requirements is determined as a master virtual page. Test instructions are generated for the master virtual page and written in. In the case where a virtual page meeting second preset requirements appears, the virtual page meeting the second preset requirements is determined as a slave virtual page of the master virtual page. Test instructions are written in the slave virtual page, and the master virtual page and the slave virtual page are mapped to the same physical page; wherein the test instructions written in the slave virtual page are consistent with the test instructions written in the master virtual page, and the page size of the slave virtual page is consistent with that of the master virtual page. In this way, the implementation cost is reduced to a certain extent, the locality of the test program is increased, and the verification coverage when using the test program to perform function verification is improved to a certain extent, and the convergence speed of the function verification work is improved.

Description

Technical Field

[0001] This invention relates to the field of network technology, and in particular to a test command processing method, apparatus, and electronic device. Background Technology

[0002] With the development of very large-scale integrated circuit (VLSI) technology, more and more functions are being integrated onto a single processor. Furthermore, the requirements for processor functionality are becoming increasingly complex, leading to continuous expansion of the processor's instruction set, a significant increase in the number and types of instructions, and correspondingly more complex functions. To meet these changing demands, processor design is becoming increasingly complex. Currently, to prevent processors from malfunctioning after deployment, test programs need to be generated to verify the processor's test instructions and detect functional design errors.

[0003] The test program may include a randomly generated instruction sequence and execution data (DATA) related to the simulated execution of the instructions (PC) on the verification platform (i.e., the processor under test). The generation of the test program involves mapping virtual addresses to physical addresses (virtual-to-physical address translation). Specifically, test instructions are generated and written to virtual pages during the test program generation process. Correspondingly, existing technologies often map virtual pages to physical pages one-to-one. This approach consumes significant physical storage resources and has a high implementation cost. Summary of the Invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a test instruction processing method that overcomes or at least partially solves the above problems.

[0005] Accordingly, embodiments of the present invention also provide a test instruction processing device, an electronic device, and a storage medium to ensure the implementation and application of the above method.

[0006] To address the aforementioned problems, this invention discloses a test instruction processing method applied to electronic devices, the method comprising:

[0007] During the generation of the test program, if a virtual page that meets the first preset requirement appears, the virtual page that meets the first preset requirement will be determined as the main virtual page.

[0008] Generate and write test instructions for the main virtual page;

[0009] If a virtual page that meets the second preset requirement appears, the virtual page that meets the second preset requirement is determined as the slave virtual page of the main virtual page;

[0010] Test instructions are written to the virtual page, and the main virtual page and the virtual page are mapped to the same physical page; wherein the test instructions written to the virtual page are the same as the test instructions written to the main virtual page, and the page size of the virtual page and the main virtual page are the same.

[0011] This invention also discloses a test instruction processing device applied to an electronic device, the device comprising:

[0012] The first determining module is used to determine the virtual page that meets the first preset requirements as the main virtual page if a virtual page that meets the first preset requirements appears during the generation of the test program.

[0013] The first writing module is used to generate and write test instructions for the main virtual page.

[0014] The second determining module is used to determine the virtual page that meets the second preset requirements as the slave virtual page of the main virtual page when a virtual page that meets the second preset requirements appears.

[0015] The second writing module is used to write test instructions to the slave virtual page and map the master virtual page and the slave virtual page to the same physical page; wherein the test instructions written in the slave virtual page are the same as the test instructions written in the master virtual page, and the page size of the slave virtual page and the master virtual page are the same.

[0016] This invention also discloses an electronic device including a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors, the one or more programs containing instructions for implementing the steps in the above method.

[0017] This invention also discloses a readable storage medium, wherein when the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is able to perform one or more of the methods described in this invention.

[0018] The embodiments of the present invention have the following advantages:

[0019] In this embodiment of the invention, during the generation of the test program, if a virtual page that meets the first preset requirement appears, it is determined as the primary virtual page. Test instructions are generated and written to the primary virtual page. If a virtual page that meets the second preset requirement appears, it is determined as a secondary virtual page of the primary virtual page. Test instructions are written to the secondary virtual page, and the primary and secondary virtual pages are mapped to the same physical page; wherein the test instructions written in the secondary virtual page are consistent with the test instructions written in the primary virtual page, and the page size of the secondary virtual page and the primary virtual page are consistent. In this way, by mapping multiple virtual pages that write test instructions to the same physical page during the generation of the test program, physical storage resources can be saved, and implementation costs can be reduced to a certain extent. At the same time, by mapping multiple virtual pages to the same physical page, the locality of the test program can be increased, thereby improving the verification coverage when using the test program for functional verification to a certain extent, and improving the convergence speed of functional verification work. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the steps of an embodiment of the test instruction processing method of the present invention;

[0021] Figure 2 This is a mapping diagram provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of a writing process provided in an embodiment of the present invention;

[0023] Figure 4 This is another writing schematic diagram provided by an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the spatial position relationship of a virtual page provided in an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of an exit strategy selection method provided by an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of a jump-out method provided by an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of a target address provided in an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram of an instruction provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram related to a conditional jump instruction provided in an embodiment of the present invention;

[0030] Figure 11This is a schematic diagram of a generation process provided by an embodiment of the present invention;

[0031] Figure 12 This is a structural block diagram of an embodiment of a test instruction processing device of the present invention;

[0032] Figure 13 This is a structural block diagram of an electronic device for testing instruction processing, according to an exemplary embodiment. Detailed Implementation

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Reference Figure 1 The diagram illustrates a flowchart of an embodiment of a test instruction processing method according to the present invention. This method can be applied to electronic devices and may specifically include the following steps:

[0035] Step 101: During the generation of the test program, if a virtual page that meets the first preset requirements appears, then the virtual page that meets the first preset requirements is determined as the main virtual page.

[0036] Step 102: Generate and write test instructions for the main virtual page.

[0037] Step 103: If a virtual page that meets the second preset requirements appears, the virtual page that meets the second preset requirements is determined as the slave virtual page of the main virtual page.

[0038] In this embodiment of the invention, since the operating system maps from the virtual address space to the physical address space on a page-by-page basis (the conversion between virtual and physical addresses), test instructions are generated and written to virtual pages on a page-by-page basis during the generation of the test program. Because the number of test instructions to be generated is large, new virtual pages are continuously activated during the generation process. For example, when a virtual page is about to complete instruction writing, a new virtual page is generated after a preset interval to activate that virtual page. Each activation of a virtual page can be considered as the appearance of a new virtual page.

[0039] Accordingly, if the virtual page that appears meets the first preset requirement, it can be determined as the master virtual page (MP). Correspondingly, test instructions can be generated for the master virtual page and written to it. In this embodiment, the test instructions can be random instructions. Alternatively, they can be dynamically generated by the generator based on a configuration file for the master virtual page. The instruction address of the generated test instructions can fall into the master virtual page. The instruction address can be the storage address of the instruction, indicating which address to store the instruction in.

[0040] Furthermore, in response to determining the primary virtual page, a multi-page mapping mechanism can be triggered. This multi-page mapping mechanism refers to a mechanism that maps multiple virtual pages to the same physical page. Accordingly, if a virtual page meeting the second preset requirement appears after the primary virtual page has been determined (i.e., when the multi-page mapping mechanism is triggered), then that virtual page can be designated as a slave page (SP) of the primary virtual page. Since a primary virtual page may have multiple slave virtual pages, a slave virtual page can also be represented as SPN, where N represents the order in which the slave virtual page appears. For example, assuming two slave virtual pages are determined sequentially for a certain primary virtual page, these two slave virtual pages can be SP1 and SP2, respectively.

[0041] The first and second preset requirements can be set according to actual needs. For example, the first preset requirement may be that the selected probability generated by the generator for the virtual page is greater than a preset probability threshold. Specifically, a configuration file can be pre-loaded before the generator starts working. This configuration file can specify the probability of the multi-page mapping mechanism being triggered during the test generation process, i.e., the preset probability threshold. At the moment a new virtual page is generated, the generator can generate a selected probability for the virtual page according to a preset random probability algorithm. If the selected probability is greater than the preset probability threshold, the virtual page meets the first preset requirement and is thus selected as the main virtual page. Further, the second preset requirement may also include that the selected probability generated by the generator for the virtual page is greater than the preset probability threshold; that is, the generator selects whether this virtual page will become a member of the multi-page mapping mechanism based on probability. Of course, the second preset requirement may also include other requirements, such as including that the virtual page is a newly generated virtual page; this invention does not limit this.

[0042] Step 104: Write test instructions to the secondary virtual page and map the primary virtual page and the secondary virtual page to the same physical page; the test instructions written in the secondary virtual page are consistent with the test instructions written in the primary virtual page, and the page size of the secondary virtual page and the primary virtual page are consistent.

[0043] The virtual page in this embodiment of the invention can also be called an instruction virtual page (PC virtual page). The timing of the operation of mapping the main virtual page and the secondary virtual page to the same physical page can be set according to actual needs, as long as it is ensured that the main virtual page and the secondary virtual page of the main virtual page are finally mapped to the same physical page when the test program is generated.

[0044] When multiple virtual pages map to the same physical page, during program execution, when the instruction sequence accesses several mapped virtual pages, it's equivalent to accessing the same physical page. Consequently, when the test program is executed, instruction fetching will focus on a small number of physical pages (physical address pages), increasing the locality of instruction fetching operations at actual physical addresses, and thus increasing the program's locality. Locality can include temporal locality and spatial locality. Temporal locality means that a memory location recently referenced during program execution is highly likely to be referenced multiple times later in the program's execution. Spatial locality means that if a memory location is referenced during program execution, locations near that memory location are highly likely to be referenced later in the program's execution. In other words, if a variable is referenced once during program execution, it is very likely to be referenced again later. And once a variable is accessed, locations near that variable are very likely to be accessed later in the program's execution.

[0045] Correspondingly, this means that instructions (data information) stored at the same offset value on different virtual pages with a mapping relationship must be consistent. Each page is a contiguous space with a start and an end. The start of a page is where the offset value is 0, and the end of the page has the largest offset value, which is related to the size of the page itself. In other words, the offset value is the position on the page.

[0046] For example, Figure 2 This is a mapping diagram provided by an embodiment of the present invention, such as... Figure 2 As shown, virtual page ①, virtual page ②, and virtual page ③ are mapped to the same physical page. Accordingly, Figure 2 The virtual pages ①, ②, and ③ store instruction sequence information, and all three pages store the same instruction sequence; that is, the test instructions written from the virtual pages are consistent with the test instructions written from the main virtual page. Furthermore, these three pages have the same page size, ensuring that there are identical offset positions between them. The identical offset position refers to positions with the same offset value. The virtual page selected first from virtual pages ①, ②, and ③ to participate in this multi-page mapping is the main virtual page. Subsequent virtual pages selected for participation in this multi-page mapping become the slave virtual pages of this main virtual page.

[0047] In summary, the test instruction processing provided in this embodiment of the invention, during the generation of the test program, if a virtual page meeting the first preset requirement appears, it is determined as the primary virtual page. Test instructions are generated and written to the primary virtual page. If a virtual page meeting the second preset requirement appears, it is determined as a secondary virtual page of the primary virtual page. Test instructions are written to the secondary virtual page, and the primary and secondary virtual pages are mapped to the same physical page; wherein the test instructions written in the secondary virtual page are consistent with those written in the primary virtual page, and the page sizes of the secondary and primary virtual pages are consistent. Thus, by mapping multiple virtual pages for writing test instructions to the same physical page during the generation of the test program, physical storage resources can be saved, reducing implementation costs to some extent. Simultaneously, by mapping multiple virtual pages to the same physical page, the locality of the test program can be increased, thereby improving the verification coverage and convergence speed of functional verification.

[0048] Optionally, the above steps for writing test instructions from a virtual page may specifically include:

[0049] Step 1041: For the offset position to be written in the slave virtual page, write the test command at the same offset position in the master virtual page as the offset position to be written to the offset position to be written in the slave virtual page.

[0050] Accordingly, the embodiments of the present invention may further include: step 21, if there is no test instruction at the same offset position in the main virtual page, then the secondary virtual page and the main virtual page are swapped, and a test instruction is generated and written for the offset position to be written in the main virtual page obtained after the swap.

[0051] The offset to be written can be the location from the virtual page where the test command needs to be written. The offset position in the main virtual page that is the same as the offset position to be written refers to the location in the main virtual page where the offset value is the same as the offset position to be written. The offset position to be written from the virtual page can include the offset position where the command begins to be written, the offset position where the command ends to be written, and the offset position in between.

[0052] Figure 3 This is a schematic diagram of a writing process provided in an embodiment of the present invention, such as... Figure 3As shown. Since MP pages and SP pages have a chronological order but no hierarchical relationship, in this embodiment of the invention, the virtual pages participating in this multi-page mapping can be named sequentially as "MP", "SP1", "SP2", ... based on the order in which different virtual pages appear in this multi-page mapping. These multiple virtual pages are mapped to the same physical page. Correspondingly, when the instruction fetch target address of the test program falls at the same position on these different virtual pages (i.e., positions with the same offset value), instructions are fetched from the same physical address page, requiring that the fetched instructions be exactly the same. Therefore, as... Figure 3 As shown, when generating instructions on SP1 and SP2, the corresponding instructions in MP can be read and completely copied to generate instructions, so that the instruction information already stored at the corresponding positions in SP1 and SP2 is exactly the same as that stored at the corresponding positions in MP.

[0053] It should be noted that in real-world applications, the position where the SP page is first written may not be the position where the MP page is first written. For example, Figure 4 This is a schematic diagram of a writing process provided in an embodiment of the present invention, such as... Figure 4 As shown, the instruction sequence stored on the SP page is a subset of the instruction sequence stored on the MP page. Therefore, in this embodiment of the invention, the consistency of instruction sequence information stored on different virtual pages specifically refers to the consistency of instructions stored at the same offset position.

[0054] Furthermore, swapping the slave virtual page and the master virtual page can mean using the slave virtual page as the master virtual page in this multi-page mapping, and using the original master virtual page as the slave virtual page. Correspondingly, since the program generator processes the slave virtual page, when it is used as the master virtual page in this multi-page mapping, test instructions can be generated and written to the offset position to be written in the swapped master virtual page (i.e., the original slave virtual page). The test instructions for the offset position to be written can be generated by the program generator according to a preset generation algorithm. In this way, by generating and writing test instructions for the offset position to be written, the slave virtual page can directly copy the test instructions for this offset position, thereby ensuring that the test instructions at the same offset position are consistent across all virtual pages mapped to the same physical page in this multi-page mapping.

[0055] It should be noted that in this embodiment of the invention, there are still locations on the MP page where no instructions are stored. During the instruction generation process, when the program first lands on a certain location on the SP page, but the corresponding location on the MP page has not yet been written with instructions, the roles of the SP page and the MP page are reversed when processing this instruction sequence. That is, on these different virtual pages mapped to the same physical address, the virtual space that is first written with instructions is considered the "Master segment virtual space" of the corresponding location space of other virtual pages, while the corresponding location space of other virtual pages can be called the "Slave segment space".

[0056] Optionally, embodiments of the present invention may further include the following steps:

[0057] Step 31: Obtain the maximum number of mappings from the pre-set configuration file.

[0058] Specifically, the generator can pre-read a configuration file. The configuration file can define the exact number of maximum mappings. Accordingly, the maximum number of mappings defined in the configuration file can be read directly. Alternatively, the configuration file can define a range for the maximum number of mappings, and the generator can randomly select a value from this range as the maximum number of mappings for this multi-page mapping. This maximum number of mappings represents how many virtual pages are allowed to map to the same physical page in this multi-page mapping.

[0059] Step 32: Take the physical page corresponding to the main virtual page as the target physical page. When the number of virtual pages of the target physical page reaches the maximum mapping number, stop mapping virtual pages to the target physical page and start writing test instructions to other virtual pages; the other virtual pages are virtual pages that are mapped one-to-one with physical pages.

[0060] In this context, the physical page corresponding to the primary virtual page is the physical page mapped to the primary virtual page. When mapping secondary virtual pages to the target physical page stops, the selection of new secondary virtual pages for that primary virtual page also stops. Other virtual pages can be referred to as Normal Pages (NPs). For example, an NP page can be a virtual page that does not meet the first and second preset requirements. For NP pages, a one-to-one mapping can be established between NP pages and physical pages; that is, one NP page occupies one physical page.

[0061] Furthermore, if the number of virtual pages of the current target physical page reaches the maximum number of mappings, the current multi-page mapping can be considered complete. Accordingly, we can wait for a virtual page that meets the first preset requirement to reappear, triggering the next multi-virtual page mapping mechanism, and then begin the next multi-page mapping. Specifically, after the current multi-page mapping has ended, test instructions can be generated and written for the NP page until a virtual page that meets the first preset requirement reappears, at which point the next multi-page mapping will begin.

[0062] It should be noted that during the generation of the test program, multiple multi-page mappings may occur, resulting in multiple primary virtual pages. The maximum number of mappings specifically refers to the maximum number of virtual pages that can be mapped from the physical page corresponding to the primary virtual page in the current multi-page mapping, rather than the total number of virtual pages participating in the mapping mechanism in the test program.

[0063] In this embodiment of the invention, by obtaining the maximum number of mappings, the number of virtual pages mapped to a physical page in multi-page mapping is controlled based on the maximum number of mappings. This avoids the problem of a single physical page being mapped to too many virtual pages.

[0064] Optionally, the above steps for generating and writing test instructions for the main virtual page may specifically include:

[0065] Step 1021: For the non-terminal address in the main virtual page, randomly generate a test instruction for the non-terminal address, and write the test instruction at the non-terminal address if the test instruction is not an instruction of a specified type; the specified type of instruction includes register jump instructions.

[0066] Step 1022: For the end address in the main virtual page, if there are other virtual pages that conform to a preset relationship with the main virtual page, then generate and write a test instruction of the sequential execution type for the end address; if there are no other virtual pages that conform to the preset relationship with the main virtual page, then generate and write a test instruction of the jump type for the end address; the preset relationship includes the other virtual pages being adjacent to the main virtual page and the first address of the other virtual pages not storing instructions.

[0067] In this embodiment of the invention, the end address can refer to the end position of the main virtual page, and the test instruction at the end address is the last instruction in the main virtual page. A non-end address refers to any position in the main virtual page other than the end position. If a test instruction of a different type is generated and written for a non-end address, since this will not cause the user to exit the main virtual page, test instructions can be randomly generated and written for non-end addresses, thus ensuring writing efficiency to a certain extent. If a test instruction is generated and written for the end address, test instructions need to be adaptively generated for the end address to control the exit strategy from the main virtual page, control the direction of instruction generation, and thus ensure that multi-page mapping can proceed normally. It should be noted that the exit strategy of the main virtual page needs to be determined based on whether there are other virtual pages that conform to a preset relationship with the main virtual page. Therefore, it is possible to determine in advance which virtual page will be mapped to the same physical page as other virtual pages; that is, first determine the secondary virtual page for the main virtual page, and then determine the exit strategy.

[0068] Specifically, if there are other virtual pages adjacent to the main virtual page whose starting address does not store instructions, a sequential jump can be performed, generating and writing a test instruction of sequential execution type to the ending address. If there are no other virtual pages adjacent to the main virtual page whose starting address does not store instructions, a jump instruction can be performed, generating and writing a test instruction of jump type to the ending address. The sequential execution type test instruction can be a sequential execution instruction, such as a summation instruction or a clear instruction. The jump type test instruction can be a jump instruction, such as a register jump instruction.

[0069] Of course, if there are other virtual pages adjacent to the main virtual page and whose starting address does not store instructions, one can randomly choose between sequential exit and exit via jump instructions. This embodiment of the invention does not limit this.

[0070] It should be noted that in the sequential jump method, it is possible to control that the instruction addresses of all generated instructions on the MP page from the beginning to the end fall on the MP page, the last instruction falls at the end of the MP page, and the instructions are executed sequentially. Figure 5 This is a schematic diagram of the spatial positional relationship of a virtual page provided in an embodiment of the present invention, such as... Figure 5 As shown, the spatial relationship between the MP page and the NP page is as follows: they are adjacent, and the instruction stored at the beginning of the NP page (0x10) is generated immediately after the instruction at the end of the MP page (0xc). Each instruction has a size; assuming the instruction code consists of 32 bits (4 bytes), the first instruction occupies a space range of "0x0-0x4" within the page. Therefore, when determining whether the MP page uses a sequential jump method, it is necessary to ensure that the beginning address of the adjacent NP page has not yet stored any instructions.

[0071] Optionally, the above steps of generating and writing a test instruction of the jump type for the terminal address may specifically include:

[0072] Step 1022a: Generate a jump instruction for the terminal address that uses a specified register and whose target address falls into a specified transfer space, and write it to the terminal address; wherein, the specified register is a pre-set register for use by the jump instruction for the terminal address.

[0073] Jump instructions can be divided into register jump instructions and immediate jump instructions. Immediate jump instructions are also called immediate addressing instructions (Class B jump instructions). Register jump instructions are also called register addressing instructions (Class J jump instructions). The target address of a Class B jump instruction is calculated as: current PC + immediate value. The target address of a Class J jump instruction is calculated as: register value + immediate value. The immediate value is the operand.

[0074] In this embodiment of the invention, the jump instruction can specifically be a register jump instruction. The operation of continuing to write instructions on the MP page can be terminated by selecting a target address outside the MP page range (i.e., falling into a specified transfer space). Specifically, the target address of the jump instruction can be constrained to a certain memory space (i.e., a specified transfer space) through an instruction bundling generation method. Figure 6 This is a schematic diagram of an exit strategy selection method provided by an embodiment of the present invention, such as... Figure 6 As shown, for different situations, an adaptive selection of either a sequential exit strategy or a J-exit strategy is used. Finally, the instruction writing can be completed through a transfer space.

[0075] Furthermore, in this embodiment of the invention, a specified jump instruction can be inserted into the transit space; the specified jump instruction is used to jump out of the transit space to the NP page, so as to control the generator to continue generating and writing test instructions for the NP page. Figure 7 This is a schematic diagram of a jump-out method provided by an embodiment of the present invention, such as... Figure 7 As shown, a jump instruction (J) can be used to jump from the MP page to the intermediate space. Then, a specified jump instruction can be used to jump back from the intermediate space to the NP page. Thus, as long as the intermediate space is not written to by other instructions, it can be used only when jumping out of the MP and SP pages.

[0076] Furthermore, since the target address of a jump instruction is related to registers and immediate values, in this embodiment of the invention, a dedicated register (i.e., the designated register) is reserved for jump instructions that jump out of the MP page. This ensures that the target address of the jump instruction falls within a designated transfer space. It should be noted that the value of this designated register cannot be randomly modified (it can only be modified by inserting instructions as needed). Figure 8 This is a schematic diagram of a target address provided in an embodiment of the present invention, such as... Figure 8 As shown, assuming the initial value of register reg1 is 0x0 and imm is 0x0, in page MP, after the instruction Addi(reg1=reg1+0x8), the value in register reg1 becomes 0x8. Therefore, the jump target address of the J instruction is 0x8. When writing instructions to SP1, the instruction information needs to be consistent with the same location in MP. Therefore, Addi and J instructions will also appear. As long as register reg1 is not modified by other instructions, the target address of the J instruction in SP1 is 0x10, and similarly, the target address of J in SP2 is 0x18. It can be seen that the addresses that jump out of pages MP and SP are constrained within a contiguous transfer space, and the empty addresses in between (such as 0xc) can be used to insert appropriate jump instructions to reselect page NP and return to the random instruction generation process. This contiguous space is protected as a transfer space, and storage of other cases except for jumping out of pages MP and SP is not allowed.

[0077] Optionally, embodiments of the present invention may further include:

[0078] Step 41: If the test instruction generated for the non-terminal address is a register jump instruction, cancel the test instruction and regenerate the test instruction for the non-terminal address.

[0079] Alternatively, in step 42, if the test instruction generated for the non-terminal address is another instruction included in the specified type of instruction, cancel the test instruction and regenerate the test instruction for the non-terminal address; or, bind an operand modification instruction to the test instruction to make the operand of the test instruction valid; write the operand modification instruction and the test instruction sequentially into the main virtual page based on the non-terminal address.

[0080] In this embodiment of the invention, when the generator generates instructions, there may be instances where the generated instructions are illegal under certain circumstances (the results are random and unpredictable, therefore impossible to compare through simulation; for example, the result of a division instruction is unpredictable when the divisor is zero). Such instructions that may exhibit illegal behavior can be called UPI (Unpredictable Instruction) instructions. Accordingly, the generator can impose certain constraints on the selection of instruction operands when generating instructions. The specified type of instruction is the UPI instruction. The specified type of instruction can include register jump instructions, division instructions, and modulo instructions. If the test instruction generated for the non-terminal address is a register jump instruction, a division instruction, or a modulo instruction, then the test instruction generated for the non-terminal address can be determined to be an instruction of the specified type.

[0081] During instruction generation on the MP page, the selection of registers with valid values ​​(appropriate operands) can be controlled. However, during instruction generation on the SP page, because the instruction sequence information must be completely consistent with that on the MP page at the same offset, the registers used by all instructions cannot be changed. However, as the test program is generated and executed, the values ​​in the registers are continuously rewritten. Therefore, when writing instructions to the SP page, illegal UPI instructions are likely to occur.

[0082] Therefore, in this embodiment of the invention, if the test instruction is a register jump instruction, the generation of the UPI instruction on the MP page can be directly cancelled. That is, the generated UPI instruction can be cancelled, and a new test instruction can be generated and written to the non-terminal address. In this way, by directly cancelling, processing efficiency can be ensured to a certain extent. At the same time, the generation of register jump instructions at non-terminal addresses is not allowed. Specifically, if the regenerated test instruction is not an instruction of a specified type, the test instruction can be written at the non-terminal address; otherwise, regeneration continues.

[0083] Furthermore, if the test instruction generated for a non-terminal address is one of the instructions included in the specified type, cancellation can be used. This direct cancellation ensures processing efficiency to some extent. Alternatively, UPI instructions and operand modification instructions that change their operands can be bundled together to ensure operand validity. Specifically, different instructions can be inserted for different UPI instructions. That is, UPI instructions always appear in the form of an instruction sequence. In this embodiment of the invention, by bundling operand modification instructions, it is possible to generate and write test instructions of the specified type for MP pages, thereby ensuring the comprehensiveness of subsequent verification work to some extent.

[0084] Specifically, invalid instructions often arise because the register values ​​(operands) used by the UPI instruction are inappropriate. Therefore, ensuring the operands used by the UPI instruction are valid is sufficient. Accordingly, in this embodiment of the invention, by bundling operand modification instructions and sequentially writing the operand modification instructions and test instructions into the main virtual page based on a non-terminal address, the operands of the test instruction can be made valid. The operand modification instructions can be used to change the operands of the test instruction to valid values. Specifically, writing the operand modification instructions and test instructions into the main virtual page based on a non-terminal address can be done by starting with the non-terminal address, writing the operand modification instructions first, and then writing the test instruction. That is, there is always an instruction that modifies the register value of this UPI instruction immediately before the UPI instruction, ensuring that its register value is valid when the program reaches that UPI instruction. Figure 9 This is a schematic diagram of an instruction provided in an embodiment of the present invention, such as... Figure 9As shown, a UPI instruction is preceded by a UPI register modification instruction. Specifically, this UPI register modification instruction modifies the register value of the UPI instruction to make its operands valid.

[0085] Different UPI instruction types require different processing strategies. UPI instructions can be broadly categorized into two types: register jump instructions and division / modulo instructions. Division / modulo instructions can also be referred to as Class D instructions.

[0086] For register jump instructions, the target address is defined as "the value in the register + the immediate value". If the value of the register being used is changed, the target address becomes uncontrollable and may fall on an address where the instruction has already been stored. Therefore, for register jump instructions, the processing method in step 41 can be adopted, that is, register jump instructions are not allowed to be generated at non-terminal addresses.

[0087] For Class D instructions, the instruction is illegal when the divisor is zero. Therefore, when writing a Class D instruction on the MP page, an operand modification instruction can be inserted before the Class D instruction. This operand modification instruction can be used to "OR" a non-zero value onto the register value (i.e., the divisor) of the Class D instruction to modify the divisor. This ensures that when this instruction is generated on the SP page based on the instruction sequence on the MP page, there will always be an instruction before it that writes the divisor to a non-zero value, thus ensuring that the Class D instruction is legal.

[0088] Optionally, before writing the test instruction at the non-terminal address, the embodiments of the present invention may further include:

[0089] Step 501: If the test instruction is an immediate jump instruction, then check whether the jump address of the immediate jump instruction falls into the main virtual page;

[0090] The operation of writing the test instruction at the non-terminal address described above may specifically include:

[0091] Step 1021a: If the jump address of the immediate jump instruction falls within the main virtual page, and if the immediate jump instruction is a direct jump type, then the test instruction is written at the non-terminal address; if the immediate jump instruction is a conditional jump type, and if the immediate jump instruction meets the jump condition, then the jump address is set as the next address to be written, the specified address is set as a reserved position, and the test instruction is written at the non-terminal address; if the conditional jump instruction does not meet the jump condition, then the specified address is set as the next address to be written, the jump address is set as a reserved position, and the test instruction is written at the non-terminal address; the specified address is the next instruction address after the instruction address of the immediate jump instruction.

[0092] Here, "next address to be written" can refer to the address of the next instruction to be generated, i.e., the address of the next instruction to be generated. The jump address of an immediate jump instruction can be the address of the immediate jump instruction plus the immediate value `imm`, which can be represented as `PC+imm`. The address of the instruction following the address of an immediate jump instruction can be the address of the immediate jump instruction plus the length of the instruction itself (e.g., 4), i.e., the address of the instruction following the address of an immediate jump instruction can be represented as `PC+4`. Reserved locations can refer to locations where instruction generation is prohibited. Thus, by setting reserved locations, the generator can prevent writing instructions to those reserved locations.

[0093] In this embodiment of the invention, random jumps are not allowed from the start of writing the MP page to the control of jumping out of the MP page. That is, constraints need to be added when generating jump instructions. For J-type jump instructions, they are only allowed to be generated at the end address. For non-end addresses, immediate jump instructions can be generated. Immediate jump instructions are further divided into conditional jumps and direct jumps. Direct jump instructions will always result in a jump, while conditional jump instructions determine whether a jump occurs based on the current internal state of the processor (register values). If no jump occurs, the address of the next instruction in the conditional jump instruction is the same as that of sequentially executed instructions, which can be "current instruction address + 4".

[0094] Immediate jump instructions of the direct jump type jump from their own address to the current address, and the jump distance depends on the size of the immediate value. Therefore, for immediate jump instructions of the direct jump type, it is only necessary to ensure that the target address falls within the current MP page. This avoids illegal situations.

[0095] The immediate jump instruction of the conditional jump type has two possible paths (jump / no jump). Although a jump may occur when generated on the MP page, the condition may not be met when generated on the SP page, and no jump may occur. Therefore, it is necessary to handle the two cases of jump and no jump separately. Figure 10 This is a schematic diagram related to a conditional jump instruction provided in an embodiment of the present invention, such as... Figure 10 As shown in Figure a, when the jump condition is not met, the instruction generation direction is "①", and when the jump condition is met, the instruction generation direction is "②". Therefore, when generating the conditional jump instruction at the PC position, both the "PC+4" and "PC+imm" positions can be considered in this embodiment of the invention. Specifically, a reserved space approach can be adopted. If the jump condition is met, the instruction is written to the "PC+imm" position, and the position of "PC+4" on the MP page is recorded as reserved space, preventing other instructions from writing. Correspondingly, the same position on the SP page can also be reserved. That is, the jump address is set as the next address to be written, and the specified address is set as a reserved position. In this way, when the immediate jump instruction on the SP page does not meet the jump condition, it can be guaranteed that there is no instruction at the target address, and the program can be generated normally. Conversely, if the condition is met, the instruction is written to the "PC+4" position, and the position of "PC+imm" on the MP page is recorded as reserved space, preventing other instructions from writing. That is, the specified address is set as the next address to be written, and the jump address is set as a reserved position. It should be noted that when conditional jump instructions from the MP page are repeatedly generated in the SP page, if changes in register state cause the jump behavior to fall into a reserved location, writing instructions to the reserved location in the SP page is permitted. Specifically, the instructions can be generated and written normally. Alternatively, a direct jump instruction can be selected to return to the original address to continue generating instructions on the SP page. For example, it can be done as follows: Figure 10 The direction indicated by "③" in b will jump back to the original position PC+4.

[0096] In this embodiment of the invention, during the implementation of mapping multiple virtual pages to the same physical page, the selection of instruction types and the direction of program generation are controlled. By controlling the generation direction of instruction types and instruction sequences generated in the MP page, the legality of subsequent instructions generated on the SP page can be guaranteed to a certain extent.

[0097] The following describes a specific application scenario related to an embodiment of the present invention. In the field of microprocessors, the functional requirements for microprocessors are becoming increasingly complex. To meet these changing demands, processor designs are becoming increasingly complex, and processor functional verification is extremely complex and time-consuming, inevitably impacting processor development time. Furthermore, it is not uncommon for design errors to be discovered after processor chips have been released to the market. Therefore, the generation of random instruction verification programs, as a crucial step in the microprocessor functional verification process, has received widespread attention.

[0098] Figure 11 This is a schematic diagram of a generation process provided by an embodiment of the present invention, such as... Figure 11 As shown, a jump strategy can be determined for the MP page. Specifically, the final jump strategy can be determined based on the processor's internal state, i.e., the relevant information about the virtual page. Next, instructions are generated and written to the MP page. During instruction generation on the MP, it is necessary to control the type of instruction (e.g., not randomly generating J-type instructions, only generating J-type instructions at the end position, etc.) and to take corresponding processing measures according to different instruction types (e.g., bundling UPI instructions, reserving space for immediate jump instructions, etc.).

[0099] Specifically, the instruction generation direction can be selected based on the jump strategy. For a sequential jump strategy, it can be guaranteed that instructions are generated to the end of the MP page, and that instructions at this position are executed sequentially. For a J-type jump instruction jump strategy, a J-type jump instruction can be inserted to jump out of the MP page at any time while writing instructions on the MP page.

[0100] Furthermore, after exiting the MP page, instructions can be randomly generated on the NP page, awaiting the triggering of the SP1 write mechanism. If the SP1 write mechanism is triggered, the virtual page to be used as SP1 can be selected. Then, instructions are fetched from the corresponding position in MP based on the current address in SP1 and written to SP1. Space reservation is performed for conditional jump instructions. Because the instruction sequence is generated entirely according to the MP page, SP1 can ultimately exit using the same exit strategy as MP. Further, after exiting SP1, instructions can be randomly generated on the NP page, awaiting the triggering of the SP2 write mechanism, and so on, until the number of virtual pages mapped to the same physical page reaches the maximum mapping limit. Then, it can jump back to the NP page and begin randomly generating instructions, waiting for the next multi-page mapping to be triggered.

[0101] It should be noted that both instruction pages and data pages in the test program can undergo virtual-physical address mapping. Specifically, the instruction page corresponding to the test program can be a storage page used to store the instructions in the test program, and the data page corresponding to the test program can be a storage page used to store the data in the test program. The data can be the operations required during instruction execution; for example, the data can be the data required for operations by a memory access instruction. That is, multiple data pages can also be mapped to the same physical page, and this embodiment of the invention does not impose any limitations on this.

[0102] Furthermore, the essence of mapping multiple virtual pages to the same physical page is that when a program accesses these virtual pages, the physical page it reads is the same physical page. When this mapping occurs for data pages, accessing different virtual pages only requires ensuring that the memory access operation is on a single physical page. That is, it only requires controlling that the same data is stored at the same offset position in each virtual page, without needing to control the specific data stored on the virtual page. In other words, the strategy of mapping multiple virtual pages of data pages to a single physical page is part of the strategy of mapping multiple virtual pages of instruction pages to the same physical page.

[0103] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0104] Reference Figure 12 The diagram illustrates a structural block diagram of an embodiment of a test instruction processing device according to the present invention, which is applied to an electronic device and may specifically include the following modules:

[0105] The first determining module 301 is used to determine the virtual page that meets the first preset requirements as the main virtual page if a virtual page that meets the first preset requirements appears during the generation of the test program.

[0106] The first writing module 302 is used to generate and write test instructions for the main virtual page.

[0107] The second determining module 303 is used to determine the virtual page that meets the second preset requirements as the slave virtual page of the main virtual page when a virtual page that meets the second preset requirements appears.

[0108] The second writing module 304 is used to write test instructions to the slave virtual page and map the master virtual page and the slave virtual page to the same physical page; wherein the test instructions written in the slave virtual page are the same as the test instructions written in the master virtual page, and the page size of the slave virtual page and the master virtual page are the same.

[0109] Optionally, the first writing module 302 is specifically used for:

[0110] For non-terminal addresses in the main virtual page, a test instruction is randomly generated for the non-terminal address, and if the test instruction is not a specified type of instruction, the test instruction is written at the non-terminal address; the specified type of instruction includes register jump instructions.

[0111] For the final address in the main virtual page, if there are other virtual pages that conform to a preset relationship with the main virtual page, a test instruction of the sequential execution type is generated for the final address and written; if there are no other virtual pages that conform to the preset relationship with the main virtual page, a test instruction of the jump type is generated for the final address and written; the preset relationship includes the other virtual pages being adjacent to the main virtual page and the first address of the other virtual pages not storing instructions.

[0112] Optionally, the device further includes:

[0113] The cancellation module is used to cancel the test instruction and regenerate the test instruction for the non-terminal address if the test instruction generated for the non-terminal address is a register jump instruction.

[0114] The modification module is configured to, if the test instruction generated for the non-terminal address is another instruction included in the specified type of instruction, cancel the test instruction and regenerate the test instruction for the non-terminal address, or, bind an operand modification instruction to the test instruction to make the operand of the test instruction valid; and write the operand modification instruction and the test instruction sequentially to the main virtual page based on the non-terminal address.

[0115] Optionally, the first writing module 302 is further specifically used for:

[0116] Generate a jump instruction for the terminal address that uses a specified register and whose target address falls into a specified transfer space, and write it to the terminal address;

[0117] The designated register is a pre-configured register used by the jump instruction at the end address.

[0118] Optionally, the device further includes:

[0119] The acquisition module is used to obtain the maximum number of mappings from a pre-set configuration file;

[0120] The stop module is used to take the physical page corresponding to the main virtual page as the target physical page, and when the number of virtual pages of the target physical page reaches the maximum mapping number, stop mapping the virtual pages to the target physical page and start writing test instructions to other virtual pages; the other virtual pages are virtual pages that are mapped one-to-one with physical pages.

[0121] Optionally, the second writing module 304 is specifically used for:

[0122] For the offset position to be written in the slave virtual page, the test instruction at the same offset position in the master virtual page as the offset position to be written is written to the offset position to be written in the slave virtual page;

[0123] The device further includes: a swapping module, configured to swap the slave virtual page with the main virtual page if no test instruction is present at the same offset position in the main virtual page, and generate and write a test instruction for the offset position to be written in the main virtual page obtained after the swap.

[0124] Optionally, before writing the test instruction at the non-terminal address, the device further includes: a detection module, configured to detect whether the jump address of the immediate jump instruction falls into the main virtual page if the test instruction is an immediate jump instruction;

[0125] The first writing module 302 is also specifically used for:

[0126] If the jump address of the immediate jump instruction falls into the main virtual page, and if the immediate jump instruction is a direct jump type, then the test instruction is written at the non-terminal address.

[0127] If the immediate jump instruction is a conditional jump type, then if the immediate jump instruction meets the jump condition, the jump address is set to the next address to be written, the specified address is set to a reserved position, and the test instruction is written at the non-terminal address; if the conditional jump instruction does not meet the jump condition, the specified address is set to the next address to be written, the jump address is set to a reserved position, and the test instruction is written at the non-terminal address; the specified address is the address of the instruction following the instruction address of the immediate jump instruction.

[0128] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0129] Figure 13 This is a structural block diagram illustrating an electronic device for processing test instructions, according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0130] Reference Figure 13 The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0131] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0132] Memory 404 is configured to store various types of data to support the operation of device 400. Examples of this data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0133] Power component 404 provides power to various components of electronic device 400. Power component 404 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0134] Multimedia component 408 includes a screen that provides an output interface between the electronic device 400 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When the electronic device 400 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0135] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0136] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0137] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0138] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 414 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 414 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0139] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0140] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0141] A non-transitory computer-readable storage medium, wherein instructions in the storage medium, when executed by a terminal's processor, enable the terminal to perform the methods described above.

[0142] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0143] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0144] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0145] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0146] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0147] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0148] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0149] The present invention has provided a detailed description of a test instruction processing method and apparatus, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A test instruction processing method, characterized in that, Applied to electronic devices, the method includes: During the generation of the test program, if a virtual page that meets the first preset requirement appears, the virtual page that meets the first preset requirement will be determined as the main virtual page. Generate and write test instructions for the main virtual page; If a virtual page that meets the second preset requirement appears, the virtual page that meets the second preset requirement is determined as the slave virtual page of the main virtual page; Test instructions are written to the virtual page, and the main virtual page and the virtual page are mapped to the same physical page; wherein the test instructions written to the virtual page are the same as the test instructions written to the main virtual page, and the page size of the virtual page and the main virtual page are the same; The step of generating and writing test instructions for the main virtual page includes: For non-terminal addresses in the main virtual page, a test instruction is randomly generated for the non-terminal address, and if the test instruction is not an instruction of a specified type, the test instruction is written at the non-terminal address; the specified type of instruction includes register jump instructions. For the final address in the main virtual page, if there are other virtual pages that conform to a preset relationship with the main virtual page, a test instruction of the sequential execution type is generated for the final address and written; if there are no other virtual pages that conform to the preset relationship with the main virtual page, a test instruction of the jump type is generated for the final address and written; the preset relationship includes the other virtual pages being adjacent to the main virtual page and the first address of the other virtual pages not storing instructions.

2. The method according to claim 1, characterized in that, The method further includes: If the test instruction generated for the non-terminal address is a register jump instruction, cancel the test instruction and regenerate the test instruction for the non-terminal address; If the test instruction generated for the non-terminal address is another instruction included in the specified type, cancel the test instruction and regenerate the test instruction for the non-terminal address; or, bind an operand modification instruction to the test instruction to make the operand of the test instruction valid; write the operand modification instruction and the test instruction sequentially to the main virtual page based on the non-terminal address.

3. The method according to claim 1, characterized in that, The step of generating and writing a test instruction of the jump type for the terminal address includes: Generate a jump instruction for the terminal address that uses a specified register and whose target address falls into a specified transfer space, and write it to the terminal address; The designated register is a pre-configured register used by the jump instruction at the end address.

4. The method according to claim 1, characterized in that, The method further includes: Get the maximum number of mappings from the pre-set configuration file; The physical page corresponding to the main virtual page is taken as the target physical page. When the number of virtual pages of the target physical page reaches the maximum mapping number, the mapping of virtual pages to the target physical page stops, and test instructions are written to other virtual pages. The other virtual pages are virtual pages that are mapped one-to-one with physical pages.

5. The method according to claim 1, characterized in that, The aforementioned writing test instructions from the virtual page includes: For the offset position to be written in the slave virtual page, the test instruction at the same offset position in the master virtual page as the offset position to be written is written to the offset position to be written in the slave virtual page; The method further includes: if there is no test instruction at the same offset position in the main virtual page, then the secondary virtual page and the main virtual page are swapped, and a test instruction is generated and written for the offset position to be written in the main virtual page obtained after the swap.

6. The method according to claim 1, characterized in that, Before writing the test instruction at the non-terminal address, the method further includes: if the test instruction is an immediate jump instruction, then detecting whether the jump address of the immediate jump instruction falls into the main virtual page; Writing the test instruction at the non-terminal address includes: If the jump address of the immediate jump instruction falls into the main virtual page, and if the immediate jump instruction is a direct jump type, then the test instruction is written at the non-terminal address. If the immediate jump instruction is a conditional jump type, then if the immediate jump instruction meets the jump condition, the jump address is set to the next address to be written, the specified address is set to a reserved position, and the test instruction is written at the non-terminal address; if the conditional jump instruction does not meet the jump condition, the specified address is set to the next address to be written, the jump address is set to a reserved position, and the test instruction is written at the non-terminal address; the specified address is the address of the instruction following the instruction address of the immediate jump instruction.

7. A test instruction processing device, characterized in that, Applied to electronic devices, the device includes: The first determining module is used to determine the virtual page that meets the first preset requirements as the main virtual page if a virtual page that meets the first preset requirements appears during the generation of the test program. The first writing module is used to generate and write test instructions for the main virtual page. The second determining module is used to determine the virtual page that meets the second preset requirements as the slave virtual page of the main virtual page when a virtual page that meets the second preset requirements appears. The second writing module is used to write test instructions to the slave virtual page and map the master virtual page and the slave virtual page to the same physical page; wherein the test instructions written in the slave virtual page are the same as the test instructions written in the master virtual page, and the page size of the slave virtual page and the master virtual page are the same; Specifically, the first writing module is used for: For non-terminal addresses in the main virtual page, a test instruction is randomly generated for the non-terminal address, and if the test instruction is not an instruction of a specified type, the test instruction is written at the non-terminal address; the specified type of instruction includes register jump instructions. For the final address in the main virtual page, if there are other virtual pages that conform to a preset relationship with the main virtual page, a test instruction of the sequential execution type is generated for the final address and written; if there are no other virtual pages that conform to the preset relationship with the main virtual page, a test instruction of the jump type is generated for the final address and written; the preset relationship includes the other virtual pages being adjacent to the main virtual page and the first address of the other virtual pages not storing instructions.

8. An electronic device, characterized in that, It includes a memory and one or more programs, wherein one or more programs are stored in the memory and configured to be executed by one or more processors. The one or more programs include instructions for implementing the steps of the method as described in any one of claims 1-6.

9. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method as described in any one of claims 1-6.

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