A pseudo-random frequency agility implementation method based on multi-loop flow operation

Abstract

This invention relates to a pseudo-random frequency agility implementation method based on multi-loop continuous operation. The frequency synthesizer controller controls the output / setting of the i-th frequency point of the i-th loop in the first phase-locked loop (PRF) during the first phase-locked loop (PLL) processing cycle; the second PRF outputs / setting the (i+1)-th frequency point of the first loop in the second PLF; the third PRF outputs / setting the (i+2)-th frequency point of the second PLF in the third PLF; and so on, in a continuous operation. This invention provides (i-1) PRF cycles for frequency locking at each frequency point in each PLF, thus solving the constraint of single-loop frequency hopping time on pseudo-random frequency agility.

Description

Technical Field

[0001] This invention belongs to the field of radar technology and relates to a pseudo-random frequency agility implementation method based on multi-loop flow operation, which is applied in radar frequency synthesizers. Background Technology

[0002] A phase-locked loop (PLL) is a negative feedback control system that uses a voltage generated for phase synchronization to tune a voltage-controlled oscillator (VCO) to produce a target frequency. According to automatic control principles, this is a typical feedback control circuit. It uses an externally input reference signal to control the frequency and phase of the oscillation signal within the loop, achieving automatic tracking of the output signal frequency to the input signal frequency. It is generally used in closed-loop tracking circuits. It is a method for stabilizing the frequency in radio transmission, mainly using a VCO (Voltage-Controlled Oscillator) and a PLL IC (Phase-Locked Loop Integrated Circuit). The VCO provides a signal; part of it is output, and the other part is compared in phase with the local oscillator signal generated by the PLL IC through frequency division. To maintain a constant frequency, the phase difference must not change. If there is a change in the phase difference, the voltage output of the PLL IC changes, controlling the VCO until the phase difference is restored, achieving phase locking. It is a closed-loop electronic circuit that ensures the frequency and phase of the controlled oscillator maintain a definite relationship with the input signal.

[0003] Pseudo-random frequency hopping technology, also known as pseudo-random frequency shift keying (PSK), utilizes the inherent "randomness" of pseudo-random sequences to control the "irregular" switching of carrier frequencies. This not only ensures excellent anti-interference performance but also significantly improves system sensitivity. Currently, pseudo-random frequency hopping technology has a wide range of applications, including civilian uses such as automotive radar and wireless network communication, and military applications such as target detection.

[0004] Phase-locked loops (PLLs) are widely used in radar frequency synthesizers as a primary method for indirect frequency synthesis. Their advantages include small size, low power consumption, low cost, and simple circuit design. However, their frequency hopping time, ranging from tens to hundreds of microseconds, is a drawback. In pseudo-random frequency agile applications, due to their randomness, the frequency hopping interval varies significantly across a large operating bandwidth, resulting in substantial variations in hopping time. Especially for applications with short pulse repetition periods (PRFs) (tens of microseconds), the design methods and application schemes of PLL circuits must be rigorously analyzed to meet system requirements.

[0005] In classic second- and third-order loops, f i →f j Frequency hopping time depends on ω n (natural frequency) and ξ (damping factor), when the frequency hopping interval is dF and the distance from the target frequency is f jWhen the allowable frequency difference is df, the frequency hopping time is approximately:

[0006]

[0007] For example:

[0008] dF = 20MHz

[0009] df = 1kHz

[0010] ξ=1

[0011]

[0012]

[0013] Normally ω n Taking a frequency of around 150kHz, the frequency hopping time is approximately 66.67μs, which cannot satisfy the PRF period T. PRF Applications with a hopping frequency of less than 66.67 μs are particularly problematic. In pseudo-random frequency hopping, the hopping interval dF can reach hundreds of MHz (or even GHz), which significantly increases the hopping time (approximately 96.7 μs when dF = 2 GHz). This means that PRFs below 100 μs cannot be selected in the overall radar design. Summary of the Invention

[0014] Technical problems to be solved

[0015] To resolve the contradiction between the long single-loop frequency hopping time and the radar frequency agility requirement (typically ≤1μs), and to realize pseudo-random frequency hopping applications over a wide bandwidth, this invention provides a pseudo-random frequency agility implementation method based on multi-loop continuous operation.

[0016] Technical solution

[0017] A pseudo-random frequency agility implementation method based on multi-loop flow operation, characterized by: including a frequency synthesizer controller, a power divider network, and multiple phase-locked loops (PLLs). i One switching network; phase-locked loop reference clock f ref The input is fed into a power splitter network, which connects n phase-locked loops (PLLs). i Phase-locked loop (PLL) i The output is connected to a switching network; when the frequency controller receives the central unit's "pseudo-random frequency hopping enable" and "pseudo-random frequency hopping code initial value" commands, it calculates the pseudo-random frequency code sequence within the current coherent processing cycle CPI based on the pseudo-random "characteristic polynomial," pre-sets the first (i-1) phase-locked loops, and the final stage selects f through the switching network. o The output provides the reference clock for generating the switching signals and the phase-locked loop reference clock f. ref It should satisfy the properties of coherence and reciprocity.

[0018] A further technical solution of the present invention: The pre-setting of the first (i-1) phase-locked loops specifically involves: the frequency controller controlling the first phase-coefficient processing cycle PRF to output / set the frequency point of the first phase-locked loop, the second PRF to output / set the frequency point of the first loop, the third PRF to output / set the frequency point of the second phase-locked loop, and so on, in a continuous process.

[0019] A computer system is characterized by comprising: one or more processors, and a computer-readable storage medium for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method described above.

[0020] A computer-readable storage medium is characterized by storing computer-executable instructions, which, when executed, are used to implement the above-described method.

[0021] Beneficial effects

[0022] The pseudo-random frequency agility implementation method based on multi-loop flow operation provided by this invention has the following advantages compared with the prior art:

[0023] 1) The pseudo-random frequency agility implementation method based on multi-loop flow operation designed in this invention has (i-1) PRF cycles for frequency locking at each frequency point of each phase-locked loop, which solves the problem of the constraint of single-loop frequency hopping time on pseudo-random frequency agility.

[0024] 2) The pseudo-random frequency agile implementation method based on multi-loop flow operation designed in this invention uses "space to time" to map the single-loop frequency hopping time to the switching time of the switching network, which is usually in the tens of ns range, thereby improving the flexibility of radar anti-jamming design. Attached Figure Description

[0025] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0026] Figure 1 Block diagram of the implementation scheme of the present invention.

[0027] Figure 2 Flowchart of the processing of this invention (3-ring scheme);

[0028] Figure 3 Flowchart of the processing of this invention (4-ring scheme);

[0029] Figure 4 Example of pseudo-random frequency point code calculation in this invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0031] like Figure 1 The diagram shown is a block diagram of the implementation scheme of this invention. It includes one power divider network and multiple phase-locked loops (PLLs). i (i≥2), 1 switching network. The frequency synthesizer is generally provided by an external circuit.

[0032] When the frequency synthesizer receives the "pseudo-random frequency hopping enable" and "pseudo-random frequency hopping code initial value" commands from the central unit (usually a signal processor or real-time control computer on radar), it calculates the pseudo-random frequency point code sequence within the current coherent processing cycle (CPI) based on the pseudo-random "characteristic polynomial" (the characteristic polynomial is determined by the overall system requirements). Figure 4 As shown, the characteristic polynomial used is x 24 +x 2 +1), the first (i-1) phase-locked loops (i.e., the first (i-1) frequencies of the pseudo-random frequency code sequence) are pre-set, and the final stage selects f through a switching network. o The output provides the reference clock for generating the switching signals and the phase-locked loop reference clock f. ref It should satisfy the properties of coherence (same crystal source) and reciprocity (integer multiple relationship).

[0033] like Figure 2 , 3 The diagram shown is a flowchart of the process of the method of the present invention.

[0034] The frequency synthesizer controller controls the output / setting of the i-th frequency point of the first phase-locked loop (PLL) in the first phase-coherent processing cycle, the output / setting of the (i+1)-th frequency point of the first PLF in the second PLF, the output / setting of the (i+2)-th frequency point of the second PLF in the third PLF, and so on, in a continuous process.

[0035] Figure 2 The diagram illustrates this using three loops. It includes three phase-locked loops: output loop 1 writes to loop 3, output loop 2 writes to loop 1, and output loop 3 writes to loop 2; this process is repeated sequentially in a continuous flow.

[0036] The output of ring 1 writing to ring 3 means:

[0037] Within each CPI cycle, the first loop (first frequency point) is output within the first PRF cycle, and the register value of the third loop (preparing for the third frequency point) is written at the rising edge of the first PRF.

[0038] The output of 2 rings writing 1 ring means:

[0039] Within each CPI cycle, the second loop outputs (the second frequency point) within the second PRF cycle, and the register value of the first loop is written at the rising edge of the second PRF (preparing for the fourth frequency point);

[0040] The output is 3 rings writing to 2 rings:

[0041] The third ring outputs (the third frequency point) within the third PRF cycle, and the register value of the second ring is written at the rising edge of the third PRF (preparing for the fifth frequency point).

[0042] The first ring outputs (the fourth frequency point) within the fourth PRF cycle, and the register value of the third ring is written at the rising edge of the fourth PRF (preparing for the sixth frequency point);

[0043] ...

[0044] The three-ring scheme means that each frequency point can have two PRF cycles to meet the frequency hopping time.

[0045] Similarly Figure 3 The diagram uses four rings as an example, including four phase-locked loops. Output ring 1 writes to ring 4, output ring 2 writes to ring 1, output ring 3 writes to ring 2, and output ring 4 writes to ring 3; this process is repeated sequentially in a continuous flow.

[0046] The output of 1 ring writing 4 rings means:

[0047] Within each CPI cycle, the first loop outputs (the first frequency point) within the first PRF cycle, and writes the register value of the fourth loop (preparing for the fourth) frequency point at the rising edge of the first PRF.

[0048] The output 2 rings write 1 ring:

[0049] The second ring outputs (the second frequency point) within the second PRF cycle, and the register value of the first ring is written at the rising edge of the second PRF (preparing for the fifth frequency point).

[0050] The output is 3 rings writing to 2 rings:

[0051] The third ring outputs (the third frequency point) within the third PRF cycle, and writes the register value of the second ring (preparing for the sixth) frequency point at the rising edge of the third PRF.

[0052] The output 4 rings write 3 rings:

[0053] The fourth ring outputs (the fourth frequency point) within the fourth PRF cycle, and writes the register value of the third ring (preparing for the seventh) frequency point at the rising edge of the fourth PRF.

[0054] The 4-ring scheme means that each frequency point can have 3 PRF cycles to meet the frequency hopping time; the i-ring scheme means that each frequency point can have i-1 PRF cycles to meet the frequency hopping time.

[0055] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A pseudo-random frequency agility implementation method based on multi-loop flow operation, characterized in that: A frequency synthesizer includes a frequency synthesizer controller, a power divider network, a plurality of phase locked loops , and a switch network. Phase-locked loop reference clock Input to the power splitter network, power splitter network connection A phase-locked loop Phase-locked loop Output connection to the switching network; when the frequency controller receives the "pseudo-random frequency hopping enable" and "pseudo-random frequency hopping code initial value" commands from the central unit, it calculates the pseudo-random frequency code sequence within the current coherent processing cycle CPI based on the pseudo-random "characteristic polynomial", and pre-sets the previous... A phase-locked loop, the final stage of which is selected via a switching network. The output provides a reference clock for generating the switching signals and a phase-locked loop reference clock. It should satisfy the properties of coherence and reciprocity; Among them, multiple phase-locked loops It includes 3 phase-locked loops, with output loop 1 writing to loop 3, output loop 2 writing to loop 1, and output loop 3 writing to loop 2; this is done sequentially in a pipeline operation. The output of ring 1 writing to ring 3 means: Within each CPI cycle, the first frequency point of the first ring is output within the first PRF cycle, and the register value of the third ring is written at the rising edge of the first PRF to prepare for the third frequency point; The output of 2 rings writing 1 ring means: Within each CPI cycle, the second frequency point is output by the second ring in the second PRF cycle, and the register value of the first ring is written at the rising edge of the second PRF to prepare for the fourth frequency point. The output is 3 rings writing to 2 rings: During the third PRF cycle, the third ring outputs the third frequency point, and at the rising edge of the third PRF, the register value of the second ring is written to prepare for the fifth frequency point.

2. A computer system, characterized by include: One or more processors, a computer-readable storage medium for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method of claim 1.

3. A computer-readable storage medium, characterized in that The device stores computer-executable instructions, which, when executed, are used to implement the method of claim 1.

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