A fast frequency hopping system for ultra-wideband frequency agile radar and its implementation method

Abstract

The present invention relates to the fields of radar, communication, and anti-interference technology, and discloses a fast frequency hopping system for an ultra-wideband frequency agile radar and an implementation method thereof. The system comprises: a frequency agile receiving module comprising a radio frequency receiving module, a first mixer, an analog-to-digital converter module, and a programmable, pre-stored phase-locked loop (PLL) 1; a frequency agile transmitting module comprising a radio frequency transmitting module, a second mixer, a digital-to-digital converter module, and a programmable, pre-stored PLL 2; and an FPGA comprising a first memory, a second memory, a digital down-conversion module, a digital up-conversion module, a digital frequency hopping NCO module, and a frequency hopping control module. The system implements fast frequency hopping by rewriting the BUFFER0 / 1 cache in a ping-pong manner to quickly rewrite the preset PLL.

Description

Technical Field

[0001] The present invention relates to the fields of radar, communication and anti-interference technology, and in particular to a fast frequency hopping system of an ultra-wideband frequency agile radar and an implementation method thereof. Background Art

[0002] The key to the design and implementation of a frequency-agile stepped radar system is the rapid generation of variable-frequency carrier signals. While the frequency synthesizer generates carrier signals with an ultra-wide frequency range, it also requires high requirements for indicators such as phase noise, in-band and out-of-band spurious signals, and frequency agility time at each carrier frequency point.

[0003] Frequency synthesizers using traditional analog phase-locked loop technology have the advantages of low phase noise, low spurious signals, and high signal frequency. Although the loop division ratio and synthesized carrier frequency of traditional analog phase-locked loops can be flexibly set, the filter resistor and capacitor values of the analog loop and the VCO tuning voltage cannot be programmably configured and preset. The loop bandwidth of the loop filter is narrow, resulting in a long phase-locked loop locking time, the VCO tuning voltage cannot be quickly switched to the new frequency point, and the fast frequency hopping frequency locking is very slow.

[0004] The commonly used direct digital frequency synthesizer DDS has the advantages of wide bandwidth, fast frequency agility, high frequency resolution, and full digital programmability. The carrier frequency switching depends on the speed of writing the digital frequency control word. The specific implementation is to preset the frequency control word for the DDS phase accumulator in the digital domain, and output the digital carrier signal of the required frequency by looking up the preset sine table. However, the maximum frequency of the carrier signal output after DAC synthesis is limited by the system clock rate, and the generated carrier frequency is relatively low and the spurious harmonics are large. Usually, the digital carrier NCO signal synthesized by DDS is complex multiplied with the baseband signal in the digital domain to realize the digital up and down conversion function of multiple transceiver channels. A large number of complex multipliers and sine tables for generating digital carrier signals will also consume a lot of hardware resources. Summary of the Invention

[0005] The present invention provides a fast frequency hopping system for an ultra-wideband frequency agile radar and an implementation method thereof, so as to achieve the goals of wide radar operating frequency range, fast carrier frequency hopping and low hardware cost.

[0006] The present invention is achieved through the following technical solutions:

[0007] A fast frequency hopping system for an ultra-wideband frequency agile radar, comprising:

[0008] The agile frequency receiving module includes a radio frequency receiving module, a first mixer, an AD conversion module and a programmable, pre-stored phase-locked loop 1; the output end of the radio frequency receiving module and the output end of the pre-stored phase-locked loop 1 are input to the first mixer and then transmitted to the AD conversion module;

[0009] The agile frequency transmission module includes a radio frequency transmission module, a second mixer, a DA conversion module and a programmable, pre-stored phase-locked loop 2; the output end of the DA conversion module and the output end of the pre-stored phase-locked loop 2 are input to the second mixer and then transmitted to the radio frequency transmission module;

[0010] An FPGA includes a memory 1, a memory 2, a digital down-conversion module, a digital up-conversion module, a digital frequency hopping NCO module, and a frequency hopping control module. The memory 1 is bidirectionally connected to the pre-stored phase-locked loop 1, and the memory 2 is bidirectionally connected to the pre-stored phase-locked loop 2. The frequency hopping control module generates a frequency hopping synchronization signal and a frequency point number to control the digital frequency hopping NCO module to generate a local digital carrier frequency NCO signal for use by the digital down-conversion module and the digital up-conversion module in digital frequency hopping. Another input end of the digital down-conversion module is connected to the AD conversion module, and an output end of the digital down-conversion module is connected to a signal processing module. Another input end of the digital up-conversion module is connected to an IQ digital baseband signal module, and an output end of the digital up-conversion module is connected to the DA conversion module. Programmable registers are respectively provided in the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2.

[0011] As an optimization, both memory 1 and memory 2 include a gain control storage module that stores the initial gain of the RF receiving module and the RF transmitting module, and a phase-locked loop storage module that stores the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2.

[0012] As an optimization, the optimal phase-locked loop tuning parameters include the PLL loop frequency division ratio of each frequency point, the VCO frequency division value, the VCO tuning voltage value, the loop filter's electrically adjustable resistance and capacitance values, and the optimal frequency tuning parameters at different temperatures for each frequency point.

[0013] As an optimization, the agile frequency conversion receiving module is connected to the memory one through SPI interface one, the AD conversion module is connected to the digital down-conversion module through a discrete high-speed data transmission interface one, and the digital down-conversion module is connected to the signal processing module through a discrete high-speed data transmission interface three.

[0014] As an optimization, the agile frequency transmission module is connected to the memory 2 through SPI interface 2, the IQ digital baseband signal module is connected to the digital up-conversion module through a discrete high-speed data transmission interface 4, and the digital up-conversion module is connected to the DA conversion module through a discrete high-speed data transmission interface 1.

[0015] A method for implementing fast frequency hopping of an ultra-wideband frequency agile radar, based on the above-mentioned fast frequency hopping system of the ultra-wideband frequency agile radar, comprises:

[0016] S1. Power on, perform full-frequency self-tuning on the fast frequency hopping system of the ultra-wideband frequency agile radar, save the initial gain parameters of the radio frequency receiving module and the radio frequency transmitting module in the first memory and the second memory, and save the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop first and the pre-stored phase-locked loop second in the first memory and the second memory, respectively;

[0017] S2. Reading initial gain parameters of the RF receiving module and the RF transmitting module from the first memory and the second memory, respectively; configuring the initial gain, frequency hopping sequence, and step frequency hopping range of the RF receiving module and the RF transmitting module according to the initial gain parameters; and simultaneously, reading optimal phase-locked loop tuning parameters of the preset phase-locked loop 1 and the preset phase-locked loop 2 from the first memory and the second memory, respectively, to quickly preset the programmable registers of the preset phase-locked loop 1 and the preset phase-locked loop 2;

[0018] S3, when frequency hopping is enabled, the frequency hopping control module generates a frequency hopping synchronization signal and a frequency point number, with a frequency hopping interval time Th f The digital frequency hopping NCO module generates a frequency of i*D for periodic control Δf The local digital carrier frequency signal is used for digital frequency hopping;

[0019] S4. When the RF receiving module receives an external RF signal, the preset phase-locked loop (PLL) 1 adjusts the first analog carrier frequency signal according to the optimal phase-locked loop tuning parameters in the preset programmable register to complete a rapid jump of the first analog carrier frequency signal.

[0020] S5. The first mixer performs orthogonal demodulation on the RF signal and the corresponding first analog carrier signal to convert them into an I-channel analog signal and a Q-channel analog signal; the I-channel analog signal and the Q-channel analog signal are then respectively sent to the AD conversion module to obtain discrete IQ digital orthogonal signals after completing analog-to-digital conversion, and are transmitted to the digital down-conversion module to mix with the local digital carrier signal to achieve digital down-conversion and then output to the signal output module;

[0021] S6. After the digital up-conversion module receives the digital baseband signal transmitted by the IQ digital baseband signal module, it mixes it with the local digital carrier signal to achieve digital up-conversion and then outputs it to the DA conversion module for digital-to-analog conversion. At the same time, the preset phase-locked loop 2 adjusts the second analog carrier signal according to the preset optimal phase-locked loop tuning parameters in the order of the IQ digital baseband signals to complete the rapid jump of the analog carrier signal.

[0022] S7. The baseband signal after digital-to-analog conversion by the DA conversion module is mixed with the second analog carrier signal by a second mixer and then output to the RF transmission module for transmission.

[0023] As an optimization, both the memory 1 and the memory 2 include a gain control storage module that stores the initial gains of the RF receiving module and the RF transmitting module, and a phase-locked loop storage module that stores the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2, wherein the gain control storage module of the RF receiving module and the RF transmitting module is preset through the initial gain table, and the programmable registers of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2 are quickly preset according to the optimal phase-locked loop tuning parameters.

[0024] As an optimization, the parameters stored in the frequency tuning parameter table are the optimal phase-locked loop tuning parameters for each frequency point when the phase-locked loop self-tunes and locks after the self-tuning process of the fast frequency hopping system of the ultra-wideband agile frequency radar, and each of the optimal phase-locked loop tuning parameters is stored in the order of the frequency points of the external signal.

[0025] As an optimization, the programmable register in the preset phase-locked loop 1 includes a first high-speed cache and a second high-speed cache, and the steps of quickly presetting the programmable register in the preset phase-locked loop 1 are:

[0026] A1. Finding corresponding optimal phase-locked loop tuning parameters from the first memory according to the frequency sequence of the external signal, and writing the found optimal phase-locked loop tuning parameters into the first cache and the second cache in advance according to the odd and even numbers of the frequency sequence, wherein if the number of the optimal phase-locked loop tuning parameter stored in the first cache is odd, the number of the optimal phase-locked loop tuning parameter stored in the second cache is even;

[0027] A2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the first cache and the second cache in a ping-pong manner.

[0028] As an optimization, the programmable register in the preset phase-locked loop 2 includes a third high-speed cache and a fourth high-speed cache, and the steps of quickly presetting the programmable register in the preset phase-locked loop 2 are:

[0029] B1. Finding corresponding optimal phase-locked loop tuning parameters from the second memory according to the frequency sequence of the external signal, and writing the found optimal phase-locked loop tuning parameters into the third cache and the fourth cache in advance, alternately according to the odd and even numbers of the frequency sequence, wherein if the number of the optimal phase-locked loop tuning parameter stored in the third cache is odd, the number of the optimal phase-locked loop tuning parameter stored in the fourth cache is even;

[0030] B2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the third cache and the fourth cache in a ping-pong manner.

[0031] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0032] All parameters of the pre-stored phase-locked loop of the present invention are digitally programmable and pre-stored. The core technology of the pre-stored phase-locked loop (PRE-STORE_PLL / LPF) is an integrated circuit that can preset VCO tuning voltage and loop filter resistor and capacitor values. By quickly switching the preset VCO tuning voltage and loop resistor and capacitor values, the transmit and receive local oscillator (LO) signal at the required frequency point is quickly tuned and locked, generating a high-precision, high-performance local oscillator (LO) signal as an analog fast-hopping ultra-wideband carrier frequency. This fast-hopping carrier frequency is then mixed with a baseband signal to generate a fast-hopping radio frequency (RF) signal.

[0033] The present invention uses the PRE-STORE_PLL / LPF programmable registers (first cache, second cache, third cache, fourth cache) to retrieve the tuning parameter data of the corresponding frequency from the external memory according to the pre-acquired frequency tuning parameters and in accordance with any arranged frequency hopping sequence, thereby completing frequency hopping modes such as arbitrary sequence and random sequence of fast frequency points.

[0034] The present invention adopts a fast jump scheme combining (large step) radio frequency fast jump + (small step) digital carrier frequency fast jump to realize stepped frequency radar carrier frequency signal generation and echo reception, so as to achieve a wide radar operating frequency range;

[0035] The present invention uses a frequency tuning parameter table to preset register values corresponding to various frequencies of a phase-locked loop (PRE-STORE_PLL / LPF) for fast frequency hopping. A fast presetting method is to design at least two frequency tuning parameter caches BUFFER0 / 1, wherein the BUFFER0 memory stores the current frequency parameters and the BUFFER1 memory stores the next frequency parameters. The caches BUFFER0 / 1 are updated and used alternately, and the preset phase-locked loop is quickly rewritten by rewriting the BUFFER0 / 1 cache in a ping-pong manner, thereby completing fast frequency hopping. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings:

[0037] Figure 1 Schematic diagram of the structure of the fast frequency hopping system of the ultra-wideband frequency agile radar according to the present invention;

[0038] Figure 2 To obtain the principle block diagram of the phase-locked loop frequency tuning parameters;

[0039] Figure 3 To simulate the principle block diagram of fast frequency hopping;

[0040] Figure 4 This is the frequency distribution diagram of analog and digital mixed frequency hopping.

[0041] Markings and corresponding parts names in the accompanying drawings:

[0042] 100-Agile frequency receiving module, 110-RF receiving module, 120-First mixer, 130-AD conversion module, 140-Pre-stored phase-locked loop 1, 200-Agile frequency transmitting module, 210-RF transmitting module, 220-Second mixer, 230-DA conversion module, 240-Pre-stored phase-locked loop 2, 300-FPGA, 310-Digital down-conversion module, 320-Frequency hopping control module, 330-Digital frequency hopping NCO module, 340-Digital up-conversion module, 350-Memory 1, 360-Memory 2, 400-Signal processing module, 500-IQ digital baseband signal module. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0044] In a frequency-agile stepped radar, the operating carrier frequency of the radar signal waveform needs to jump rapidly over a wide range. The present invention utilizes a highly integrated analog RF agile transceiver (frequency-agile receiving module 100 and frequency-agile transmitting module 200) and an FPGA300-based (CORDIC_DDU / DDC) all-digital carrier frequency up- and down-conversion method to achieve ultra-wide frequency carrier frequency fast hopping in both the analog RF domain and the digital domain. The details are as follows:

[0045] Example 1 A fast frequency hopping system for ultra-wideband frequency agile radar, such as Figure 1 Shown, including:

[0046] The frequency agile receiving module 100 includes a radio frequency receiving module 110, a first mixer 120, an AD conversion module 130, and a pre-stored phase-locked loop 1 140; the output end of the radio frequency receiving module 110 and the output end of the pre-stored phase-locked loop 1 140 are input to the first mixer 120 and then transmitted to the AD conversion module 130;

[0047] The frequency agile transmission module 200 includes a radio frequency transmission module 210, a second mixer 220, a DA conversion module 230, and a second pre-stored phase-locked loop 240; the output end of the DA conversion module 230 and the output end of the second pre-stored phase-locked loop 240 are input to the second mixer 220 and then transmitted to the radio frequency transmission module 210;

[0048] FPGA300 includes a memory 1 350, a memory 2 360, a digital down-conversion module 310, a digital up-conversion module 340, a digital frequency hopping NCO module 330, and a frequency hopping control module 320. The memory 1 350 is bidirectionally connected to the pre-stored phase-locked loop 1 140, the memory 2 360 is bidirectionally connected to the pre-stored phase-locked loop 2 240, the frequency hopping control module 320 generates a frequency hopping synchronization signal and a frequency point number to control the digital frequency hopping NCO module 330 to generate a local digital carrier frequency NCO signal for the digital down-conversion module 310 and the digital up-conversion module 340 to perform digital frequency hopping. Another input end of the digital down-conversion module 310 is connected to the AD conversion module 130, and an output end of the digital down-conversion module 310 is connected to the signal processing module 400. Another input end of the digital up-conversion module 340 is connected to the IQ digital baseband signal. The module 500 is connected, the output end of the digital up-conversion module 340 is connected to the DA conversion module 230. Specifically, the agile frequency receiving module 100 is connected to the memory 1 350 through the SPI interface 1, the AD conversion module 130 is connected to the digital down-conversion module 310 through a discrete high-speed data transmission interface 1, the digital down-conversion module 310 is connected to the signal processing module 400 through a discrete high-speed data transmission interface 3, the agile frequency transmitting module 200 is connected to the memory 2 360 through the SPI interface 2, the IQ digital baseband signal module 500 is connected to the digital up-conversion module 340 through a discrete high-speed data transmission interface 4, and the digital up-conversion module 340 is connected to the DA conversion module 230 through a discrete high-speed data transmission interface 1. Programmable registers are respectively provided in the preset phase-locked loop 1 and the preset phase-locked loop 2.

[0049] More specifically, the memory 1 350 and the memory 2 360 both include a gain control storage module that stores the initial gains of the RF receiving module 110 and the RF transmitting module 210, and a phase-locked loop storage module that stores the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop 1 140 and the pre-stored phase-locked loop 2 240 in the order of the frequency points of the external signal. The optimal phase-locked loop tuning parameters include the PLL loop frequency division ratio, VCO frequency division value, VCO tuning voltage value, loop filter electrical adjustment resistance and capacitance value, and the optimal frequency tuning parameters at different temperatures for each frequency point.

[0050] The fast frequency hopping system of the ultra-wideband frequency agile radar of the present invention is based on a highly integrated analog radio frequency (RF) agile transceiver. All parameters of the pre-stored phase-locked loop 140 and the pre-stored phase-locked loop 240 of the ultra-wideband frequency synthesizer in the analog radio frequency (RF) agile transceiver have digital programmable and pre-stored functions. The core technology of the pre-stored phase-locked loop (PRE-STORE_PLL / LPF) of the pre-stored phase-locked loop 140 and the pre-stored phase-locked loop 240 is an integrated circuit with preset VCO tuning voltage and preset loop filter resistance and capacitance values. By quickly switching the preset VCO tuning voltage and loop resistance and capacitance values, the transmit and receive local oscillator (LO) signal (analog carrier signal) at the desired frequency point is quickly tuned and locked to generate a high-precision, high-performance local oscillator. The LO signal is used as an analog fast-hopping ultra-wideband carrier frequency, which is then mixed with the baseband signal to generate a fast-hopping RF signal. Local oscillator (LO) signal carrier frequencies at different frequencies typically have corresponding phase-locked loop (PLL) parameters and electrically adjustable resistance and capacitance values for the loop filter. Since the optimal PLL parameters and loop filter resistance and capacitance values for each carrier frequency are typically only affected by device hardware and ambient temperature, the optimal PLL tuning parameters (optimal PLL parameters, loop filter resistance and capacitance values, etc.) can be obtained in advance through long-term precise tuning and calibration and stored to form a pre-stored parameter table for each carrier frequency point. During normal operation, the pre-stored parameters for each carrier frequency point are directly used by the PRE-STORE_PLL / LPF (pre-stored PLL) to achieve rapid analog RF carrier frequency hopping.

[0051] The digital carrier frequency agility of the transceiver channel of the present invention adopts the FPGA300 all-digital circuit to realize (CORDIC_DDU / DDC) digital carrier frequency up and down conversion. The DDU / DDC digital frequency conversion is realized by the CORDIC algorithm, which can save hardware logic resources, improve the system clock rate and the output carrier signal frequency. The high-precision frequency of the digital carrier is controlled by the digital carrier NCO frequency word register, and the phase of the digital carrier is directly controlled by the digital phase register (the digital carrier NCO frequency word register and the digital phase register are both set in the frequency hopping control module 320). For the stepped carrier frequency, the step frequency interval and the starting frequency can be preset to automatically and evenly generate the digital fast hopping carrier frequency.

[0052] The frequency agile receiving module 100 and the frequency agile transmitting module 200 may be integrated into one IC.

[0053] A method for implementing fast frequency hopping of an ultra-wideband frequency agile radar in Example 2 is based on the fast frequency hopping system of the ultra-wideband frequency agile radar in Example 1, comprising:

[0054] S1. Power on, perform full-frequency self-tuning on the fast frequency hopping system of the ultra-wideband frequency agile radar, save the initial gain parameters of the radio frequency receiving module and the radio frequency transmitting module in the first memory and the second memory, respectively, and save the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop first and the pre-stored phase-locked loop second in the first memory and the second memory, respectively, in the order of the external signals to be received;

[0055] Both the first and second memories include a gain control storage module storing the initial gains of the radio frequency receiving module and the radio frequency transmitting module, and a phase-locked loop storage module storing the optimal phase-locked loop tuning parameters of the pre-stored first and second phase-locked loops. The gain control storage module of the radio frequency receiving module and the radio frequency transmitting module is preset using an initial gain table, and the phase-locked loop storage module is preset based on a frequency tuning parameter table corresponding to the order of the frequency points of the external signal corresponding to the pre-stored first and second phase-locked loops.

[0056] The parameters stored in the frequency tuning parameter table are the optimal phase-locked loop tuning parameters for each frequency point when the phase-locked loop self-tunes and locks after the fast frequency hopping system of the ultra-wideband agile frequency radar performs a self-tuning process, and each of the optimal phase-locked loop tuning parameters is stored in the order of the frequency points of the external signal.

[0057] When powered on for the first time, the optimal phase-locked loop tuning parameters for each frequency point and the initial gain of each channel must be automatically obtained and saved. The optimal phase-locked loop tuning parameters include the PLL loop frequency division ratio, VCO frequency division value, VCO tuning voltage value of the lower phase-locked loop, the electronically adjustable resistance and capacitance values of the loop filter, and the optimal frequency tuning parameters at different temperatures for each frequency point.

[0058] The first time power is turned on, a full-frequency self-tuning program is required. The self-tuning program reserves a long time for each frequency point to obtain the optimal phase-locked loop tuning parameters when the phase-locked loop self-tunes and locks at each frequency point. The frequency self-tuning program is started in sequence to obtain frequency parameter data such as the PLL loop frequency division ratio, VCO frequency division value, VCO tuning voltage value, and loop filter electronic adjustment resistance and capacitance values of the locked frequency point. The optimal frequency tuning parameter table obtained at different temperatures for each frequency point is saved in the FPGA's ROM or FLASH external memory for use during fast frequency hopping.

[0059] The analog frequency conversion channels for transmission and reception (RF receiving module, RF transmitting module) and analog-to-digital conversion modules (AD conversion module, DA conversion module) can use a single-chip solution of RF analog hybrid IC or separate components to convert analog signals into discretely sampled IQ digital complex signals; the frequency parameters, frequency hopping control, and AD / DA configuration interface use the SPI bus.

[0060] Stored procedures such as Figure 2As shown, the present invention can obtain the optimal frequency parameters of each frequency point when the phase-locked loop is self-tuned and locked in advance through the PRE-STORE_PLL / LPF programmable register in the integrated chip (module); start the frequency self-tuning program in sequence to obtain frequency parameter data such as the PLL loop frequency division ratio, VCO frequency division value, VCO tuning voltage value, and loop filter electronic adjustment resistance and capacitance values of the locked frequency point, and save the optimal frequency tuning parameters obtained at different temperatures for each frequency point in the ROM or FLASH external memory of the FPGA.

[0061] S2, read the initial gain parameters of the RF receiving module and the RF transmitting module from the memory 1 and the memory 2 respectively; configure the initial gain, frequency hopping sequence, and step frequency hopping range of the RF receiving module and the RF transmitting module according to the initial gain parameters Δf At the same time, the optimal phase-locked loop tuning parameters of the preset phase-locked loop 1 and the preset phase-locked loop 2 are read from the memory 1 and the memory 2 respectively.

[0062] S3, when frequency hopping is enabled, the frequency hopping control module generates a frequency hopping synchronization signal and a frequency point number, with a frequency hopping interval time Th f The digital frequency hopping NCO module generates a frequency of i*D for periodic control Δf The local digital carrier signal is used for digital frequency hopping.

[0063] S4. When the RF receiving module receives an external RF signal, the preset phase-locked loop (PLL) 1 reads the preset optimal phase-locked loop tuning parameters from the memory 1 according to the order of the external signal to adjust the first analog carrier frequency signal, thereby completing a rapid jump of the first analog carrier frequency signal.

[0064] S5. The first mixer performs orthogonal demodulation on the RF signal and the corresponding first analog carrier signal to convert them into an I-channel analog signal and a Q-channel analog signal; the I-channel analog signal and the Q-channel analog signal are then respectively sent to the AD conversion module to obtain discrete IQ digital orthogonal signals after completing analog-to-digital conversion, and are transmitted to the digital down-conversion module to mix with the local digital carrier signal to achieve digital down-conversion and then output to the signal output module;

[0065] S6. After receiving the digital baseband signal transmitted by the IQ digital baseband signal module, the digital up-conversion module mixes the digital baseband signal with the local digital carrier signal to achieve digital up-conversion, and then outputs the mixed signal to the DA conversion module for digital-to-analog conversion. At the same time, the preset phase-locked loop 2 reads the preset optimal phase-locked loop tuning parameters from the memory 2 in the order of the IQ digital baseband signals to adjust the second analog carrier signal, thereby completing the rapid jump of the analog carrier signal.

[0066] S7. The baseband signal after digital-to-analog conversion by the DA conversion module is mixed with the second analog carrier signal by a second mixer and then output to the RF transmission module for transmission.

[0067] The programmable register in the preset phase-locked loop 1 includes a first high-speed cache and a second high-speed cache, and the steps of quickly presetting the programmable register in the preset phase-locked loop 1 are:

[0068] A1. Find the corresponding optimal phase-locked loop tuning parameters from the memory 1 according to the frequency sequence of the external signal, and write the found optimal phase-locked loop tuning parameters into the first cache and the second cache in advance according to the odd and even numbers of the frequency sequence, wherein, if the number of the optimal phase-locked loop tuning parameters stored in the first cache is odd, the number of the optimal phase-locked loop tuning parameters stored in the second cache is even; if the number of the optimal phase-locked loop tuning parameters stored in the first cache is even, the number of the optimal phase-locked loop tuning parameters stored in the second cache is odd.

[0069] A2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the first cache and the second cache in a ping-pong manner.

[0070] The ping-pong method is specifically as follows: first write / read the best phase-locked loop tuning parameters of the first frequency point into the first cache, then write / read the best phase-locked loop tuning parameters of the second frequency point into the second cache, and then repeat the above steps, alternately writing / reading the best phase-locked loop tuning parameters of subsequent frequency points into the first cache and the second cache.

[0071] The programmable register in the preset phase-locked loop 2 includes a third high-speed cache and a fourth high-speed cache, and the steps of quickly presetting the programmable register in the preset phase-locked loop 2 are:

[0072] B1. Find the corresponding optimal phase-locked loop tuning parameters from the second memory according to the frequency sequence of the external signal, and write the found optimal phase-locked loop tuning parameters into the third cache and the fourth cache in advance according to the odd and even numbers of the frequency sequence, wherein, if the number of the optimal phase-locked loop tuning parameters stored in the third cache is odd, the number of the optimal phase-locked loop tuning parameters stored in the fourth cache is even; if the number of the optimal phase-locked loop tuning parameters stored in the third cache is even, the number of the optimal phase-locked loop tuning parameters stored in the fourth cache is odd.

[0073] B2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the third cache and the fourth cache in a ping-pong manner.

[0074] At least two high-speed caches BUFFER0 / 1 (PRE-STORE_PLL / LPF programmable registers) for storing frequency tuning parameters are designed. The BUFFER0 memory stores the current frequency parameters, and the BUFFER1 memory stores the next frequency parameters. The high-speed caches BUFFER0 / 1 are updated and used alternately. By rewriting the BUFFER0 / 1 high-speed cache in a ping-pong manner, the phase-locked loop parameter registers can be quickly rewritten to complete fast frequency hopping. This embodiment designs two high-speed caches. According to the pre-acquired frequency tuning parameters, the tuning parameter data of the corresponding frequency can be retrieved from the external memory FPGA according to the arranged frequency hopping sequence to complete fast frequency hopping. The reading process is as follows: Figure 3 shown.

[0075] Specifically, the implementation of analog RF and digital carrier frequency hopping is as follows:

[0076] The present invention can adopt a fast jump scheme combining (large step) radio frequency fast jump + (small step) digital carrier frequency fast jump to realize stepped frequency radar carrier frequency signal generation and echo reception.

[0077] RF Δf is the carrier frequency interval of the simulated frequency hopping, D Δf is the digital carrier frequency interval, and the analog frequency hopping and digital frequency hopping waveform signals of the nth pulse are:

[0078] S n (t) = A n exp[-j2π(f0+k*RF Δf +i*D Δf )t](i=0,1,...,N-1)(k=0,1,...,M-1)

[0079] Where f0-starting frequency, A n -The amplitude of the nth pulse signal, M and N represent the maximum number of analog and digital frequency hopping points respectively;

[0080] Typically large-step analog frequency-hopping RF Δf Small step digital frequency hopping D Δf The total number of frequency hopping points is N*M.

[0081] If RF Δf The RF frequency hopping interval range is 10M~200MHz; D Δf The frequency range of the digital carrier frequency hopping interval is 1M~100MHz, so the RF frequency conversion range of the frequency agile transceiver of the present invention is (f0+(M-1)*RFΔf ) is 2~8GHz.

[0082] The present invention innovatively extracts all the loop locking parameters of the PRE-STORE_PLL / LPF operating frequencies in advance, forms a parameter table, and saves it. During normal operation, it is only necessary to search the locking parameter table for the frequency point according to the frequency hopping frequency, and preset the optimal locking parameters for the corresponding frequency point in the programmable register of the PRE-STORE_PLL / LPF in advance, greatly accelerating the loop locking time of the local oscillator LO signal at different carrier frequencies.

[0083] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A fast frequency hopping system for ultra-wideband frequency agile radar, characterized in that: include: The agile frequency receiving module includes a radio frequency receiving module, a first mixer, an AD conversion module and a programmable and pre-stored phase-locked loop 1; The output end of the radio frequency receiving module and the output end of the pre-stored phase-locked loop 1 are input to the first mixer and then transmitted to the AD conversion module; The agile frequency transmission module includes a radio frequency transmission module, a second mixer, a DA conversion module and a programmable, pre-stored phase-locked loop 2; the output end of the DA conversion module and the output end of the pre-stored phase-locked loop 2 are input to the second mixer and then transmitted to the radio frequency transmission module; The pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2 are integrated circuits with preset VCO tuning voltages and preset loop filter resistor and capacitor values. By quickly switching the preset VCO tuning voltages and loop resistor and capacitor values, the transmit and receive local oscillator (LO) signals of the desired frequency are quickly tuned and locked. The generated local oscillator (LO) signal is used as a simulated fast-hopping ultra-wideband carrier frequency, and the fast-hopping ultra-wideband carrier frequency is then mixed with a baseband signal to generate a fast-hopping radio frequency (RF) signal. An FPGA includes a memory 1, a memory 2, a digital down-conversion module, a digital up-conversion module, a digital frequency hopping NCO module, and a frequency hopping control module. The memory 1 is bidirectionally connected to the pre-stored phase-locked loop 1, and the memory 2 is bidirectionally connected to the pre-stored phase-locked loop 2. The frequency hopping control module generates a frequency hopping synchronization signal and a frequency point number to control the digital frequency hopping NCO module to generate a local digital carrier frequency NCO signal for the digital down-conversion module and the digital up-conversion module to perform digital frequency hopping. Another input end of the digital down-conversion module is connected to the AD conversion module, and an output end of the digital down-conversion module is connected to the signal processing module. Another input end of the digital up-conversion module is connected to the IQ digital baseband signal module, and the output end of the digital up-conversion module is connected to the DA conversion module. Programmable registers are respectively provided in the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2. The programmable register retrieves the tuning parameter data of the corresponding frequency point from the external memory according to the pre-acquired frequency tuning parameters and in accordance with the arbitrarily arranged frequency hopping sequence, thereby completing the arbitrary sequence or random sequence frequency hopping mode of the fast frequency point.

2. The fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 1, characterized in that: The memory 1 and the memory 2 both include a gain control storage module storing the initial gains of the RF receiving module and the RF transmitting module, and a phase-locked loop storage module storing the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2.

3. The fast frequency hopping system of ultra-wideband frequency agile radar according to claim 2, characterized in that: The optimal phase-locked loop tuning parameters include the PLL loop frequency division ratio of each frequency point, the VCO frequency division value, the VCO tuning voltage value, the loop filter's electrically adjustable resistance and capacitance values, and the optimal frequency tuning parameters at different temperatures for each frequency point.

4. The fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 1, characterized in that: The agile frequency conversion receiving module is connected to the memory through SPI interface one, the AD conversion module is connected to the digital down conversion module through a discrete high-speed data transmission interface one, and the digital down conversion module is connected to the signal processing module through a discrete high-speed data transmission interface three.

5. The fast frequency hopping system of ultra-wideband frequency agile radar according to claim 1, characterized in that: The agile frequency transmission module is connected to the memory 2 through SPI interface 2, the IQ digital baseband signal module is connected to the digital up-conversion module through a discrete high-speed data transmission interface 4, and the digital up-conversion module is connected to the DA conversion module through a discrete high-speed data transmission interface 1.

6. A method for implementing fast frequency hopping of an ultra-wideband frequency agile radar, based on the fast frequency hopping system of an ultra-wideband frequency agile radar according to any one of claims 1 to 5, characterized in that: include: S1. Power on, perform full-frequency self-tuning on the fast frequency hopping system of the ultra-wideband frequency agile radar, save the initial gain parameters of the radio frequency receiving module and the radio frequency transmitting module in the first memory and the second memory, and save the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop first and the pre-stored phase-locked loop second in the first memory and the second memory, respectively; S2. Reading initial gain parameters of the RF receiving module and the RF transmitting module from the first memory and the second memory, respectively; configuring the initial gain, frequency hopping sequence, and step frequency hopping range of the RF receiving module and the RF transmitting module according to the initial gain parameters; and simultaneously, reading optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop one and the pre-stored phase-locked loop two from the first memory and the second memory, respectively, to quickly preset the programmable registers of the pre-stored phase-locked loop one and the pre-stored phase-locked loop two; S3, when frequency hopping is enabled, the frequency hopping control module generates a frequency hopping synchronization signal and a frequency point number, with a frequency hopping interval time The digital frequency hopping NCO module generates a frequency of The local digital carrier signal is used for digital frequency hopping, i=0,1,···,N-1, N represents the maximum number of digital frequency hopping points, is the digital carrier frequency interval; S4. When the RF receiving module receives an external RF signal, the pre-stored PLL adjusts the first analog carrier frequency signal according to the optimal PLL tuning parameters in the preset programmable register to complete a rapid jump of the first analog carrier frequency signal; S5. The first mixer performs orthogonal demodulation on the RF signal and the corresponding first analog carrier signal to convert them into an I-channel analog signal and a Q-channel analog signal; the I-channel analog signal and the Q-channel analog signal are then respectively sent to the AD conversion module to obtain discrete IQ digital orthogonal signals after completing analog-to-digital conversion, and are transmitted to the digital down-conversion module to mix with the local digital carrier signal to achieve digital down-conversion and then output to the signal output module; S6. After the digital up-conversion module receives the digital baseband signal transmitted by the IQ digital baseband signal module, it mixes it with the local digital carrier signal to achieve digital up-conversion and then outputs it to the DA conversion module for digital-to-analog conversion. At the same time, the pre-stored phase-locked loop second adjusts the second analog carrier signal according to the preset optimal phase-locked loop tuning parameters in the order of the IQ digital baseband signal to complete the rapid jump of the analog carrier signal; S7. The baseband signal after digital-to-analog conversion by the DA conversion module is mixed with the second analog carrier signal by a second mixer and then output to the RF transmission module for transmission.

7. The method for implementing a fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 6, characterized in that: Both the memory 1 and the memory 2 include a gain control storage module storing the initial gains of the RF receiving module and the RF transmitting module, and a phase-locked loop storage module storing the optimal phase-locked loop tuning parameters of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2. The gain control storage module of the RF receiving module and the RF transmitting module is preset using an initial gain table, and the programmable registers of the pre-stored phase-locked loop 1 and the pre-stored phase-locked loop 2 are quickly preset according to the optimal phase-locked loop tuning parameters.

8. The method for implementing a fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 7, characterized in that: The parameters stored in the frequency tuning parameter table are the optimal phase-locked loop tuning parameters for each frequency point when the phase-locked loop self-tunes and locks after the fast frequency hopping system of the ultra-wideband agile frequency radar performs a self-tuning process, and each of the optimal phase-locked loop tuning parameters is stored in the order of the frequency points of the external signal.

9. The method for implementing a fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 7, characterized in that: The programmable register pre-stored in the first phase-locked loop includes a first high-speed cache and a second high-speed cache, and the steps of quickly pre-setting the programmable register pre-stored in the first phase-locked loop are: A1. Finding corresponding optimal phase-locked loop tuning parameters from the first memory according to the frequency sequence of the external signal, and writing the found optimal phase-locked loop tuning parameters into the first cache and the second cache in advance according to the odd and even numbers of the frequency sequence, wherein if the number of the optimal phase-locked loop tuning parameter stored in the first cache is odd, the number of the optimal phase-locked loop tuning parameter stored in the second cache is even; A2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the first cache and the second cache in a ping-pong manner.

10. The method for implementing a fast frequency hopping system of an ultra-wideband frequency agile radar according to claim 7, characterized in that: The programmable registers pre-stored in the second phase-locked loop include a third high-speed cache and a fourth high-speed cache, and the steps of quickly pre-setting the programmable registers pre-stored in the second phase-locked loop are: B1. Finding corresponding optimal phase-locked loop tuning parameters from the second memory according to the frequency sequence of the external signal, and writing the found optimal phase-locked loop tuning parameters into the third cache and the fourth cache in advance, alternately according to the odd and even numbers of the frequency sequence, wherein if the number of the optimal phase-locked loop tuning parameter stored in the third cache is odd, the number of the optimal phase-locked loop tuning parameter stored in the fourth cache is even; B2. When frequency hopping is required, optimal phase-locked loop tuning parameters corresponding to the frequency points are read alternately from the third cache and the fourth cache in a ping-pong manner.

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