Back contact solar cell and method of manufacturing the same

Abstract

The application relates to the photovoltaic field and discloses a back contact solar cell and a manufacturing method thereof. The back surface of a silicon wafer has a first region and a second region which are spaced apart, and a porous dot array is formed in a tunneling layer located at the first region of the back surface of the silicon wafer; a doped polysilicon layer is formed on the surface of the tunneling layer away from the silicon wafer, and the doping concentration of the doped polysilicon layer gradually decreases in the direction away from the tunneling layer. Many holes are formed in the tunneling layer, thereby forming a carrier tunneling channel in the tunneling layer, and the doping atoms in the doped polysilicon layer form atom-level "pinholes" on the surface of the tunneling layer, so that the tunneling contact resistance is small. The doping concentration of the region of the doped polysilicon layer in contact with the tunneling layer is the highest, and the tunneling layer and the region jointly form a higher asymmetric offset barrier layer, allowing majority carriers to pass through and minority carriers not to pass through, so that the collection of the majority carriers is more uniform and unimpeded, the passivation effect is improved, and the efficiency of the cell is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaics, and in particular to a back-contact solar cell and a method for manufacturing the same. Background Technology

[0002] In an IBC (interdigitated back contact) battery, the positive and negative metal electrodes are arranged in an interdigital pattern on the back of the battery, with no metal electrodes blocking the front. This allows the light incident on the front of the battery to be utilized as much as possible, increasing the battery's current density and thus improving its photoelectric conversion efficiency.

[0003] Taking a P-type IBC battery as an example, SiO is formed in the N-region on the back of the battery. x Tunneling layer and N-type doped polycrystalline silicon layer, SiO x The tunneling layer is generally formed by LPCVD (low-pressure chemical vapor deposition) or PECVD (pasma-enhanced chemical vapor deposition), with SiO₂ as the deposition material. x Uneven tunneling layer thickness can easily lead to excessive tunneling resistance, poor passivation, and low carrier selectivity, resulting in low cell efficiency and even a certain proportion of inefficient and defective cells. Furthermore, in N-type doped polysilicon layers, the dopant elements are uniformly distributed within the polysilicon layer, leading to a relatively high tunneling contact resistance between the N-type doped polysilicon layer and the tunneling layer. This hinders the collection of most carriers, further limiting cell efficiency.

[0004] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a back-contact solar cell and a method for manufacturing the same, so as to improve the passivation effect and increase the efficiency of the cell.

[0006] To address the aforementioned technical problems, this application provides a method for fabricating a back-contact solar cell, comprising:

[0007] The back side of the silicon wafer has a first region and a second region spaced apart, and a porous lattice is formed in the tunneling layer located in the first region on the back side of the silicon wafer.

[0008] A doped polycrystalline silicon layer is formed on the surface of the tunneling layer away from the silicon wafer, and the doping concentration in the doped polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer.

[0009] Optionally, forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer includes:

[0010] The tunneling layer is etched to form a porous lattice that does not completely penetrate the tunneling layer.

[0011] Optionally, forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer includes:

[0012] The tunneling layer is etched using a laser or an etchant containing additives to form a porous lattice within the tunneling layer.

[0013] Optionally, forming a doped polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer includes:

[0014] An intrinsic polycrystalline silicon layer is deposited on the surface of the tunneling layer opposite to the silicon wafer;

[0015] The intrinsic polycrystalline silicon layer is doped by multiple diffusion processes to form the doped polycrystalline silicon layer.

[0016] Optionally, the region of the doped polycrystalline silicon layer closest to the tunneling layer has a doping concentration of 1E20 to 6E20 atoms / cm². 3 The region of the doped polycrystalline silicon layer furthest from the tunneling layer has a doping concentration of 1E19–3E20 atoms / cm². 3 .

[0017] Optionally, when using a laser to etch the tunneling layer, the laser pulse width ranges from 1 ps to 50 ns, and the laser wavelength ranges from 200 to 800 nm.

[0018] Optionally, when etching the tunneling layer using an etchant containing additives, the concentration of the etchant ranges from 0.5% to 15%.

[0019] Optionally, before forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer, the method further includes:

[0020] The tunneling layer is deposited on the back side of the silicon wafer, wherein the tunneling layer is any one or any combination of silicon carbide, silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide.

[0021] Optionally, depositing the tunneling layer in a first region on the back side of the silicon wafer includes:

[0022] The tunneling layer is deposited on the back side of the silicon wafer using any one or any combination of PECVD, PEALD, LPCVD, PVD, and ALD.

[0023] This application also provides a back-contact solar cell, comprising: a silicon wafer, wherein the back side of the silicon wafer has a first region and a second region with different doping types distributed at intervals; the first region is provided with a tunneling layer and a doped polycrystalline silicon layer, the tunneling layer having a porous lattice, and the doping concentration in the doped polycrystalline silicon layer gradually decreasing in the direction away from the tunneling layer.

[0024] Optionally, the porous lattice does not completely penetrate the tunneling layer.

[0025] Optionally, the tunneling layer is any one or any combination of silicon carbide, silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide.

[0026] The present application provides a method for fabricating a back-contact solar cell, comprising: a first region and a second region spaced apart on the back side of a silicon wafer; forming a porous lattice in a tunneling layer located in the first region on the back side of the silicon wafer; and forming a doped polycrystalline silicon layer on the surface of the tunneling layer away from the silicon wafer, wherein the doping concentration in the doped polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer.

[0027] As can be seen, in the cell fabrication process of this application, numerous pores are formed in the tunneling layer, thereby creating carrier tunneling channels on the surface of the tunneling layer. Simultaneously, dopant atoms in the polycrystalline silicon layer form atomic-level "pinholes" on the surface of the tunneling layer, resulting in low tunneling contact resistance. Furthermore, the region in the polycrystalline silicon layer that contacts the tunneling layer has the highest doping concentration, forming a higher asymmetric offset barrier layer together with the tunneling layer. This allows majority carriers to pass through while preventing minority carriers from passing, resulting in more uniform and unobstructed collection of majority carriers, improved passivation, and ultimately, increased solar cell efficiency.

[0028] In addition, this application also provides a back-contact solar cell with the above-mentioned advantages. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A flowchart illustrating a method for fabricating a back-contact solar cell, as provided in this application embodiment;

[0031] Figure 2 This is a schematic diagram of the structure of a back-contact solar cell provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the structure of an incompletely penetrating hole in the tunneling layer in an embodiment of this application. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0034] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0035] As described in the background section, the uneven thickness of the tunneling layer in back-contact solar cells can easily lead to problems such as excessive tunneling resistance, poor passivation effect, and low carrier selectivity, resulting in low cell efficiency. At the same time, the tunneling contact resistance between the N-type doped polycrystalline silicon layer and the tunneling layer is relatively large, which hinders the collection of most carriers and limits the cell efficiency.

[0036] In view of this, this application provides a method for fabricating a back-contact solar cell, please refer to... Figure 1 The method includes:

[0037] Step S101: The back side of the silicon wafer has a first region and a second region distributed at intervals, and a porous lattice is formed in the tunneling layer located in the first region on the back side of the silicon wafer.

[0038] The porous lattice includes numerous pores, which are of two types: those that penetrate the tunneling layer and those that do not completely penetrate the tunneling layer. Preferably, the pores in the porous lattice do not completely penetrate the tunneling layer to increase carrier selectivity while satisfying passivation and contact requirements. A schematic diagram of the structure of the partially penetrated pore 21 in the tunneling layer 2 is shown below. Figure 3 As shown.

[0039] It should be noted that this application does not limit the formation method of the porous lattice.

[0040] As one possible implementation, forming a porous lattice in a tunneling layer located in a first region on the back side of a silicon wafer includes:

[0041] The tunneling layer is etched using a laser to form a porous lattice within it.

[0042] When the tunneling layer is ablated using a laser, the laser pulse width can be 1ps to 50ns and the laser wavelength can be 200 to 800nm; corresponding regular lattice micropores are formed in the tunneling layer, with the size of the pores ranging from 0.1um to 50um and the spacing between the micropores ranging from 0.5um to 4mm.

[0043] By adjusting the wavelength, power, and pulse width of the laser, holes that do not completely penetrate the tunneling layer can be formed on the surface of the tunneling layer, thereby increasing carrier selectivity while satisfying passivation and contact requirements.

[0044] As another possible implementation, forming a porous lattice in a tunneling layer located in a first region on the back side of the silicon wafer includes:

[0045] The tunneling layer is etched using an etchant containing additives to form a porous lattice within the tunneling layer.

[0046] The additives enable selective etching by the etchant, protecting localized areas of the tunneling layer surface from corrosion and thus forming a porous lattice. The thickness of the etched tunneling layer is controlled between 0.1 nm and 10 nm.

[0047] The corrosive solution can be either acidic or alkaline, both of which are within the scope of protection of this application.

[0048] The additive material mainly contains organic / inorganic functional groups, which can effectively bind to the surface of the tunneling layer. However, due to the difference in bonding force, there are certain differences in surface protection, and therefore, there are certain differences in acid and alkali resistance. Thus, when acid or alkali is used, micro-corrosion pits can be formed, that is, a porous lattice is formed.

[0049] In order to form pores that do not completely penetrate the tunneling layer, protective additives are used to protect the tunneling layer, slow down the reaction rate of the corrosion liquid on the tunneling layer, and etch to form pores that do not completely penetrate the tunneling layer, so as to increase the carrier selectivity while satisfying passivation and contact.

[0050] When the tunneling layer is corroded using an etchant containing additives, the concentration of the acidic or alkaline etchant can be between 0.5% and 15%, depending on the specific additives, temperature, and reaction time.

[0051] In this embodiment, the silicon wafer is a P-type silicon wafer. After subsequent N-type doping (phosphorus doping), the first region corresponds to the N-type region of the battery, and the second region corresponds to the P-type region of the battery. When the silicon wafer is an N-type silicon wafer, the doped polycrystalline silicon layer is located over the entire back surface of the silicon wafer, and the doping type of the doped polycrystalline silicon layer corresponding to the N-type region is opposite to the doping type of the corresponding P-type region.

[0052] Optionally, in one embodiment of this application, before forming the porous lattice in the tunneling layer, the method further includes:

[0053] Double-sided polishing of the silicon wafer;

[0054] A tunneling layer is formed on the surface of the silicon wafer.

[0055] The purpose of polishing is to remove cutting damage from the silicon wafer surface, smooth the surface, and reduce surface defects. Conventional alkaline polishing can be used, employing solutions such as 5–20% potassium hydroxide, sodium hydroxide, or TMAH (tetramethylammonium hydroxide) at 60–90°C to carry out a chemical reaction. Polishing additives can also be added to the solution to further flatten the silicon wafer surface. Polishing additives are readily available for purchase.

[0056] The materials and specific manufacturing methods of the tunneling layer are described in the following embodiments.

[0057] Step S102: A doped polycrystalline silicon layer is formed on the surface of the tunneling layer away from the silicon wafer, wherein the doping concentration in the doped polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer.

[0058] To enhance the selectivity for charge carriers and thus improve battery efficiency, the region of the doped polycrystalline silicon layer closest to the tunneling layer has a doping concentration of 1E20 to 6E20 atoms / cm². 3 The region of the doped polycrystalline silicon layer furthest from the tunneling layer has a doping concentration of 1E19–3E20 atoms / cm². 3 .

[0059] It should be noted that this application does not limit the formation method of the doped polycrystalline silicon layer.

[0060] As one possible implementation, forming a doped polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer includes:

[0061] Step S102a1: Deposit an intrinsic polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer.

[0062] Step S102a2: The intrinsic polycrystalline silicon layer is doped using a multiple diffusion method to form the doped polycrystalline silicon layer.

[0063] To ensure that the doping concentration of the polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer, it is possible to control three aspects: doping source concentration, bonding temperature, and diffusion time. For example, the doping source concentration can be gradually reduced during multiple diffusions, the bonding temperature can be gradually decreased, and the diffusion time can be gradually shortened.

[0064] The diffusion process in this step mainly consists of three steps. After the first step of diffusion, the diffusion concentration reaches 5E20cm-3; after the second step of diffusion, the diffusion concentration reaches 3E20cm-3; and after the third step of diffusion, the diffusion concentration reaches 1E20cm-3.

[0065] The thickness of the intrinsic polycrystalline silicon layer can be between 30nm and 300nm, and the deposition method can be LPCVD, PEALD, PVD (Physical Vapor Deposition), etc.

[0066] As another possible implementation, forming a doped polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer includes:

[0067] Step S102b1: Deposit an intrinsic polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer.

[0068] Step S102b2: The intrinsic polycrystalline silicon layer is doped by multiple ion implantations to form the doped polycrystalline silicon layer.

[0069] To ensure that the doping concentration of the polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer, the implantation dose and time can be controlled.

[0070] The thickness of the intrinsic polysilicon layer can be between 30 nm and 300 nm.

[0071] Step S103: Remove the doped polysilicon layer on the back side of the silicon wafer corresponding to the second region.

[0072] It should be noted that before step 103 and after step S102, the process further includes: removing a portion of the oxide dielectric layer on the back side using a laser to separate the P-type and N-type regions, forming a PN junction at the P / N interface. The P-type region can account for 10% to 40%, with the remainder being the N-type region. The laser pulse width used is 1 ps to 15 ps, corresponding to a laser wavelength typically of 355 nm. The oxide dielectric layer is formed when the intrinsic polycrystalline silicon layer is doped. For example, if the silicon wafer is a P-type silicon wafer, and the intrinsic polycrystalline silicon layer is doped with phosphorus, the oxide dielectric layer is phosphosilicate glass.

[0073] Alkaline solutions (such as 5–20% potassium hydroxide solution, sodium hydroxide solution, TMAH solution, etc.) can be used at 60–90°C to remove the doped polycrystalline silicon layer corresponding to the P-type region. This process also removes laser damage, smooths the surface, and reduces surface defects. Polishing additives can also be added to the alkaline solution to further enhance surface flatness.

[0074] Step S104: Remove the oxide dielectric layer on the front side of the silicon wafer.

[0075] Methods for removing the oxide medium layer on the front side include chain-type single-sided removal with HF solution, HF and HCl mixture, HNO3 solution, etc.

[0076] Step S105: Deposit passivation layers on the front and back sides of the silicon wafer, respectively.

[0077] The passivation layer serves a chemical passivation function. The front passivation layer can be a stack of aluminum oxide, silicon nitride, and silicon oxide layers, with corresponding thicknesses of 2–20 nm, 50–80 nm, and 5–20 nm. Fabrication methods include, but are not limited to, PECVD, ALD (atomic layer deposition), and PEALD (pasma-enhanced atomic layer deposition). The back passivation layer can be a stack of aluminum oxide and silicon nitride layers, with corresponding thicknesses of 2–20 nm and 60–200 nm. Fabrication methods include, but are not limited to, PECVD, ALD, and PEALD.

[0078] Step S106: Electrodes are fabricated on the first and second regions on the back side of the silicon wafer to obtain a back-contact solar cell.

[0079] The first region corresponds to the N-type region, and the second region corresponds to the P-type region. Local openings are created in the N-type region using laser or acidic etching materials. The opening shape can be any of the following: dot-like, dot-spaced, line-like, line-spaced, or a combination of dot-like and line-spaced, with a diameter or width of 10–50 μm. It is important to note that only the passivation layer is removed in the opening areas, without damaging the underlying doped polysilicon layer. A low-etching silver paste or silver-aluminum paste, 50–100 μm wide, is printed above the opening areas in the N-type region to provide electrical contact with the doped polysilicon layer. An etchable silver paste is then printed above the doped polysilicon layer. The glassy component in the etchable silver paste opens the passivation layer, allowing the silver to contact the doped polysilicon layer. Electrode paste is printed directly onto the passivation layer in the P-type region, and then co-sintered at 600–800 °C to form the electrode.

[0080] In this application, numerous pores are formed in the tunneling layer during the cell fabrication process, thereby creating carrier tunneling channels on the surface of the tunneling layer. Simultaneously, dopant atoms in the polycrystalline silicon layer form atomic-level "pinholes" on the surface of the tunneling layer, resulting in low tunneling contact resistance. Furthermore, the region of the polycrystalline silicon layer in contact with the tunneling layer has the highest doping concentration, forming a higher asymmetric offset barrier layer together with the tunneling layer. This allows majority carriers to pass through while preventing minority carriers from passing, resulting in more uniform and unobstructed collection of majority carriers, improved passivation, and ultimately, increased solar cell efficiency.

[0081] Based on the above embodiments, in one embodiment of this application, after forming a doped polycrystalline silicon layer on the surface of the tunneling layer away from the silicon wafer, the method further includes:

[0082] The silicon wafer is texturized.

[0083] Specifically, texturing occurs after removing the oxide dielectric layer on the front side of the silicon wafer and before creating the passivation layer.

[0084] Alkaline solutions, such as 5-20% potassium hydroxide solution, sodium hydroxide solution, or TMAH solution, can be used during texturing, with the aid of texturing additives. A pyramid structure is formed in the area not covered by the oxide dielectric layer, resulting in a pyramidal textured surface on the entire front side, which serves to trap light. Simultaneously, texturing can also remove polysilicon from the front side.

[0085] To avoid the formation of a textured surface on the back side, after removing the doped polysilicon layer corresponding to the P-type region on the back side of the silicon wafer, an oxide layer can be formed on the back side of the wafer. The oxidation method can be either thermal oxidation or ultraviolet ozone oxidation. The oxide layer is then removed using an acidic solution after texturing.

[0086] Based on any of the above embodiments, in one embodiment of this application, before forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer, the method further includes:

[0087] The tunneling layer is deposited on the back side of the silicon wafer, wherein the tunneling layer is any one or any combination of silicon carbide, silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide.

[0088] The thickness of the tunneling layer can be between 0.1 nm and 10 nm.

[0089] In the prior art, the material of the tunneling layer is silicon oxide. In this application, the material of the tunneling layer can be silicon carbide, silicon nitride, silicon oxynitride, or aluminum oxide, in addition to silicon oxide, and has the same tunneling effect.

[0090] Optionally, depositing the tunneling layer on the back side of the silicon wafer includes:

[0091] The tunneling layer is deposited on the back side of the silicon wafer using any one or any combination of PECVD, PEALD, LPCVD, PVD, and ALD.

[0092] When depositing the tunneling layer, the entire surface can be deposited, and then the corresponding part of the second region can be removed later.

[0093] The fabrication method in this application will be described below using a P-type silicon wafer as an example.

[0094] Step 1: Double-sided polishing of P-type silicon wafers

[0095] Conventional alkaline polishing uses a 5-20% solution of potassium hydroxide, sodium hydroxide, TMAH containing polishing additives, and a chemical reaction is carried out at a temperature of 60-90℃ to achieve double-sided polishing.

[0096] Step 2: Deposit a tunneling layer on the back side

[0097] The tunneling layer is deposited using any one of LPCVD, PECVD, PEALD, PVD, or ALD. The tunneling layer can be one or more of Si oxide, nitride, oxynitride, or aluminum oxide, and its thickness is between 0.1 nm and 10 nm.

[0098] Step 3: Laser micro-ablation or wet micro-corrosion of the tunneling layer

[0099] When using the dry method, laser is used to perform micro-ablation on the surface of the tunneling layer. The laser pulse width is 1ps-50ns and the wavelength is 200-800nm, forming corresponding regular lattice micropores on the surface of the tunneling layer. The size of the pores is 0.1um-50um and the spacing between the micropores is 0.5um-4mm.

[0100] When using a wet process, an acidic or alkaline solution containing additives is used to micro-corrode the tunneling layer, forming a porous structure on the surface of the tunneling layer. The thickness of the tunneling layer after corrosion is controlled between 0.1 nm and 10 nm.

[0101] Step 4: Deposit an intrinsic amorphous silicon layer

[0102] Using any of the methods LPCVD, PEALD, or PVD, an intrinsic amorphous silicon layer with a thickness between 30 nm and 300 nm is deposited on the surface of the tunneling layer.

[0103] Step 5, n-type doping

[0104] P doping was achieved through a multi-step P (phosphorus) diffusion process, with P doping concentrations near the tunneling layer ranging from 1E20 to 6E20 atoms / cm². 3 The P-doping concentration far from the tunneling layer is 1E19~3E20 atoms / cm 3 ;

[0105] Step 6: Laser Graphics

[0106] Picosecond ultraviolet laser is used to remove part of the PSG layer on the back side, thereby separating the P-type and n-type regions and forming a PN junction at the P / N interface. The P-type region accounts for 10%-40%, and the remainder is the N-type region. The laser pulse width used is 1ps-15ps, and the corresponding laser wavelength is 355nm.

[0107] Step 7: Alkali washing + oxidation

[0108] Conventional alkaline polishing uses 5-20% potassium hydroxide, sodium hydroxide, TMAH solution, etc., to carry out a chemical reaction at a temperature of 60-90℃. Adding polishing additives helps to make the surface flatter. The purpose is to remove laser damage and N-type doped polysilicon layer in the P-region, smooth the surface, and reduce surface defects.

[0109] A protective layer is formed on the back polished area by using thermal oxygen or ultraviolet ozone to prevent the formation of a napped surface during the napping process.

[0110] Step 8: Remove PSG+ from the fabric.

[0111] The PSG layer on the front side is removed using an acidic solution via a chain-like single-sided method.

[0112] Texturing is performed using a 5-20% potassium hydroxide, sodium hydroxide, and TMAH solution to form a pyramid structure in the area not covered and protected by the PSG layer. That is, the entire front surface is a pyramid textured surface, which serves to trap light and remove the poly-Si on the front surface through texturing.

[0113] Step 9: Front and back stack passivation

[0114] Hydrogen-containing dielectric layers are deposited on the front and back sides to chemically passivate the back surface. The back side is an aluminum oxide + silicon nitride stacked film, and the front side is an aluminum oxide + silicon nitride + silicon oxide stacked film.

[0115] Step 10, Backside Metallization

[0116] The N-type region is partially opened using laser or acid etching materials without damaging the underlying N-type polysilicon layer. Low-corrosion silver paste or silver-aluminum paste is printed above the opening area of ​​the N-type region, and etchable silver paste is printed above the N-type polysilicon. The glassy substance in the etchable silver paste can open the passivation layer, allowing silver to contact the N-type polysilicon. Electrode paste is directly printed in the P-type region and co-sintered at 600-800℃ to form the electrode.

[0117] This application also provides a back-contact solar cell, such as Figure 2 As shown, it includes: a silicon wafer 1, the back side of which has a first region and a second region with different doping types distributed at intervals; the first region is provided with a tunneling layer 2 and a doped polycrystalline silicon layer 3, the tunneling layer 2 has a porous lattice, and the doping concentration in the doped polycrystalline silicon layer 3 gradually decreases in the direction away from the tunneling layer 2.

[0118] The back-contact solar cell also includes a front passivation layer 5 disposed on the front side of the silicon wafer 1, a back passivation layer 4 disposed on the back side of the silicon wafer 1, and an electrode 6. The front passivation layer 5 can be a stack of aluminum oxide layer, silicon nitride layer, and silicon oxide layer, and the back passivation layer 4 can be a stack of aluminum oxide layer and silicon nitride layer.

[0119] Silicon wafer 1 can be a P-type silicon wafer, and the doping type of polycrystalline silicon layer 3 is N-type doping, with phosphorus as the doping element. Correspondingly, the first region is an N-type region and the second region is a P-type region.

[0120] The tunneling layer 2 includes, but is not limited to, any one or any combination of silicon carbide layer, silicon nitride layer, silicon oxynitride layer, silicon oxide layer, and aluminum oxide layer.

[0121] The porous lattice includes many pores, which are of two types: one is a pore that penetrates the tunneling layer, and the other is a pore that does not fully penetrate the tunneling layer. Preferably, the pores in the porous lattice do not fully penetrate the tunneling layer in order to increase carrier selectivity while satisfying passivation and contact requirements.

[0122] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0123] The foregoing has provided a detailed description of the back-contact solar cell and its fabrication method provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for manufacturing a back-contact solar cell, characterized in that, include: The back side of the silicon wafer has a first region and a second region spaced apart, and a porous lattice is formed in the tunneling layer located in the first region on the back side of the silicon wafer. A doped polycrystalline silicon layer is formed on the surface of the tunneling layer away from the silicon wafer, and the doping concentration in the doped polycrystalline silicon layer gradually decreases in the direction away from the tunneling layer; Forming a doped polycrystalline silicon layer on the surface of the tunneling layer opposite to the silicon wafer includes: An intrinsic polycrystalline silicon layer is deposited on the surface of the tunneling layer opposite to the silicon wafer; The intrinsic polycrystalline silicon layer is doped using a multiple diffusion process to form the doped polycrystalline silicon layer. During doping, the dopant concentration, junction temperature, and diffusion time are controlled. The dopant concentration, junction temperature, and diffusion time gradually decrease during the multiple diffusion processes. The diffusion occurs in three steps; after the first diffusion step, the diffusion concentration reaches 5E20cm⁻¹. -3 After the second diffusion step, the diffusion concentration reached 3E20cm³. -3 After the third diffusion step, the diffusion concentration reaches 1E20cm³. -3 ; Alternatively, forming a doped polysilicon layer on the surface of the tunneling layer opposite to the silicon wafer includes: An intrinsic polycrystalline silicon layer is deposited on the surface of the tunneling layer opposite to the silicon wafer; the intrinsic polycrystalline silicon layer is doped by multiple ion implantations to form the doped polycrystalline silicon layer; the implantation dose and time are controlled during ion implantation.

2. The method for manufacturing a back-contact solar cell as described in claim 1, characterized in that, Forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer includes: The tunneling layer is etched to form a porous lattice that does not completely penetrate the tunneling layer.

3. The method for fabricating a back-contact solar cell as described in claim 1 or 2, characterized in that, Forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer includes: The tunneling layer is etched using a laser or an etchant containing additives to form a porous lattice within the tunneling layer.

4. The method for fabricating a back-contact solar cell as described in claim 1, characterized in that, The region of the doped polycrystalline silicon layer closest to the tunneling layer has a doping concentration of 1E20~6E20 atoms / cm². 3 The region of the doped polycrystalline silicon layer furthest from the tunneling layer has a doping concentration of 1E19~3E20 atoms / cm². 3 .

5. The method for fabricating a back-contact solar cell as described in claim 2, characterized in that, When etching the tunneling layer using a laser, the laser pulse width ranges from 1 ps to 50 ns, and the laser wavelength ranges from 200 to 800 nm.

6. The method for manufacturing a back-contact solar cell as described in claim 3, characterized in that, When etching the tunneling layer using an etchant containing additives, the concentration of the etchant ranges from 0.5% to 15%.

7. The method for manufacturing a back-contact solar cell as described in claim 1, characterized in that, Before forming a porous lattice in the tunneling layer located in the first region on the back side of the silicon wafer, the method further includes: The tunneling layer is deposited on the back side of the silicon wafer, wherein the tunneling layer is any one or any combination of silicon carbide, silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide.

8. The method for fabricating a back-contact solar cell as described in claim 7, characterized in that, Depositing the tunneling layer in a first region on the back side of the silicon wafer includes: The tunneling layer is deposited on the back side of the silicon wafer using any one or any combination of PECVD, PEALD, LPCVD, PVD, and ALD.

9. A back-contact solar cell obtained based on the back-contact solar cell manufacturing method according to any one of claims 1 to 8, characterized in that, include: A silicon wafer, the back side of which has a first region and a second region with different doping types distributed at intervals; the first region is provided with a tunneling layer and a doped polysilicon layer, the tunneling layer has a porous lattice, and the doping concentration in the doped polysilicon layer gradually decreases in the direction away from the tunneling layer.

10. The back-contact solar cell as described in claim 9, characterized in that, The porous lattice does not completely penetrate the tunneling layer.

11. The back-contact solar cell as described in claim 9 or 10, characterized in that, The tunneling layer is any one or any combination of silicon carbide, silicon nitride, silicon oxynitride, silicon oxide, and aluminum oxide.

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