Method of fabricating a multi-bit magnetic memory cell and memory cell

Abstract

The application provides a manufacturing method, a unit and a memory of a multi-bit magnetic storage unit. The method comprises the following steps: forming a spin-orbit torque layer; forming at least one magnetic tunnel junction and at least one magnetic body on the spin-orbit torque layer, the magnetic tunnel junction is used for storing data, and the magnetic body is used for providing a magnetic leakage field for the magnetic tunnel junction, so that the asymmetry of the magnetic tunnel junction is enhanced. The application can increase the reading margin and reduce the power consumption.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a multi-bit magnetic memory cell and the memory cell itself. Background Technology

[0002] As semiconductor process dimensions continue to shrink and Moore's Law slows down, increased leakage current and interconnect delays have become bottlenecks for traditional CMOS memories. Finding solutions for next-generation memory technologies has become a key focus of integrated circuit research, with magnetic random access memory (MRAM) receiving widespread attention. Compared to traditional devices, MRAM offers advantages such as unlimited erase / write cycles, non-volatility, fast read / write speeds, and radiation resistance, making it a promising candidate for general-purpose memory and an ideal device for building next-generation non-volatile memories and in-memory computing. To further increase the storage density of spin-orbit moment (SMT) devices, researchers have proposed a quasi-two-ended NAND-SPIN structure. This structure achieves multi-bit data storage by fabricating two or more magnetic tunnel junctions (MTJs) on the same spin-orbit moment layer. Since the MTJs share transistors connected to the spin-orbit moment layer, the overall number of transistors required is reduced, effectively increasing storage density.

[0003] To address this structure, researchers have proposed corresponding data writing schemes. One such scheme involves using a spin orbit torque (SOT) current to erase all magnetic tunnel junctions to the first state, and then using a spin transfer torque (STT) current to write a portion of the magnetic tunnel junctions to the second state. However, the read margin and power consumption of NAND-SPIN limit its performance improvement. Summary of the Invention

[0004] One object of the present invention is to provide a method for manufacturing a multi-bit magnetic memory cell, which increases read margin and reduces power consumption. Another object of the present invention is to provide a multi-bit magnetic memory cell.

[0005] To achieve the above objectives, this invention discloses a method for fabricating a multi-bit magnetic storage cell, comprising:

[0006] Formation of spin-orbit moment layers;

[0007] At least one magnetic tunnel junction and at least one magnetic body are formed on the spin orbital moment layer. The magnetic tunnel junction is used to store data, and the magnetic body is used to provide a leakage magnetic field for the magnetic tunnel junction, thereby enhancing the asymmetry of the magnetic tunnel junction.

[0008] Preferably, it further includes:

[0009] A protective dielectric layer is formed on the at least one magnetic tunnel junction and the at least one magnetic body.

[0010] Preferably, the method further includes:

[0011] The magnetic material is broken down.

[0012] Preferably, the magnetic body includes a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer and a third ferromagnetic layer arranged sequentially from top to bottom, wherein the third ferromagnetic layer is formed on the spin orbital layer;

[0013] The method further includes:

[0014] At least one of the first ferromagnetic layer, the second ferromagnetic layer, the insulating layer, and the third ferromagnetic layer of the magnetic material is etched away to form a first hollow region;

[0015] Magnetic materials or protective media are deposited in the first hollow region.

[0016] Preferably, the method further includes:

[0017] The magnetic material is etched away to form a second hollow region;

[0018] Magnetic material is deposited in the second hollow region.

[0019] Preferably, the number of the magnetic tunnel junction and the magnetic body is multiple;

[0020] In this configuration, one or more of the magnetic tunnel junctions and one or more of the magnetic bodies are spaced apart along the direction of the spin orbit moment current input to the spin orbit moment layer.

[0021] Preferred,

[0022] One or two of the magnetic tunnel junctions and one or two of the magnetic bodies are spaced apart along the direction of the spin orbit moment current input to the spin orbit moment layer.

[0023] Preferably, it further includes:

[0024] A first electrode is disposed at the top of the magnetic tunnel junction;

[0025] A second electrode is disposed on the top of at least one of the magnetic bodies.

[0026] Preferably, it further includes:

[0027] The second electrode of the magnetic body with the second electrode is connected to the data writing module. The data writing module is used to determine the writing current path of the corresponding magnetic tunnel junction according to the data to be written, and write the spin-orbit moment current through the current input terminal of the second electrode or the spin-orbit moment layer on the writing current path to write the data to be written into the corresponding magnetic tunnel junction.

[0028] This application also discloses a multi-bit magnetic storage cell, which is fabricated by the method described above.

[0029] This invention discloses a method for fabricating multi-bit magnetic memory cells, which involves forming a spin-orbit matrix layer. At least one magnetic tunnel junction and at least one magnetic element are formed on the spin-orbit matrix layer. The magnetic tunnel junction stores data, and the magnetic element provides a leakage magnetic field for the magnetic tunnel junction. By adding a magnetic tunnel junction that provides a leakage magnetic field, this invention enhances the write asymmetry of the memory cell, increases read margin, and reduces STT write power consumption, thereby optimizing the high reliability and low power consumption performance of NAND-SPIN. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This diagram illustrates the structure of a multi-bit magnetic storage cell in the prior art.

[0032] Figure 2 A flowchart illustrating a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention;

[0033] Figure 3 A flowchart illustrating a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention, including step S300, is provided.

[0034] Figure 4 A flowchart illustrating a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention, including step S400, is provided.

[0035] Figure 5 A schematic diagram of a magnetic tunnel junction and a magnetic body is shown in a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention.

[0036] Figure 6 A flowchart illustrating the etching process of the magnetic body portion in a specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention is shown.

[0037] Figure 7 This diagram illustrates a specific embodiment of the fabrication method for a multi-bit magnetic storage cell of the present invention, showing the etching of the magnetic body portion.

[0038] Figure 8 A flowchart illustrating the etching of the entire magnetic body in a specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention is shown.

[0039] Figure 9 This diagram illustrates a specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention, showing the complete etching of the magnetic material;

[0040] Figure 10 and Figure 11 The diagram illustrates a specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention, showing two arrangement methods: magnetic tunnel junction and magnetic body.

[0041] Figure 12 A flowchart illustrating the specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention, showing the setting of the first electrode;

[0042] Figure 13 A schematic diagram showing a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention, illustrating the setting of the first electrode;

[0043] Figure 14 The flowchart illustrates a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention, showing the setup of the first and second electrodes;

[0044] Figure 15 A schematic diagram showing a specific embodiment of the fabrication method of the multi-bit magnetic storage cell of the present invention, illustrating the setting of the first electrode and the second electrode;

[0045] Figure 16 A flowchart illustrating a specific embodiment of the method for fabricating a multi-bit magnetic storage cell according to the present invention, including step S900, is provided.

[0046] Figure 17 A schematic diagram of a computer device suitable for implementing embodiments of the present invention is shown. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] It should be noted that, in one or more embodiments of the present invention, NAND-SPIN refers to a multi-bit storage cell in which two or more magnetic tunnel junctions are fabricated on the same spin orbital layer.

[0049] It should be noted that, in one or more embodiments of the present invention, TST (Toggle-spin torques) writing refers to writing data into the storage cell by simultaneously or overlapping the application of SOT current and STT current.

[0050] It should be noted that, in one or more embodiments of the present invention, the VCMA effect (Voltage-controlled magnetic anisotropy effect) refers to the phenomenon that by applying a voltage across a specific device (e.g., a magnetic tunnel junction), the anisotropy of the device is increased or decreased, thereby increasing or decreasing the critical switching current of the device.

[0051] In existing technologies, data writing to multi-bit magnetic storage cells typically involves erasing or writing all magnetic tunnel junctions to the AP (Antiparallel) state using a SOT (Site-Tight) current, followed by a STT (Site-Tight) current to transition from the AP state to the P (Parallel) state. When data writing asymmetry is enhanced, such as an increase in the critical switching current from the P state to the AP state, this means an increase in the read margin; conversely, a decrease in the critical switching current from the AP state to the P state means a decrease in STT current writing power consumption, resulting in an overall reduction in power consumption.

[0052] Authorized invention patent CN108538328 B, "A Data Writing Method for a Magnetic Memory," discloses a NAND-SPIN data writing scheme. In this patent, SOT and STT currents are applied simultaneously or overlappingly to collaboratively achieve data writing. The final state of the memory cell is determined by the direction of the STT current. By extension, the required STT critical current can be increased or decreased by adjusting the SOT current. Similarly, this patent also suffers from the problem of increasing asymmetry and adding operational steps by using TST.

[0053] like Figure 1 As shown, patent CN201710812254.7, "A High-Density Magnetic Storage Device," discloses a NAND-SPIN structure. However, this structure does not involve any design that increases write asymmetry, and there is considerable room for optimization in read margin and write power consumption. Furthermore, each MTJ serves as a data storage MTJ.

[0054] In summary, increasing asymmetry is an effective means to improve NAND-SPIN performance. When data write asymmetry is enhanced, such as an increase in the critical switching current from the second state to the first state, this means an increase in read margin; conversely, a decrease in the critical switching current from the first state to the second state means a decrease in STT current write power consumption, resulting in overall power consumption reduction. This invention proposes a multi-bit magnetic memory cell that increases write asymmetry by adding a magnetic tunnel junction that provides a leakage magnetic field, thereby improving the data read / write performance of the multi-bit magnetic memory cell, increasing read margin, and reducing power consumption. Compared to existing technologies that enhance write asymmetry through the VCMA effect, this application enhances write asymmetry by setting a magnetic material. The fabrication process of the magnetic material is compatible with that of MTJ (Metal-to-Jack) and does not require consideration of the VCMA effect. Therefore, the magnetic memory cell of this application does not require precise control of interface quality during fabrication, nor does it require setting up related circuit structures to control the intensity of the VCMA effect. This application has high simplicity and feasibility.

[0055] Based on this, according to one aspect of the present invention, this embodiment discloses a method for fabricating a multi-bit magnetic storage cell. For example... Figure 2 As shown, in this embodiment, the method includes:

[0056] S100: Forms a spin-orbit moment layer C;

[0057] S200: At least one magnetic tunnel junction M and at least one magnetic body N are formed on the spin-orbit matrix C. The magnetic tunnel junction M is used to store data, and the magnetic body N is used to provide a leakage magnetic field for the magnetic tunnel junction M, thereby enhancing the asymmetry of the magnetic tunnel junction M. The method for fabricating a multi-bit magnetic memory cell of the present invention forms a spin-orbit matrix C; at least one magnetic tunnel junction M and at least one magnetic body N are formed on the spin-orbit matrix C. The magnetic tunnel junction M is used to store data, and the magnetic body N is used to provide a leakage magnetic field for the magnetic tunnel junction M. The size of the magnetic body N is larger than the size of the magnetic tunnel junction M. By adding a magnetic tunnel junction M that can provide a leakage magnetic field, the magnetic tunnel junction M used for storing data is affected by the magnetic body N, thereby increasing the write asymmetry of the memory cell, increasing the read margin, and reducing STT write power consumption, achieving high reliability and low power consumption performance optimization for NAND-SPIN.

[0058] Preferably, the magnetic material N can be formed together with the magnetic tunnel junction M in a single process to reduce the manufacturing complexity of the magnetic storage unit. More preferably, the size of the magnetic material N, formed simultaneously with the magnetic tunnel junction M, can be larger than the size of the magnetic tunnel junction M, so that the magnetic material N can form a stronger leakage magnetic field and enhance the asymmetry of the magnetic tunnel junction M.

[0059] Specifically, the magnetic layer in the magnetic tunnel junction M is made of ferromagnetic material B5. Therefore, the magnetic layer or multiple magnetic layers in the magnetic tunnel junction M will exhibit a certain degree of magnetism (leakage magnetic field, or dipolar interaction, or stray field). Even after the pinning layer A1 is fabricated, the leakage magnetic field exhibited by the magnetic tunnel junction M is difficult to completely eliminate. Therefore, the magnetic body N formed simultaneously with the magnetic tunnel junction M will also exhibit a leakage magnetic field. When the distance between the magnetic tunnel junction M and the magnetic body N is close, the effect of the leakage magnetic field is more pronounced. As a result, the anisotropy of the magnetic tunnel junction M is reduced on one side due to the influence of the leakage magnetic field of the magnetic body N. This avoids barrier breakdown caused by excessive write voltage while reducing power consumption. It also eliminates the need for an input STT current to jointly overcome the anisotropy of the magnetic tunnel junction M, thus increasing the STT asymmetry and read margin.

[0060] It is understandable that the leakage magnetic field of magnetic material N is related to the direction of its magnetic moment (analogous to a reference magnetic hysteresis loop). The magnetic tunnel junction M surrounding magnetic material N is equivalent to being subjected to an equivalent magnetic field similar to a magnetic hysteresis loop. Therefore, by adjusting M and N, the energies of the magnetic tunnel junction M in the AP and P states can be made unequal, thus enhancing the asymmetry of STT writing.

[0061] In a preferred embodiment, such as Figure 3 As shown, the method further includes:

[0062] S300: A protective dielectric layer is formed on the at least one magnetic tunnel junction M and the at least one magnetic body N.

[0063] It is understandable that a protective dielectric layer is formed on the magnetic tunnel junction M and the magnetic body N. This protective dielectric layer is formed of an insulating material, which can keep the magnetic tunnel junction M and the magnetic body N isolated and can also maintain the stability of the magnetic tunnel junction M and the magnetic body N without tilting.

[0064] In a preferred embodiment, such as Figure 4 As shown, the method further includes:

[0065] S400: Breakdown of the magnetic body N.

[0066] It is understandable that after the magnetic material N is formed, it can be subjected to a breakdown process to reduce the magnetic resistance of the magnetic material N and increase the leakage magnetic field strength.

[0067] In an optional embodiment, the magnetic tunnel junction M includes, from top to bottom, a pinned layer A1, a fixed layer A2, a barrier layer A3, and a free layer A4, wherein the free layer A4 is formed on the spin-orbit moment layer C. The magnetic body N includes, from top to bottom, a first ferromagnetic layer B1, a second ferromagnetic layer B2, an insulating layer B3, and a third ferromagnetic layer B4, as shown below. Figure 5 As shown. Figure 6 As shown, the method further includes:

[0068] S510: Etching away at least one of the first ferromagnetic layer B1, the second ferromagnetic layer B2, the insulating layer B3, and the third ferromagnetic layer B4 of the magnetic body N forms a first hollow region.

[0069] S520: Deposit magnetic material B5 or a protective medium in the first hollow region.

[0070] It is understandable that, such as Figure 7 As shown, after obtaining the magnetic body N, at least one of the first ferromagnetic layer B1, the second ferromagnetic layer B2, the insulating layer B3 and the third ferromagnetic layer B4 of the magnetic body N can be etched by photolithography or other processes to form a first hollow region. Magnetic material B5 or a protective medium is deposited in the first hollow region to improve the magnetic field strength of the leakage magnetic field formed by the surrounding magnetic tunnel junction M.

[0071] In another alternative implementation, such as Figure 8 As shown, the method further includes:

[0072] S610: Etch away the magnetic material N to form a second hollow region.

[0073] S620: Magnetic material B5 is deposited in the second hollow region.

[0074] It is understandable that, such as Figure 9 As shown, after the magnetic material N is fabricated, all layers of the magnetic material N can be etched using processes such as photolithography to form voids, i.e., the second hollow region. Then, magnetic material B5 is filled into the second hollow region to form a leakage magnetic field on the surrounding magnetic tunnel junction M through the filled magnetic material B5. In this optional embodiment, since the second hollow region is entirely filled with magnetic material B5, the magnetic field strength of the formed leakage magnetic field is relatively strong, which can reduce the size of the magnetic material N and thus reduce costs.

[0075] In a preferred embodiment, there are multiple magnetic tunnel junctions M and magnetic bodies N.

[0076] In this configuration, one or more of the magnetic tunnel junctions M and one or more of the magnetic bodies N are spaced apart along the direction of the spin orbit moment current input to the spin orbit moment layer C.

[0077] It is understandable that by separating the magnetic body N and the magnetic tunnel junction M, the magnetic tunnel junction M in the memory cell can be affected by the leakage magnetic field of the magnetic body N.

[0078] Preferably, the plurality of magnetic tunnel junctions M and the plurality of magnetic bodies N can be arranged as follows: one or two magnetic tunnel junctions M and one or two magnetic bodies N are spaced apart along the direction of the spin-orbit moment current input to the spin-orbit moment layer C. In a specific example, the magnetic tunnel junctions M and magnetic bodies N can be arranged alternately, for example, ...NMNM..., where M represents magnetic body N and N represents magnetic tunnel junction M, as... Figure 10 As shown. In another specific example, the magnetic tunnel junction M and the magnetic body N can be arranged alternately, for example...NNMNNM..., as... Figure 11 As shown. Of course, in other embodiments, the magnetic tunnel junction M and the magnetic body N can also adopt a similar arrangement such as MMNNMMNN. Those skilled in the art can determine the arrangement of multiple magnetic tunnel junctions M and multiple magnetic bodies N according to actual needs, and the present invention does not limit this.

[0079] In a preferred embodiment, the distance between each magnetic tunnel junction M and the nearest magnetic body N is less than twice the size of the magnetic body N.

[0080] It is understood that the multiple magnetic tunnel junctions M and multiple magnetic bodies N can be arranged in various ways. Preferably, the distance between each magnetic tunnel junction M and its nearest magnetic body N is less than twice the size of the magnetic body N, that is, less than twice the horizontal size of the magnetic tunnel junction M, to ensure that each magnetic tunnel junction M is affected by the leakage magnetic field of the magnetic body N. Of course, in practical applications, those skilled in the art can determine the distance between the magnetic tunnel junction M and the nearest magnetic body N according to the actual situation. This is only an example and is not a limitation of this application.

[0081] In a preferred embodiment, such as Figure 12 As shown, the method further includes:

[0082] S700: A first electrode is disposed on top of the magnetic tunnel junction M.

[0083] It is understandable that the magnetic tunnel junction M is used to store data. When writing data to the magnetic tunnel junction M, a write current needs to be input to the magnetic tunnel junction M so that the resistance state of the magnetic tunnel junction M corresponds to the write current, thereby achieving the purpose of data writing. By setting a first electrode on the top of the magnetic tunnel junction M, the magnetic tunnel junction M can be connected to an external data writing module through the first electrode. The data writing module can then input a data writing current to the magnetic tunnel junction M through the first electrode. Furthermore, the first electrode can also be used to read the resistance state of the magnetic tunnel junction M. The data reading module of the multi-bit magnetic memory can input a read signal to the magnetic tunnel junction M through the first electrode, and determine the resistance state of the magnetic tunnel junction M by the change in the read signal, thereby determining the data stored in the magnetic tunnel junction M.

[0084] like Figure 13 As shown, a first electrode can be set on the top of the magnetic tunnel junction M. The first electrode can be connected to the data writing module or the data reading module through switching elements such as transistors. The switching elements can be turned on or off by control signals, thereby controlling the data writing module or the data reading module to input the corresponding data writing current or reading signal to the magnetic tunnel junction M.

[0085] In a preferred embodiment, such as Figure 14 As shown, the method further includes:

[0086] S800: A second electrode is disposed on top of at least one of the magnetic bodies N.

[0087] It is understood that the magnetic body N is used to provide a leakage magnetic field for the magnetic tunnel junction M, and thus an electrode may or may not be provided on the top of the magnetic body N. In this preferred embodiment, a second electrode is provided on the top of at least one magnetic body N. The magnetic body N with the second electrode can, on the one hand, input current to the magnetic body N through the second electrode to increase the strength of the leakage magnetic field formed by the magnetic body N, and on the other hand, the magnetic body N with the second electrode can be used as the bottom electrode of the magnetic tunnel junction M, that is, as the input or output terminal of the SOT current. For example, when the magnetic tunnel junction M is arranged as MNM, M can be part of the SOT current input path of N.

[0088] like Figure 15 As shown, a second electrode can be provided on the top of the magnetic body N. This second electrode can be connected to a switching element such as a transistor. The switching element can be turned on or off by a control signal, thereby controlling the input current or SOT current flowing through the magnetic body N.

[0089] In a preferred embodiment, such as Figure 16 As shown, the method further includes:

[0090] S900: Connect the second electrode of the magnetic body N with the second electrode to the data writing module. The data writing module is used to determine the writing current path of the corresponding magnetic tunnel junction M according to the data to be written, and write the spin-orbit moment current through the second electrode or the current input terminal of the spin-orbit moment layer C on the writing current path to write the data to be written into the corresponding magnetic tunnel junction M.

[0091] It is understood that the write current path of the corresponding magnetic tunnel junction M can be determined according to the data to be written. The SOT current input and output terminals of the write current path can be a spin orbital layer C or a magnetic body N with a second electrode. The multi-bit magnetic storage cell of the present invention has high data read and write flexibility and is simple to operate.

[0092] It is understood that the magnetic tunnel junction M may include, from top to bottom, a pinned layer A1, a fixed layer A2, a barrier layer A3, and a free layer A4. The resistance of the magnetic tunnel junction M depends on the magnetization directions of the fixed layer A2 and the free layer A4, which are determined by the magnetic moment directions. Specifically, when the magnetic moment directions of the fixed layer A2 and the free layer A4 are the same, the magnetic tunnel junction M is in a low-resistance state; when the magnetic moment directions of the fixed layer A2 and the free layer A4 are opposite, the magnetic tunnel junction M is in a high-resistance state. The high-resistance and low-resistance states of the magnetic tunnel junction M can be pre-assigned to different data. For example, the high-resistance state can be pre-set to correspond to the data "1", and the low-resistance state to correspond to the data "0". Then, by inputting current or voltage into the magnetic tunnel junction M through the reading circuit, the resistance state of the magnetic tunnel junction M can be determined as either a high-resistance state or a low-resistance state based on the change in current or voltage. Based on the resistance state of the magnetic tunnel junction M, the data stored in the magnetic tunnel junction M can be determined as either "1" or "0". Determining the range of the high-resistance and low-resistance states is a common technique in the art. Those skilled in the art can determine the resistance range of the high-resistance and low-resistance states of the magnetic tunnel junction M based on common knowledge, and this invention will not elaborate further.

[0093] In optional embodiments, the magnetic tunnel junction M may further include at least one of the following layered structures: an insertion layer, a seed layer, and a capping layer. The arrangement of each layer may be one or more layers depending on actual needs, and those skilled in the art can determine the top-to-bottom arrangement order of the layers in the magnetic tunnel junction M according to requirements; this invention does not limit this.

[0094] Optionally, the shape of the magnetic tunnel junction M on the spin-orbit moment layer C can be any of the following shapes: cube, cylinder, cubic, or elliptical cylinder. The bottom surface shape of at least one magnetic tunnel junction M disposed on the spin-orbit moment layer C, i.e., the lower surface of the free layer A4, is coupled to the spin-orbit moment layer C.

[0095] Preferably, the spin-orbit layer C can be rectangular, such that the top surface area of ​​the spin-orbit layer C is larger than the area occupied by at least one magnetic tunnel junction M disposed on the spin-orbit layer C, and at least one magnetic tunnel junction M can be disposed on the spin-orbit layer C, with the outer edge of at least one magnetic tunnel junction M located inside the outer edge of the spin-orbit layer C. Preferably, the spin-orbit layer C can be made of a heavy metal strip film, an antiferromagnetic strip film, or a topological insulator, etc.

[0096] Preferably, the materials of the first electrode and the second electrode can be any one of tantalum (Ta), aluminum (Al), gold (Au), or copper (Cu).

[0097] Preferably, the materials of the free layer A4 and the fixed layer A2 can be ferromagnetic metals, and the material of the barrier layer A3 can be an oxide. The magnetic tunnel junction M has perpendicular magnetic anisotropy, in-plane magnetic anisotropy, or an intermediate state between the two. The ferromagnetic metal can be a mixed metal material formed from at least one of cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or nickel-iron (NiFe), and the proportions of the mixed metal materials can be the same or different. The oxide can be one of magnesium oxide (MgO) or aluminum oxide (Al2O3), used to generate the tunneling magnetoresistance effect. In practical applications, other feasible materials can also be used for the ferromagnetic metal and oxide, and this invention does not limit this.

[0098] The free layer A4 of the magnetic tunnel junction M is fixed in contact with the spin orbital layer C. The layers of the magnetic tunnel junction M and the spin orbital layer C can be deposited on the substrate in a bottom-up order by traditional methods such as ion beam epitaxy, atomic layer deposition or magnetron sputtering. Then, the magnetic tunnel junction M is formed by traditional nanodevice processing technology such as photolithography and etching.

[0099] In this embodiment, the magnetic tunnel junction M includes a top pinned layer A1, a fixed layer A2, a free layer A4 in contact with the spin-orbit moment layer C, and a barrier layer A3 disposed between the fixed layer A2 and the free layer A4. The magnetic tunnel junction M includes only one free layer A4. In other embodiments, there may be multiple free layers A4, i.e., two or more free layers A4. Then the magnetic tunnel junction M includes a top fixed layer A2, multiple free layers A4, and a barrier layer A3 disposed between each pair of adjacent layers, with the bottom free layer A4 in contact with the spin-orbit moment layer C. For example, in a specific example, when two free layers A4 are included, the magnetic storage cell structure may include a spin-orbit moment layer C, a second free layer A4, a barrier layer A3, a first free layer A4, a barrier layer A3, a fixed layer A2, and a pinned layer A1 disposed sequentially on the spin-orbit moment layer C.

[0100] Based on the same principle, this embodiment also discloses a multi-bit magnetic storage cell. This multi-bit magnetic storage cell is fabricated using the method described in this embodiment.

[0101] Since the principle of solving the problem in this unit is similar to the methods described above, the implementation of this unit can be found in the implementation of the methods, and will not be repeated here.

[0102] Based on the same principle, this embodiment also discloses a multi-bit magnetic memory. The multi-bit magnetic memory includes multiple multi-bit magnetic storage cells arranged in an array as described in this embodiment.

[0103] Multi-bit magnetic storage includes both permanent and non-permanent, removable and non-removable media, and information storage can be achieved by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of applications for multi-bit magnetic storage include, but are not limited to, random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by computing devices.

[0104] Since the principle of this multi-bit magnetic memory in solving the problem is similar to that of the multi-bit magnetic storage unit described above, the implementation of this multi-bit magnetic memory can be referred to the implementation of the multi-bit magnetic storage unit described above, and will not be repeated here.

[0105] Based on the same principle, this embodiment also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0106] The processor and / or the memory include a multi-bit magnetic storage unit as described in this embodiment.

[0107] The multi-bit magnetic storage unit described in the above embodiments can be specifically installed in a product device with a certain function. A typical implementation device is a computer device, specifically, such as a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0108] In a typical example, a computer device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor and / or the memory includes multi-bit magnetic storage units as described in this embodiment.

[0109] The following is for reference. Figure 17 It shows a schematic diagram of the structure of a computer device suitable for implementing the embodiments of this application.

[0110] like Figure 17 As shown, the computer device includes a central processing unit (CPU) 601, which can perform various appropriate tasks and processes based on programs stored in read-only memory (ROM) 602 or programs loaded from storage section 608 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for system operation. CPU 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0111] The following components are connected to I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal feedback (LCD), etc., and speakers, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on drive 610 as needed so that computer programs read from it can be installed in storage section 608 as needed.

[0112] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0113] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0114] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0115] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0116] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can be applied as a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0117] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0118] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0119] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method of fabricating a multi-bit magnetic memory cell, comprising: comprising: forming a spin orbit torque layer; forming at least one magnetic tunnel junction and at least one magnetic body on the spin orbit torque layer, the magnetic tunnel junction for storing data, the magnetic body for providing leakage magnetic field to the magnetic tunnel junction such that the asymmetry of the magnetic tunnel junction is enhanced.

2. The method of claim 1, wherein further comprising: forming a protective medium layer on the at least one magnetic tunnel junction and the at least one magnetic body.

3. The method of claim 1, wherein the method further comprising: punching through the magnetic body.

4. The method of claim 1 or 3, wherein the magnetic body comprising a first ferromagnetic layer, a second ferromagnetic layer, an insulating layer and a third ferromagnetic layer arranged in order from top to bottom, the third ferromagnetic layer formed on the spin orbit torque layer; the method further comprising: etching away at least one of the first ferromagnetic layer, the second ferromagnetic layer, the insulating layer and the third ferromagnetic layer of the magnetic body to form a first hollow region; depositing a magnetic material or a protective medium in the first hollow region.

5. The method of claim 1 or 3, wherein the method further comprising: etching away the magnetic body to form a second hollow region; depositing a magnetic material in the second hollow region.

6. The method of claim 1, wherein the number of the magnetic tunnel junctions and the magnetic bodies is multiple; wherein one or more of the magnetic tunnel junctions and one or more of the magnetic bodies are arranged apart along the direction of spin orbit torque current input to the spin orbit torque layer.

7. The method of claim 6, wherein one or two of the magnetic tunnel junctions and one or two of the magnetic bodies are arranged apart along the direction of spin orbit torque current input to the spin orbit torque layer.

8. The method of claim 1, wherein: further comprising: arranging a first electrode on top of the magnetic tunnel junction; arranging a second electrode on top of at least one of the magnetic bodies.

9. The method of claim 1, wherein further comprising: connecting the second electrode of the magnetic body with the second electrode to a data writing module, the data writing module for determining a writing current path of the corresponding magnetic tunnel junction according to the data to be written, and writing spin orbit torque current through the second electrode or the current input end of the spin orbit torque layer on the writing current path to write the data to be written into the corresponding magnetic tunnel junction.

10. A multi-bit magnetic memory cell, comprising: obtained by the method of any one of claims 1-9.

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