A method for manufacturing a semiconductor light emitting device, a DFB epitaxial wafer and a DFB laser

Abstract

This application provides a method for fabricating a semiconductor light-emitting device, a DFB epitaxial wafer, and a DFB laser. The fabrication method includes: providing a substrate; sequentially forming a buffer layer, a grating layer, and a waveguide stack layer on the substrate; etching the waveguide stack layer along the stacking direction to form a docking interface on opposite sides of the waveguide stack layer, wherein the docking interfaces on both sides of the waveguide stack layer are mirror-symmetrical; and epitaxially forming a waveguide material layer at the docking interface. In the semiconductor light-emitting device fabrication method provided in this application, by forming a docking interface on opposite sides of the waveguide stack layer and then epitaxially forming a waveguide material layer at the docking interface, the COD threshold of the semiconductor light-emitting device is improved, thereby improving the reliability of the semiconductor light-emitting device.

Description

Technical Field

[0001] This application relates to the field of semiconductor light-emitting device technology, and in particular to a method for fabricating a semiconductor light-emitting device, a DFB epitaxial wafer, and a DFB laser. Background Technology

[0002] High-speed, high-reliability, and low-cost semiconductor light-emitting devices are core components of modern high-speed optical networks. Compared to the indium gallium arsenide phosphide / indium phosphide InGaAsP / InP material system, the aluminum gallium indium arsenide / indium phosphide AlGaInAs / InP material system has a larger conduction band offset. Therefore, semiconductor light-emitting devices fabricated using the AlGaInAs / InP material system exhibit better electron confinement and hole allocation performance.

[0003] Catastrophic optical damage (COD) is a failure mode in high-power lasers. Under high power density operation, the cavity surface temperature rises rapidly, causing bandgap contraction in the material at the light output location. This leads to increased light absorption, resulting in a dramatic temperature increase, which in turn further increases light absorption. This vicious cycle continues, eventually causing the cavity surface region to melt and recrystallize. The affected cavity surface region will generate a large number of lattice defects, thereby reducing the reliability of semiconductor light-emitting devices.

[0004] Therefore, improving the reliability of semiconductor light-emitting devices is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] In view of this, the present application provides a method for fabricating a semiconductor light-emitting device, a DFB epitaxial wafer, and a DFB laser to solve at least one technical problem existing in the prior art.

[0006] To achieve the above objectives, the technical solution of this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor light-emitting device, the method comprising:

[0008] Provide substrate;

[0009] A buffer layer, a grating layer, and a waveguide stack layer are sequentially formed on the substrate;

[0010] The waveguide stack layer is etched along the stacking direction to form a mating interface on opposite sides of the waveguide stack layer, and the mating interfaces on both sides of the waveguide stack layer are mirror symmetrical.

[0011] A waveguide material layer is epitaxially formed at the docking interface.

[0012] In some embodiments of this application, the docking interface is at a first tilt angle to the substrate.

[0013] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; the active layer includes a first waveguide layer, a quantum well layer, and a second waveguide layer disposed along the stacking direction; the quantum well layer is made of AlGaInAs material; the etching of the waveguide stack layer along the stacking direction to form a mating interface on opposite sides of the waveguide stack layer includes:

[0014] The waveguide stack is etched along the stacking direction, and the etching stops at the N-type waveguide layer in the waveguide stack.

[0015] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially includes a first P-type confinement layer, a second P-type confinement layer, a first P-type sacrificial layer, and a first P-type cap layer along the stacking direction; the step of epitaxially forming a waveguide material layer at the mating interface includes:

[0016] A waveguide material layer is formed at the docking interface, and the upper surface of the waveguide material layer is flush with the upper surface of the first P-type confinement layer.

[0017] In some embodiments of this application, the waveguide stack layer sequentially comprises an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially comprises a first P-type confinement layer, a second P-type confinement layer, a first P-type sacrificial layer, and a first P-type cap layer along the stacking direction; after the waveguide material layer is epitaxially formed at the docking interface, the fabrication method further includes:

[0018] A third P-type confinement layer, a second P-type sacrificial layer, and a second P-type cap layer are sequentially formed on the waveguide material layer; wherein...

[0019] The upper surface of the third P-type confinement layer is flush with the upper surface of the second P-type confinement layer;

[0020] The upper surface of the second P-type sacrificial layer is flush with the upper surface of the first P-type sacrificial layer;

[0021] The upper surface of the second P-type cap layer is flush with the upper surface of the first P-type cap layer.

[0022] In some embodiments of this application, the first P-type cap layer and the second P-type cap layer are removed; the first P-type sacrificial layer and the second P-type sacrificial layer are removed.

[0023] In some embodiments of this application, the preparation method further includes:

[0024] A top epitaxial structure is formed on the second P-type confinement layer and the third P-type confinement layer to form a distributed feedback laser (DFB) epitaxial wafer. The top epitaxial structure includes a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer, and a doped contact layer.

[0025] In some embodiments of this application, the preparation method further includes:

[0026] A ridge waveguide fabrication process is used to etch the top epitaxial structure to form a DFB laser; wherein...

[0027] The DFB laser is cleaved into multiple strip laser tubes, with the cleaving direction parallel to the docking interface; wherein...

[0028] The light emission direction of the single tube of the strip laser is basically parallel to the ridge extension direction of the DFB laser.

[0029] Secondly, embodiments of this application provide a DFB epitaxial wafer, the DFB epitaxial wafer comprising:

[0030] Substrate; forming a buffer layer, a grating layer, and a waveguide stack layer stacked on the substrate;

[0031] Waveguide material layers are formed on opposite sides of the waveguide stack layer, and the waveguide stack layer and the waveguide material layers are connected through the docking interface; the docking interfaces on both sides of the waveguide stack layer are mirror symmetrical.

[0032] A top epitaxial structure is formed on the waveguide stack layer and the waveguide material layer, the top epitaxial structure including a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer and a doped contact layer.

[0033] In some embodiments of this application, the docking interface is at a first tilt angle to the substrate.

[0034] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; the active layer includes a first waveguide layer, a quantum well layer, and a second waveguide layer disposed along the stacking direction; the quantum well layer is made of aluminum gallium indium arsenide (AlGaInAs); the waveguide material layers formed on opposite sides of the waveguide stack layer, wherein the waveguide stack layer and the waveguide material layers are connected through the mating interface, include:

[0035] The lowest point of the docking interface is located in the N-type waveguide layer.

[0036] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially includes a first P-type confinement layer and a second P-type confinement layer along the stacking direction; the upper surface of the waveguide material layer is flush with the upper surface of the first P-type confinement layer.

[0037] In some embodiments of this application, the waveguide stack layer sequentially comprises an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially comprises a first P-type confinement layer and a second P-type confinement layer along the stacking direction; the DFB epitaxial wafer further comprises:

[0038] A third P-type confinement layer is formed on the waveguide material layer; wherein...

[0039] The upper surface of the third P-type confinement layer is flush with the upper surface of the second P-type confinement layer.

[0040] Thirdly, embodiments of this application provide a DFB laser, which is fabricated from a DFB epitaxial wafer as described in the above technical solutions using a ridge waveguide forming process.

[0041] Fourthly, embodiments of this application provide a single strip laser tube, which is obtained by cleaving a DFB laser as described in the above technical solution, with the cleaving direction parallel to the docking interface; wherein,

[0042] The light emission direction of the single tube of the strip laser is basically parallel to the ridge extension direction of the DFB laser.

[0043] This application provides a method for fabricating a semiconductor light-emitting device, a DFB epitaxial wafer, and a DFB laser. The fabrication method includes: providing a substrate; sequentially forming a buffer layer, a grating layer, and a waveguide stack layer on the substrate; etching the waveguide stack layer along the stacking direction to form a docking interface on opposite sides of the waveguide stack layer, wherein the docking interfaces on both sides of the waveguide stack layer are mirror-symmetrical; and epitaxially forming a waveguide material layer at the docking interface. In the semiconductor light-emitting device fabrication method provided in this application, by forming a docking interface on opposite sides of the waveguide stack layer and then epitaxially forming a waveguide material layer at the docking interface, the COD threshold of the semiconductor light-emitting device is improved, thereby improving the reliability of the semiconductor light-emitting device. Attached Figure Description

[0044] Figure 1 A three-dimensional structural schematic diagram of a semiconductor light-emitting device provided in an embodiment of this application;

[0045] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor light-emitting device;

[0046] Figure 3 A schematic cross-sectional view of a semiconductor light-emitting device after forming a mask layer, provided in an embodiment of this application;

[0047] Figure 4 A schematic cross-sectional view of a semiconductor light-emitting device after a patterned mask layer has been formed, provided as an embodiment of this application;

[0048] Figure 5 A three-dimensional structural schematic diagram of a semiconductor light-emitting device after forming a docking interface, provided for an embodiment of this application;

[0049] Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor light-emitting device;

[0050] Figure 7 for Figure 5 A top view of a semiconductor light-emitting device;

[0051] Figure 8 A schematic diagram of the three-dimensional structure of a semiconductor light-emitting device after forming a docking interface, provided as an embodiment of this application;

[0052] Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of a semiconductor light-emitting device;

[0053] Figure 10 for Figure 8 A top view of a semiconductor light-emitting device;

[0054] Figure 11 A schematic cross-sectional view of the semiconductor light-emitting device after the waveguide material layer has been formed, as provided in an embodiment of this application.

[0055] Figure 12 A schematic cross-sectional view of the semiconductor light-emitting device after removing the patterned mask layer, provided in an embodiment of this application;

[0056] Figure 13 A schematic cross-sectional view of the semiconductor light-emitting device after removing the first P-type capping layer, the second P-type capping layer, the first P-type sacrificial layer, and the second P-type sacrificial layer, as provided in the embodiments of this application.

[0057] Figure 14 A three-dimensional structural schematic diagram of the DFB epitaxial wafer provided in the embodiments of this application;

[0058] Figure 15 for Figure 14 A schematic diagram of the cross-sectional structure of a DFB epitaxial wafer;

[0059] Figure 16This is a three-dimensional structural diagram of a DFB laser provided in an embodiment of this application;

[0060] Figure 17 for Figure 16 Top view of a DFB laser in China;

[0061] Figure 18 for Figure 16 Side view of a DFB laser;

[0062] Figure 19 A flowchart illustrating a method for fabricating a semiconductor light-emitting device as provided in an embodiment of this application;

[0063] The figure includes: 100-substrate; 101-buffer layer; 102-grating layer; 103-grating protection layer; 104-first N-type confinement layer; 105-first N-type material layer; 106-second N-type confinement layer; 107-first waveguide layer; 108-quantum well layer; 109-second waveguide layer; 110-first P-type confinement layer; 111-second P-type confinement layer; 112-first P-type sacrificial layer; 113-first P-type cap layer; 114-mask layer; 1141, 1 142 - Patterned mask layer; 115 - Waveguide material layer; 116 - Third P-type confinement layer; 117 - Second P-type sacrificial layer; 118 - Second P-type cap layer; 119 - Fourth P-type confinement layer; 120 - P-type anti-corrosion layer; 121 - Fifth P-type confinement layer; 122 - Doped contact layer; 20 - N-type waveguide layer; 30 - Active layer; 40 - P-type waveguide layer; 50 - Top epitaxial structure; 60 - Ridge; β1, β2 - First tilt angle; θ - Second tilt angle. Detailed Implementation

[0064] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0065] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0066] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0067] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0068] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0069] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0070] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0071] refer to Figure 19 , Figure 19 A flowchart illustrating a method for fabricating a semiconductor light-emitting device according to an embodiment of this application. Figure 19 As shown in the figure, this application provides a method for fabricating a semiconductor light-emitting device, the method comprising:

[0072] Step S1901: Provide a substrate;

[0073] Step S1902: A buffer layer, a grating layer, and a waveguide stack layer are sequentially formed on the substrate;

[0074] Step S1903: Etch the waveguide stacked layer along the stacking direction to form a docking interface on opposite sides of the waveguide stacked layer, and the docking interfaces on both sides of the waveguide stacked layer are mirror symmetrical.

[0075] Step S1904: An epitaxial waveguide material layer is formed at the docking interface.

[0076] refer to Figure 1 and Figure 2 , Figure 1 This is a three-dimensional structural schematic diagram of the semiconductor light-emitting device provided in the embodiments of this application. Figure 2 for Figure 1 A schematic cross-sectional view of a semiconductor light-emitting device. (e.g.) Figure 1 and Figure 2 As shown, a buffer layer 101, a grating layer 102, a grating protection layer 103, and a waveguide stack layer are sequentially formed on a substrate 100. The waveguide stack layer includes an N-type waveguide layer 20, an active layer 30, and a P-type waveguide layer 40. The N-type waveguide layer 20, along the stacking direction, sequentially includes a first N-type confinement layer 104, a first N-type material layer 105, and a second N-type confinement layer 106. The active layer 30, along the stacking direction, sequentially includes a first waveguide layer 107, a quantum well layer 108, and a second waveguide layer 109. The P-type waveguide layer 40, along the stacking direction, sequentially includes a first P-type confinement layer 110, a second P-type confinement layer 111, a first P-type sacrificial layer 112, and a first P-type capping layer 113.

[0077] In some embodiments of this application, the substrate material may include, but is not limited to, indium phosphide (InP). This application does not impose any special limitations on the shape and size of the substrate; for example, the substrate may be circular, square, or other shapes.

[0078] In some embodiments of this application, metal-organic chemical vapor deposition (MOCVD) technology can be used to perform epitaxial growth on an MOCVD machine.

[0079] Specifically, organic compounds of Group III and II elements and hydrides of Group V and VI elements are used as crystal growth source materials. Vapor phase epitaxy is performed on a substrate via thermal decomposition reactions to grow thin single-crystal materials of various Group III-V and II-VI compound semiconductors and their multi-component solid solutions. Typically, in MOCVD equipment, crystal growth is carried out in a hydrogen-filled reaction chamber under normal or low pressure, with a substrate temperature of 500°C to 1200°C. A graphite substrate located below the substrate is heated by direct current, and hydrogen gas carrying the metal-organic compound is bubbled through a temperature-controlled liquid source to the growth region.

[0080] In some embodiments of this application, the growth temperature field of the buffer layer, grating layer, grating protection layer, and waveguide stack layer can be a uniform temperature field, meaning that the temperature of each epitaxial layer structure is consistent during growth, resulting in a structural layer with uniform thickness; the growth temperature field can also be a non-uniform temperature field, meaning that the temperature of each epitaxial layer structure is inconsistent during growth, resulting in an epitaxial structural layer with non-uniform thickness. Therefore, this application does not limit the temperature field for forming each epitaxial layer structure in a semiconductor light-emitting device. Furthermore, other insertion layers can be provided between the epitaxial layer structures of the buffer layer, grating layer, and grating protection layer, or within the waveguide stack layer, according to actual production needs, and are not limited to the aforementioned epitaxial structural layers.

[0081] In some embodiments of this application, the material of the buffer layer may include, but is not limited to, indium phosphide (InP) of type N. Providing a buffer layer between the grating layer and the substrate can reduce the defect density in the grating layer, thereby improving the crystal quality of the semiconductor light-emitting device.

[0082] In some embodiments of this application, the material of the grating layer may include, but is not limited to, N-type indium gallium arsenide phosphide (InGaAsP). In some embodiments of this application, the material of the grating protective layer may include, but is not limited to, N-type indium gallium arsenide phosphide (InGaAsP).

[0083] Specifically, a substrate is placed in an MOCVD apparatus, and a buffer layer, a grating layer, and a grating protection layer are sequentially epitaxially grown on the surface of the substrate. A mask layer is formed on the surface of the grating protection layer away from the grating layer. The material of the mask layer is not limited. In some preferred embodiments of this application, the mask layer includes a first mask layer and a second mask layer. Using two mask layers can improve accuracy and ensure a more precise structure obtained through etching the mask layers. The materials of the first mask layer and the second mask layer can be the same or different. In some preferred embodiments of this application, the material of the first mask layer may include amorphous carbon, and the material of the second mask layer may include silicon dioxide.

[0084] Furthermore, a pattern can be formed on the mask layer (i.e., including a first mask layer and a second mask layer) using holographic lithography (i.e., interference lithography) or electron-beam lithography (EBL). This pattern exposes a portion of the grating protective layer and covers the remainder of the grating protective layer. The grating protective layer and the grating layer are then etched using dry etching or wet etching methods to form a grating.

[0085] Furthermore, the semiconductor structure forming the grating can be placed in an MOCVD device for epitaxial growth until the resulting buried grating layer completely covers the grating. Here, the buried grating layer can be grown at 550°C, allowing for slow growth at low temperatures and resulting in a relatively smooth growth interface.

[0086] In some embodiments of this application, the N-type waveguide layer may sequentially include a first N-type confinement layer, a first N-type material layer, and a second N-type confinement layer along the stacking direction. The material of the first N-type confinement layer may include, but is not limited to, N-type indium phosphide (InP). The first N-type material layer may be an N-type quaternary graded layer; for example, the material of the first N-type material layer may include, but is not limited to, N-type aluminum gallium indium arsenide (AlGaInAs). The material of the second N-type confinement layer may include, but is not limited to, N-type aluminum indium arsenide (AlInAs).

[0087] The first N-type material layer can be an N-type aluminum gallium indium arsenide (AlGaInAs) gradient layer, that is, the composition of aluminum, gallium and indium varies gradually.

[0088] In some embodiments of this application, the active layer includes a first waveguide layer, a quantum well layer, and a second waveguide layer disposed along the stacking direction. The materials of the first waveguide layer and the second waveguide layer may include, but are not limited to, aluminum gallium indium arsenide (AlGaInAs). The material of the quantum well layer may include, but is not limited to, aluminum gallium indium arsenide (AlGaInAs).

[0089] The first waveguide layer can be an AlGaInAs composition gradient layer, and the second waveguide layer can also be an AlGaInAs composition gradient layer, wherein the composition content of aluminum, gallium and indium in the first waveguide layer and the second waveguide layer is gradually changed.

[0090] In some embodiments of this application, the quantum well layer may include a multiple quantum well (MQW) layer. The MQW layer is a superlattice structure, which may include multiple quantum well layers and multiple quantum barrier layers, with the quantum well layers and quantum barrier layers growing alternately. Here, the MQW layer primarily serves to confine charge carriers. Charge carriers may include electrons in the N-type waveguide layer and holes in the P-type waveguide layer. When a positive current passes through, the electrons in the N-type waveguide layer and the holes in the P-type waveguide layer are confined within the active layer, recombine, and emit light.

[0091] In some embodiments of this application, the number of cycles of the multiple quantum well layer can be 5 to 20, but the number of cycles of the multiple quantum well layer is not limited to this and can be set according to actual needs.

[0092] In some embodiments of this application, the thicknesses of the quantum barrier layers in the multi-quantum-well layer may be equal or unequal. Here, the thickness of the quantum barrier layers may affect the migration of electrons and holes and the crystal quality. For example, while increasing the thickness of the quantum barrier layers can improve crystal quality, it also increases the blocking effect on electrons and holes, resulting in insufficient electrons and holes to recombine and emit light in the quantum well layers, thereby reducing the luminous efficiency of the semiconductor light-emitting device. Conversely, decreasing the thickness of the quantum barrier layers leads to poor crystal quality; therefore, it is necessary to optimize the thickness range of the quantum barrier layers.

[0093] In some embodiments of this application, the P-type waveguide layer may sequentially include a first P-type confinement layer, a second P-type confinement layer, a first P-type sacrificial layer, and a first P-type cap layer along the stacking direction. The material of the first P-type confinement layer may include, but is not limited to, P-type aluminum indium arsenide (AlInAs). The material of the second P-type confinement layer may include, but is not limited to, P-type indium phosphide (InP). The material of the first P-type sacrificial layer may include, but is not limited to, P-type indium gallium arsenide phosphide (InGaAsP). The material of the first P-type cap layer may include, but is not limited to, P-type indium phosphide (InP).

[0094] The thicknesses of the first P-type confinement layer, the second P-type confinement layer, the first P-type sacrificial layer, and the first P-type capping layer are not limited and can be set according to actual needs. For example, the thickness of the second P-type confinement layer can be 30 nm, the thickness of the first P-type sacrificial layer can be 15 nm, and the thickness of the first P-type capping layer can be 30 nm.

[0095] refer to Figure 3 , Figure 3 This is a schematic cross-sectional view of a semiconductor light-emitting device after forming a mask layer, provided as an embodiment of this application. Figure 3 As shown, a mask layer 114 is formed on the waveguide stack layer of the semiconductor light-emitting device. The mask layer material may include, but is not limited to, silicon dioxide, silicon nitride, or combinations thereof. The thickness and number of mask layers can be set according to actual needs.

[0096] refer to Figure 4 , Figure 4 This is a schematic cross-sectional view of a semiconductor light-emitting device after a patterned mask layer has been formed, as provided in an embodiment of this application. Figure 4 As shown, the mask layer is etched to form a patterned mask layer 1141. Here, inductively coupled plasma (ICP) can be used to etch the mask layer to form specific tilt angles on opposite sides of the mask layer.

[0097] refer to Figure 5 , Figure 6 and Figure 7 , Figure 5 This is a three-dimensional structural diagram of a semiconductor light-emitting device after forming a docking interface, provided in an embodiment of this application. Figure 6 for Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor light-emitting device. Figure 7 for Figure 5 A top view of a semiconductor light-emitting device. (e.g.) Figure 5 and Figure 6 As shown, a patterned mask layer 1141 is used to etch the waveguide stack layer to form mating interfaces on opposite sides of the waveguide stack layer, and the mating interfaces on both sides of the waveguide stack layer are mirror-symmetrical. Here, wet etching, dry etching, or a combination thereof can be used to etch the waveguide stack layer to form the mating interfaces.

[0098] This is still a reference. Figure 7 The mirror symmetry of the docking interfaces on both sides of the waveguide stack layer means that the docking interfaces on both sides of the waveguide stack layer are symmetrical, the symmetry plane is perpendicular to the substrate, and the symmetry plane is located in the middle of the two docking interfaces on both sides of the waveguide stack layer. Figure 7The AA' shown is the orthogonal projection of this plane of symmetry onto the substrate.

[0099] Figure 6 The mating interface shown is inclined at a first angle β1 to the substrate 100. Here, the first angle β1 is an acute angle, that is, the mating interfaces on opposite sides of the waveguide stack layer appear as a trapezoid, wider at the top and narrower at the bottom, in the cross-sectional structural schematic diagram. In some preferred embodiments of this application, the first angle β1 ranges from 5° to 30°.

[0100] refer to Figure 8 , Figure 9 and Figure 10 , Figure 8 This is a schematic diagram of another three-dimensional structure of a semiconductor light-emitting device after forming a docking interface, provided as an embodiment of this application. Figure 9 for Figure 8 A schematic diagram of the cross-sectional structure of a semiconductor light-emitting device. Figure 10 for Figure 8 A top view of a semiconductor light-emitting device. (e.g.) Figure 8 and Figure 9 As shown, a patterned mask layer 1142 is used to etch the waveguide stack layer to form mating interfaces on opposite sides of the waveguide stack layer, and the mating interfaces on both sides of the waveguide stack layer are mirror-symmetrical. Here, wet etching, dry etching, or a combination thereof can be used to etch the waveguide stack layer to form the mating interfaces.

[0101] This is still a reference. Figure 10 The mirror symmetry of the docking interfaces on both sides of the waveguide stack layer means that the docking interfaces on both sides of the waveguide stack layer are symmetrical, the symmetry plane is perpendicular to the substrate, and the symmetry plane is located in the middle of the two docking interfaces on both sides of the waveguide stack layer. Figure 10 The BB' shown is the orthogonal projection of this symmetry plane onto the substrate.

[0102] Figure 9 The mating interface shown is inclined at a first angle β2 to the substrate 100. Here, the first angle β2 is an obtuse angle, that is, the mating interfaces on opposite sides of the waveguide stack layer appear as a trapezoid, narrower at the top and wider at the bottom, in the cross-sectional structural schematic diagram. In some preferred embodiments of this application, the first angle β2 ranges from 95° to 120°.

[0103] In some embodiments of this application, etching the waveguide stack layer along the stacking direction to form a mating interface on opposite sides of the waveguide stack layer includes:

[0104] The waveguide stack is etched along the stacking direction, and the etching stops at the N-type waveguide layer in the waveguide stack.

[0105] like Figure 6 and Figure 9 As shown, the waveguide stack layer is etched along the stacking direction, and the etching stops at the N-type waveguide layer in the waveguide stack layer. More specifically, the etching stops at the first N-type confinement layer in the N-type waveguide layer.

[0106] refer to Figure 11 , Figure 11 This is a schematic cross-sectional view of a semiconductor light-emitting device after forming a waveguide material layer, as provided in an embodiment of this application. Figure 11 As shown, a waveguide material layer 115 is formed at the docking interface, and the upper surface of the waveguide material layer 115 is flush with the upper surface of the first P-type confinement layer 110. Figure 11 The diagram only shows the case where the docking interface forms an acute angle with the substrate. The following description of the fabrication method of the semiconductor light-emitting device is based on the case where the docking interface forms an acute angle with the substrate, and does not constitute a limitation on the scope of protection of this application.

[0107] In some embodiments of this application, the waveguide material layer may be made of, but is not limited to, indium gallium arsenide phosphide (InGaAsP). Here, the wavelength of the waveguide material layer is shorter than the emission wavelength of the quantum well layer.

[0108] Still referencing Figure 11 A third P-type confinement layer 116, a second P-type sacrificial layer 117, and a second P-type cap layer 118 are sequentially formed on the waveguide material layer 115. The upper surface of the third P-type confinement layer 116 is flush with the upper surface of the second P-type confinement layer 111; the upper surface of the second P-type sacrificial layer 117 is flush with the upper surface of the first P-type sacrificial layer 112; and the upper surface of the second P-type cap layer 118 is flush with the upper surface of the first P-type cap layer 113. Here, the third P-type confinement layer, the second P-type sacrificial layer, and the second P-type cap layer are also in direct contact with the mating interface.

[0109] The thicknesses of the third P-type confinement layer, the second P-type sacrificial layer, and the second P-type capping layer are not limited and can be set according to actual needs. For example, the thickness of the third P-type confinement layer can be 30 nm, the thickness of the second P-type sacrificial layer can be 15 nm, and the thickness of the second P-type capping layer can be 30 nm.

[0110] In the method for fabricating a semiconductor light-emitting device provided in this application embodiment, after forming a docking interface on opposite sides of the waveguide stack layer, a waveguide material layer is epitaxially formed at the docking interface to improve the COD threshold of the semiconductor light-emitting device, thereby improving the reliability of the semiconductor light-emitting device.

[0111] More specifically, in the method for fabricating a semiconductor light-emitting device provided in this application embodiment, the waveguide stacking layer of the semiconductor light-emitting device includes an N-type waveguide layer, an active layer, and a P-type waveguide layer. The active layer can be made of an aluminum-based material, such as aluminum gallium indium arsenide (AlGaInAs). A matching wide-bandgap, oxygen-insensitive semiconductor material, such as indium gallium arsenide phosphide (InGaAsP), is grown using a material butt welding growth method to improve the COD threshold of the aluminum-based semiconductor light-emitting device, thereby improving the reliability of the aluminum-based semiconductor light-emitting device.

[0112] In some embodiments of this application, the material of the third P-type confinement layer is the same as the material of the second P-type confinement layer; and / or

[0113] The material of the second P-type sacrificial layer is the same as the material of the first P-type sacrificial layer; and / or

[0114] The material of the second P-type cap layer is the same as that of the first P-type cap layer.

[0115] Here, the material of the third P-type confinement layer can be the same as the material of the second P-type confinement layer, and the material of the third P-type confinement layer can include, but is not limited to, indium p-type indium phosphide (InP). The material of the second P-type sacrificial layer is the same as the material of the first P-type sacrificial layer, and the material of the second P-type sacrificial layer can include, but is not limited to, indium p-type gallium arsenide phosphide (InGaAsP). The material of the second P-type capping layer is the same as the material of the first P-type capping layer, and the material of the second P-type capping layer can include, but is not limited to, indium p-type indium phosphide (InP).

[0116] refer to Figure 12 , Figure 12 This is a schematic cross-sectional view of the semiconductor light-emitting device after removing the patterned mask layer, as provided in an embodiment of this application. Figure 12 As shown, the mask layer located on top of the semiconductor light-emitting device is removed.

[0117] refer to Figure 13 , Figure 13 This is a schematic cross-sectional view of the semiconductor light-emitting device after removing the first P-type capping layer, the second P-type capping layer, the first P-type sacrificial layer, and the second P-type sacrificial layer, as provided in an embodiment of this application. Figure 13 As shown, the first P-type cap layer and the second P-type cap layer are removed; the first P-type sacrificial layer and the second P-type sacrificial layer are removed.

[0118] Here, a wet etching method can be used to remove the first P-type cap layer, the second P-type cap layer, the first P-type sacrificial layer, and the second P-type sacrificial layer. If the materials of the first P-type cap layer and the second P-type cap layer are the same, the same etching solution can be used to remove them; similarly, if the materials of the first P-type sacrificial layer and the second P-type sacrificial layer are the same, the same etching solution can be used to remove them. Therefore, the etching process for removing the first P-type cap layer, the second P-type cap layer, the first P-type sacrificial layer, and the second P-type sacrificial layer is simpler and less costly.

[0119] In some embodiments of this application, the preparation method further includes:

[0120] A top epitaxial structure is formed on the second P-type confinement layer and the third P-type confinement layer to form a distributed feedback laser (DFB) epitaxial wafer. The top epitaxial structure includes a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer, and a doped contact layer.

[0121] refer to Figure 14 and Figure 15 , Figure 14 This is a three-dimensional structural diagram of the DFB epitaxial wafer provided in an embodiment of this application. Figure 15 for Figure 14 A schematic diagram of the cross-sectional structure of a DFB epitaxial wafer. (See attached diagram.) Figure 15 As shown, a top epitaxial structure 50 is epitaxially formed on the second P-type confinement layer 111 and the third P-type confinement layer 116 to form a distributed feedback laser (DFB) epitaxial wafer. The top epitaxial structure 50 includes a fourth P-type confinement layer 119, a P-type anti-corrosion layer 120, a fifth P-type confinement layer 121, and a doped contact layer 122.

[0122] In some embodiments of this application, the material of the fourth P-type confinement layer may include, but is not limited to, indium p-type indium phosphide (InP). The material of the P-type anti-corrosion layer may include, but is not limited to, indium gallium arsenide phosphide (InGaAsP). The material of the fifth P-type confinement layer may include, but is not limited to, indium p-type indium phosphide (InP). The material of the doped contact layer may include, but is not limited to, indium gallium arsenide (InGaAs).

[0123] The thicknesses of the fourth P-type confinement layer, the P-type anti-corrosion layer, the fifth P-type confinement layer, and the doped contact layer are not specifically limited and can be set according to actual needs. For example, the thickness range of the fourth P-type confinement layer can be 50 nm to 100 nm, the thickness range of the P-type anti-corrosion layer can be 20 nm to 40 nm, the thickness range of the fifth P-type confinement layer can be 50 nm to 100 nm, and the thickness range of the doped contact layer can be 20 nm to 40 nm.

[0124] In some embodiments of this application, the doping element in the doped contact layer may include, but is not limited to, Zn, with a doping concentration of approximately 1*10⁻⁶. 19 cm -3 .

[0125] In some embodiments of this application, the preparation method further includes:

[0126] A ridge waveguide fabrication process is used to etch the top epitaxial structure to form a DFB laser; wherein...

[0127] The DFB laser is cleaved into multiple strip laser tubes, with the cleaving direction parallel to the docking interface; wherein...

[0128] The light emission direction of the single tube of the strip laser is basically parallel to the ridge extension direction of the DFB laser.

[0129] refer to Figure 16 , Figure 17 and Figure 18 , Figure 16 This is a three-dimensional structural diagram of the DFB laser provided in the embodiments of this application. Figure 17 for Figure 16 Top view of a DFB laser. Figure 18 for Figure 16 Side view of a DFB laser. Figure 16 As shown, a mask layer (not shown in the figure) can be formed on the doped contact layer, and the top epitaxial structure can be etched using the patterned mask layer to form the ridge 60. The etching stops at the P-type resist layer.

[0130] Figure 16 One of the two end faces of the ridge 60 shown along the ridge extension direction is the light-emitting end face, which can be as follows: Figure 18 As shown. Here Figure 18 The light-emitting end face of the ridge 60 shown is a trapezoid that is wider at the top and narrower at the bottom. In this application, the shape of the light-emitting end face of the ridge is not specifically limited. The shape of the light-emitting end face of the ridge may include, but is not limited to, a rectangle or a trapezoid, etc.

[0131] As previously mentioned, the DFB laser is cleaved into multiple strip laser tubes, with the cleaving direction parallel to the docking interface. (See reference here.) Figure 16 and Figure 17 The waveguide stack is etched to form mating interfaces on opposite sides of the waveguide stack, and the mating interfaces on both sides of the waveguide stack are about an axis of symmetry (e.g., Figure 17 As shown, the waveguide stack exhibits mirror symmetry, with the axis of symmetry located precisely at the midpoint of the mating interface between the opposite sides of the waveguide stack. In this case, the DFB laser can be considered as being cleaved along this axis of symmetry, thus cleaving it into two strip-shaped laser tubes.

[0132] Here, the ridge extension direction of the DFB laser is substantially parallel to the emission direction of the single strip laser tube. "Substantially parallel" means that the ridge extension direction of the DFB laser is parallel to the emission direction of the single strip laser tube, or that the ridge extension direction of the DFB laser forms a certain angle with the emission direction of the single strip laser tube. In other words, the ridge extension direction of the DFB laser is substantially parallel to the normal direction of the emission end face of the single strip laser tube. More specifically, such as... Figure 17 As shown, the ridge 60 of the DFB laser extends at a second tilt angle θ to the light output direction of the single strip laser tube. For example, the second tilt angle θ can range from 2° to 10°. In other words, the ridge 60 of the DFB laser extends at a second tilt angle θ to the normal direction of the light output end face of the single strip laser tube. For example, the second tilt angle θ can range from 2° to 10°.

[0133] In some embodiments of this application, after the DFB laser is cleaved into multiple strip laser tubes, an optical thin film can be deposited on the end face of the strip laser tube.

[0134] This application embodiment also provides a DFB epitaxial wafer, the DFB epitaxial wafer comprising:

[0135] Substrate; forming a buffer layer, a grating layer, and a waveguide stack layer stacked on the substrate;

[0136] Waveguide material layers are formed on opposite sides of the waveguide stack layer, and the waveguide stack layer and the waveguide material layers are connected through the docking interface; the docking interfaces on both sides of the waveguide stack layer are mirror symmetrical.

[0137] A top epitaxial structure is formed on the waveguide stack layer and the waveguide material layer, the top epitaxial structure including a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer and a doped contact layer.

[0138] like Figure 14As shown, the DFB epitaxial wafer includes: a substrate 100; a buffer layer 101, a grating layer 102, a grating protection layer 103, and a waveguide stack layer formed on the substrate 100; waveguide material layers 115 formed on opposite sides of the waveguide stack layer, the waveguide stack layer and the waveguide material layer 115 being connected through the docking interface; the docking interfaces on both sides of the waveguide stack layer are mirror symmetrical; and a top epitaxial structure 50 formed on the waveguide stack layer and the waveguide material layer 115, the top epitaxial structure 50 including a fourth P-type confinement layer 119, a P-type anti-corrosion layer 120, a fifth P-type confinement layer 121, and a doped contact layer 122.

[0139] In some embodiments of this application, the docking interface is at a first tilt angle to the substrate.

[0140] In some embodiments of this application, the first tilt angle ranges from 5° to 30° or from 95° to 120°.

[0141] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; the waveguide material layers formed on opposite sides of the waveguide stack layer, wherein the waveguide stack layer and the waveguide material layers are connected through the mating interface, include:

[0142] The lowest point of the docking interface is located in the N-type waveguide layer.

[0143] Specifically, the waveguide stack and the waveguide material layer are connected via the interface, wherein the lowest point of the interface is located in the N-type waveguide layer. In other words, the etching of the waveguide stack stops at the N-type waveguide layer.

[0144] In some embodiments of this application, the active layer includes a first waveguide layer, a quantum well layer, and a second waveguide layer disposed along the stacking direction; the quantum well layer is made of aluminum gallium indium arsenide (AlGaInAs).

[0145] In some embodiments of this application, the waveguide stack layer sequentially includes an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially includes a first P-type confinement layer and a second P-type confinement layer along the stacking direction; the upper surface of the waveguide material layer is flush with the upper surface of the first P-type confinement layer.

[0146] In some embodiments of this application, the waveguide stack layer sequentially comprises an N-type waveguide layer, an active layer, and a P-type waveguide layer along the stacking direction; wherein, the P-type waveguide layer sequentially comprises a first P-type confinement layer and a second P-type confinement layer along the stacking direction; the DFB epitaxial wafer further comprises:

[0147] A third P-type confinement layer is formed on the waveguide material layer; wherein...

[0148] The upper surface of the third P-type confinement layer is flush with the upper surface of the second P-type confinement layer.

[0149] In some embodiments of this application, the material of the third P-type confinement layer is the same as the material of the second P-type confinement layer.

[0150] In some embodiments of this application, the waveguide material layer is made of indium gallium arsenide phosphide (InGaAsP); and / or

[0151] The grating layer is made of indium gallium arsenide phosphide (InGaAsP).

[0152] This application also provides a DFB laser, which is fabricated from a DFB epitaxial wafer as described in the above technical solution using a ridge waveguide forming process.

[0153] This application embodiment also provides a strip laser single tube, which is obtained by cleaving the DFB laser described in the above technical solution, with the cleaving direction parallel to the docking interface; wherein...

[0154] The light emission direction of the single tube of the strip laser is basically parallel to the ridge extension direction of the DFB laser.

[0155] This application provides a method for fabricating a semiconductor light-emitting device, a DFB epitaxial wafer, and a DFB laser. The fabrication method includes: providing a substrate; sequentially forming a buffer layer, a grating layer, and a waveguide stack layer on the substrate; etching the waveguide stack layer along the stacking direction to form a docking interface on opposite sides of the waveguide stack layer, wherein the docking interfaces on both sides of the waveguide stack layer are mirror-symmetrical; and epitaxially forming a waveguide material layer at the docking interface. In the semiconductor light-emitting device fabrication method provided in this application, by forming a docking interface on opposite sides of the waveguide stack layer and then epitaxially forming a waveguide material layer at the docking interface, the COD threshold of the semiconductor light-emitting device is improved, thereby improving the reliability of the semiconductor light-emitting device.

[0156] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0157] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A method for fabricating a semiconductor light-emitting device, characterized in that, The preparation method includes: Provide substrate; A buffer layer, a grating layer, and a waveguide stack layer are sequentially formed on the substrate; The waveguide stack is etched along the stacking direction to form a docking interface on opposite sides of the waveguide stack, and the docking interfaces on both sides of the waveguide stack are mirror symmetrical; the docking interface is at a first tilt angle to the substrate. A waveguide material layer is formed epitaxially at the docking interface.

2. The preparation method according to claim 1, characterized in that, The waveguide stack layer comprises, in sequence along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; the active layer comprises, along the stacking direction, a first waveguide layer, a quantum well layer, and a second waveguide layer; the quantum well layer is made of aluminum gallium indium arsenide (AlGaInAs). The etching of the waveguide stack layer along the stacking direction to form a mating interface on opposite sides of the waveguide stack layer includes: The waveguide stack is etched along the stacking direction, and the etching stops at the N-type waveguide layer in the waveguide stack.

3. The production method according to claim 1, wherein The waveguide stack layer comprises, along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; wherein, the P-type waveguide layer comprises, along the stacking direction, a first P-type confinement layer, a second P-type confinement layer, a first P-type sacrificial layer, and a first P-type cap layer; the waveguide material layer epitaxially formed at the mating interface comprises: A waveguide material layer is formed at the docking interface, and the upper surface of the waveguide material layer is flush with the upper surface of the first P-type confinement layer.

4. The production method according to claim 1, wherein The waveguide stack layer comprises, along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; wherein, the P-type waveguide layer comprises, along the stacking direction, a first P-type confinement layer, a second P-type confinement layer, a first P-type sacrificial layer, and a first P-type cap layer; after the waveguide material layer is epitaxially formed at the docking interface, the fabrication method further includes: A third P-type confinement layer, a second P-type sacrificial layer, and a second P-type cap layer are sequentially formed on the waveguide material layer; wherein... The upper surface of the third P-type confinement layer is flush with the upper surface of the second P-type confinement layer; The upper surface of the second P-type sacrificial layer is flush with the upper surface of the first P-type sacrificial layer; The upper surface of the second P-type cap layer is flush with the upper surface of the first P-type cap layer.

5. The preparation method according to claim 4, characterized in that, Remove the first P-type cap layer and the second P-type cap layer; Remove the first P-type sacrificial layer and the second P-type sacrificial layer.

6. The production method according to claim 5, wherein The preparation method further includes: A top epitaxial structure is formed on the second P-type confinement layer and the third P-type confinement layer to form a distributed feedback laser (DFB) epitaxial wafer. The top epitaxial structure includes a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer, and a doped contact layer.

7. The production method according to claim 6, wherein The preparation method further includes: A ridge waveguide fabrication process is used to etch the top epitaxial structure to form a DFB laser; wherein... The DFB laser is cleaved into multiple strip laser tubes, with the cleaving direction parallel to the docking interface; wherein... The light emission direction of the single tube of the bar laser is parallel to the ridge extension direction of the DFB laser; or, the light emission direction of the single tube of the bar laser forms a second tilt angle with the ridge extension direction of the DFB laser.

8. A DFB epitaxial wafer, characterized by, The DFB epitaxial wafer includes: Substrate; forming a buffer layer, a grating layer, and a waveguide stack layer stacked on the substrate; Waveguide material layers are formed on opposite sides of the waveguide stack layer, and the waveguide stack layer and the waveguide material layers are connected through a docking interface; the docking interfaces on both sides of the waveguide stack layer are mirror symmetrical; the docking interface is at a first tilt angle to the substrate; A top epitaxial structure is formed on the waveguide stack layer and the waveguide material layer, the top epitaxial structure including a fourth P-type confinement layer, a P-type anti-corrosion layer, a fifth P-type confinement layer and a doped contact layer.

9. The DFB epiwafer of claim 8 wherein, The waveguide stack layer comprises, in sequence along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; the active layer comprises, along the stacking direction, a first waveguide layer, a quantum well layer, and a second waveguide layer; the quantum well layer is made of aluminum gallium indium arsenide (AlGaInAs). The waveguide material layers formed on opposite sides of the waveguide stack layer, wherein the waveguide stack layer and the waveguide material layers are connected through the mating interface, include: The lowest point of the docking interface is located in the N-type waveguide layer.

10. The DFB epitaxial wafer as described in claim 8, characterized in that, The waveguide stack layer includes, in sequence along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; wherein, the P-type waveguide layer includes, in sequence along the stacking direction, a first P-type confinement layer and a second P-type confinement layer; the upper surface of the waveguide material layer is flush with the upper surface of the first P-type confinement layer.

11. The DFB epiwafer of claim 8 wherein, The waveguide stack layer comprises, along the stacking direction, an N-type waveguide layer, an active layer, and a P-type waveguide layer; wherein, the P-type waveguide layer comprises, along the stacking direction, a first P-type confinement layer and a second P-type confinement layer; the DFB epitaxial wafer further comprises: A third P-type confinement layer is formed on the waveguide material layer; wherein... The upper surface of the third P-type confinement layer is flush with the upper surface of the second P-type confinement layer.

12. A DFB laser, characterized by, The DFB laser is fabricated from a DFB epitaxial wafer as described in any one of claims 8 to 11 using a ridge waveguide forming process.

13. A bar laser single tube, characterized by The strip laser tube is obtained by cleaving the DFB laser of claim 12, with the cleaving direction parallel to the docking interface; wherein... The light emission direction of the single tube of the bar laser is parallel to the ridge extension direction of the DFB laser; or, the light emission direction of the single tube of the bar laser forms a second tilt angle with the ridge extension direction of the DFB laser.

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