Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a substrate, a display area, a first peripheral area located on one side of the display area, the first peripheral area including a ramp area, the distance between the ramp area and the substrate being a first distance at one end close to the display area, and a second distance at the other end away from the display area, the first distance being smaller than the second distance; the display area including a plurality of display units; a power line including an extension part extending away from the display area, the extension part intersecting the ramp area, the power line being electrically connected to the display units. An encapsulation layer is arranged on the side of the power line away from the substrate. A metal protection structure is arranged on the side of the encapsulation layer away from the substrate, and the orthographic projection of the metal protection structure on the substrate covers at least one edge of the extension part intersecting a first direction, the first direction being the extension direction of the edge of the display area close to the side of the first peripheral area.

Description

Technical Field

[0001] This article relates to, but is not limited to, display technology, particularly a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, and extremely fast response speed. With the continuous development of display technology, display devices using OLEDs as light-emitting elements and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field.

[0003] The inventors of this application have discovered through research that the bottom bezel of the display product has a problem of continuously expanding dark spots (GDS). Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a display substrate and its preparation method, as well as a display device, to solve the problem of GDS (Geodes Descent) on the bottom bezel of display products.

[0006] On one hand, this disclosure provides a display substrate, including a substrate, a display area, and a first peripheral area located on one side of the display area. The first peripheral area includes a ramp area, the ramp area being a first distance from the substrate near the display area and a second distance from the substrate away from the display area, the first distance being less than the second distance. The display area includes a plurality of display units. A power line includes an extension extending in a direction away from the display area, the extension intersecting the ramp area, and the power line being electrically connected to the display units. An encapsulation layer is disposed on the side of the power line away from the substrate. A metal protective structure is disposed on the side of the encapsulation layer away from the substrate, and the orthographic projection of the metal protective structure on the substrate covers at least one edge of the extension intersecting the first direction, the first direction being an extension direction parallel to the edge of the display area near the first peripheral area.

[0007] In one exemplary embodiment, the first peripheral area further includes a bending area located on the side of the climbing area away from the display area.

[0008] In one exemplary embodiment, the first peripheral area further includes an isolation dam located on the side of the climbing area closer to the display area.

[0009] In one exemplary embodiment, in the first direction, the edge of the extension is serrated, and the orthographic projection of the metal protective structure on the substrate covers the orthographic projection of the serrated shape on the substrate.

[0010] In one exemplary embodiment, the power cord includes a first power cord and a second power cord, wherein in the first peripheral area, the second power cord is disposed on both sides of the first power cord along a first direction.

[0011] In one exemplary embodiment, the metal protection structure includes a first metal protection structure and a second metal protection structure. The orthographic projection of the first metal protection structure on the substrate covers at least one edge where the extension of the first power line intersects with the first direction. The orthographic projection of the second metal protection structure on the substrate covers at least one edge where the extension of the second power line intersects with the first direction.

[0012] In one exemplary embodiment, the orthographic projection of the first metal protective structure on the substrate covers the edge of the extension of the first power line near the side of the extension of the second power line; the orthographic projection of the second metal protective structure on the substrate covers the edge of the extension of the second power line near the side of the extension of the first power line.

[0013] In one exemplary embodiment, in a plane direction perpendicular to the display substrate, the display substrate includes the substrate, a driving structure layer disposed on the substrate, a first planarization layer disposed on the driving structure layer, a metal conductive layer disposed on the first planarization layer, a second planarization layer disposed on the metal conductive layer, and a light-emitting element disposed on the second planarization layer; the light-emitting element is connected to the driving structure layer through the metal conductive layer; the driving structure layer includes a source / drain metal layer, and at least one of the first power line and the second power line is disposed in the same layer as the metal conductive layer or the source / drain metal layer.

[0014] In one exemplary embodiment, in a plane direction perpendicular to the display substrate, the display substrate further includes a touch layer disposed on the side of the encapsulation layer away from the substrate. The touch layer includes multiple metal film layers, and the metal protective structure is disposed in the same layer as any one of the multiple metal film layers.

[0015] In one exemplary embodiment, the touch layer includes a first touch metal layer, a first touch insulating layer, a second touch metal layer, and a touch protective layer, wherein the metal protective structure is disposed in the same layer as the first touch metal layer.

[0016] In one exemplary embodiment, on the side of the isolation dam closest to the display area, the first power line is connected to the high-voltage power line of the display area, and the second power line is connected to the low-voltage power line of the display area.

[0017] In one exemplary embodiment, the isolation dam includes a first isolation dam and a second isolation dam, the second isolation dam being located on the side of the first isolation dam away from the display area; the climbing area is located on the side of the second isolation dam away from the display area.

[0018] In one exemplary embodiment, the substrate further includes a second peripheral region located on the periphery of the display area and away from the ramp area, wherein the first peripheral region and the second peripheral region are connected and surround the display area; within the second peripheral region, the second power line is configured to surround the display area.

[0019] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: providing a substrate, the substrate including a display area and a first peripheral area located on one side of the display area, the first peripheral area including a ramp area, the ramp area being a first distance from the substrate near the display area and a second distance from the substrate away from the display area, the first distance being less than the second distance; forming a power line in the first peripheral area, the power line being electrically connected to a display unit of the display area; the power line including an extension extending in a direction away from the display area, the extension intersecting the ramp area; forming an encapsulation layer on the side of the power line away from the substrate; forming a metal protection structure on the side of the encapsulation layer away from the substrate, the orthographic projection of the metal protection structure on the substrate covering at least one edge of the extension intersecting the first direction, the first direction being an extension direction parallel to the edge of the display area near the first peripheral area.

[0020] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0021] The display substrate provided in this embodiment provides a metal protection structure on the side of the encapsulation layer away from the substrate, and the orthogonal projection of the metal protection structure on the substrate covers at least one edge where the extension of the power line intersects with the first direction. This allows the metal protection structure to protect the ramp area of ​​the display substrate. Even if other film layers on the side of the power line away from the substrate break in the ramp area, the metal protection structure can prevent water and oxygen intrusion, thus solving the problem of GDS on the bottom bezel of the display product.

[0022] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0025] Figure 1 This is a schematic diagram of the structure of a display substrate;

[0026] Figure 2 This is a schematic diagram of the planar structure of a display area in a display substrate;

[0027] Figure 3 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0028] Figure 4 This is a schematic diagram illustrating a GDSX malfunction occurring on the bottom bezel of a display device.

[0029] Figure 5 These are schematic diagrams of the structure of display substrates in some technologies;

[0030] Figure 6 This is a schematic diagram of the edge shape of the extension of the power line at the dashed box c in an exemplary embodiment;

[0031] Figure 7 for Figure 5 Sectional view at point AA;

[0032] Figure 8 This is a schematic diagram of the structure of the display substrate provided in the embodiments of this disclosure;

[0033] Figure 9 In an exemplary embodiment Figure 8A top view of the power line and metal protective structure at area e;

[0034] Figure 10 In an exemplary embodiment Figure 8 A cross-sectional view at BB;

[0035] Figure 11 In an exemplary embodiment Figure 10 A magnified view of region f. Detailed Implementation

[0036] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0037] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0038] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0039] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0040] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0041] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0042] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0043] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0044] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0045] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic diagram of the structure of a display substrate. Figure 1 As shown, the display substrate may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, scan driver, and light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, data signal lines, and light-emitting signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED signal lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0047] Figure 2This is a schematic diagram of a planar structure of a display area in a display substrate. For example... Figure 2 As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit in each sub-pixel is connected to the pixel driving circuit of its respective sub-pixel, and the light-emitting unit is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0048] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0049] In an exemplary embodiment, a pixel unit may include four sub-pixels. For example, the four sub-pixels may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel that emits white (W) light. Alternatively, the four sub-pixels may include a red sub-pixel, a blue sub-pixel, and two green sub-pixels. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontally parallel, vertically parallel, square, or diamond shape, etc., and this disclosure does not limit the arrangement.

[0050] Figure 3 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 3 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit is connected to 6 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission signal line E, initial signal line INIT and first power supply line VDD).

[0051] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0052] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0053] The gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first terminal of the first transistor T1 is connected to the initial signal line INIT, and the second terminal of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initial voltage to the gate electrode of the third transistor T3 to initialize the charge on the gate electrode of the third transistor T3.

[0054] The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the second node N2, and the second terminal of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to its second terminal.

[0055] The gate electrode of the third transistor T3 is connected to the second node N2, meaning the gate electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first terminal of the third transistor T3 is connected to the first node N1, and the second terminal of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The amount of driving current flowing between the first power line VDD and the second power line VSS is determined by the potential difference between its gate electrode and its first terminal.

[0056] The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0057] The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the first terminal of the light-emitting unit EL. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting unit EL to emit light.

[0058] The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting unit EL. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initial voltage to the first electrode of the light-emitting unit EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting unit EL.

[0059] In an exemplary embodiment, the light-emitting unit EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0060] In an exemplary embodiment, the second electrode of the light-emitting unit EL is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0061] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0062] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0063] The following example illustrates the operation of a pixel driving circuit, where all seven transistors are P-type transistors:

[0064] In the first stage, A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting signal line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1 and the seventh transistor T7. The turn on of the first transistor T1 provides the initial voltage of the initial signal line INIT to the second node N2, initializing the storage capacitor C and clearing the existing data voltage within it. The turn on of the seventh transistor T7 provides the initial voltage of the initial signal line INIT to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing its internal pre-stored voltage, and completing the initialization. The high signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6; during this stage, the OLED does not emit light.

[0065] The second stage, A2, is called the data writing stage or threshold compensation stage. In this stage, the signal on the first scan signal line S1 is low, while the signals on the second scan signal line S2 and the light emission signal line E are high. The data signal line D outputs a data voltage. During this stage, because the second terminal of the storage capacitor C is low, the third transistor T3 is turned on. The low signal on the first scan signal line S1 turns on the second transistor T2 and the fourth transistor T4. The turning on of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The high signal on the second scan signal line S2 turns off the first transistor T1 and the seventh transistor T7. The signal on the light-emitting signal line E is a high-level signal, which disconnects the fifth transistor T5 and the sixth transistor T6.

[0066] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting signal line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. Because a voltage Vd-|Vth| was written to the second terminal of the storage capacitor C in the previous stage, the third transistor T3 remains on in this stage. The power supply voltage output from the first power line VDD provides a driving voltage to the first electrode of the OLED through the on-state fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0067] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0068] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0069] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0070] A display device includes: a driving circuit layer disposed on a substrate, a light-emitting element disposed on the driving circuit layer, and an encapsulation layer disposed on the light-emitting element, the encapsulation layer being used to protect the light-emitting element. Research shows that the encapsulation effect of the encapsulation layer has a significant impact on the display performance of the display device. If the encapsulation layer fails, such as by creating a gap or breaking, moisture in the atmosphere can enter the light-emitting element along the gap, causing the organic materials in the light-emitting element to oxidize and fail, forming a failure area that cannot emit light. As moisture continues to invade the light-emitting element along the gap, the failure area gradually expands, leading to display defects in the display device, known as Growing Dark Spot (GDS). A GDS occurring at a fixed position on the bottom bezel of the display device is called a GDSX defect.

[0071] Figure 4 This is a diagram illustrating a GDSX malfunction occurring on the bottom bezel of a display device. Figure 4 As shown, dashed boxes a and b indicate the locations where the display device experiences GDSX malfunctions. These locations have noticeable dark spots when the screen is displayed, affecting the screen display effect and user experience.

[0072] Figure 5 This is a schematic diagram of the structure of a display substrate in some technologies. For example... Figure 5As shown, the display substrate provided in this embodiment includes a display area 100 and a non-display area surrounding the display area 100. The non-display area includes a bonding area 400 located on one side of the display area 100, a first peripheral area 200 located between the display area 100 and the bonding area 400, and a second peripheral area 300 located outside the display area 100 and away from the bonding area 400. The first peripheral area 200 and the second peripheral area 300 are connected and surround the display area 100. The display area 100 includes at least a plurality of display units. In some examples, a pixel includes three display units, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel includes four display units, for example, a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The first peripheral area 200 includes at least an isolation dam and power lines for transmitting voltage signals to the plurality of display units. The bonding area 400 includes circuitry for connecting the signal lines of the plurality of display units to an external driving device. The second peripheral region 300 includes at least an isolation dam and power lines for transmitting voltage signals to multiple display units. The isolation dams of the first peripheral region 200 and the second peripheral region 300 can form a ring structure surrounding the display region 100. The bonding region 400 includes multiple bonding pads configured to bond to external flexible printed circuit boards (FPCs) or chip-on-flex (COF) films.

[0073] like Figure 5 As shown, the power lines may include a first power line 210 and a second power line 220. The first power line 210 is connected to the high-voltage power line of the display area 100 and is configured to transmit high-voltage signals to a plurality of display units of the display area 100. The second power line 220 is connected to the low-voltage power line of the second peripheral area 300 and is configured to transmit low-voltage signals to a plurality of display units of the display area 100.

[0074] like Figure 5 As shown, the power line of the first peripheral region 200 may include a main body Z and an extension S. The extension direction of the main body Z may be approximately the same as the first direction X, and the extension direction of the extension S may intersect the first direction X. The extension S can connect the main body Z to the pads corresponding to the bonding region 400. Figure 5 As shown, the first direction X is an extension direction parallel to the edge of the display area 100 near the first peripheral area 200. That is, the first direction X is an extension direction parallel to the edge 110 of the display area, and the second direction Y can be set to intersect with the first direction X. The plane containing the first direction X and the second direction Y can be the plane containing the display substrate. Figure 5 As shown, the first power line 210 may include a main body Z1 and two extensions S1, and the second power line 220 may include a main body Z2 and two extensions S2.

[0075] Figure 6 for Figure 5 A schematic diagram of the edge shape of the power line extension at point c (within the dashed box). Figure 5 and Figure 6 As shown, within the first peripheral region 200, the extension S1 of the first power line 210 and the extension S2 of the second power line 220 can extend in a direction away from the display area 100. In this first direction, the edges of the extension S1 of the first power line 210 and the extension S2 of the second power line 220 can be configured as follows: Figure 6 The serrated shape shown can increase the intrusion path of moisture into the display area 100 by setting the edges of the extensions of the first power line 210 and the second power line 220 into a serrated shape. Figure 6 The diagram illustrates the sawtooth shape of the opposing edges of the extension S1 of the first power line 210 and the extension S2 of the second power line 220. In an exemplary embodiment, the opposite edges of the first power line 210 and the second power line 220 are also set in a sawtooth shape. That is, in the first direction, the edges of the extension S1 of the first power line 210 and the extension S2 of the second power line 220 are both set in a sawtooth shape. In other embodiments, the edges of the extension S1 of the first power line 210 and the extension S2 of the second power line 220 can be set in other shapes of sawtooth patterns, such as circles, ellipses, triangles, quadrilaterals, other polygonal shapes, or irregular shapes, etc., and this disclosure does not limit this.

[0076] Figure 7 for Figure 5 The cross-sectional view at point AA shows a portion of the film structure of the display substrate. (Example) Figure 7 As shown, in a plane perpendicular to the display substrate, the display substrate may include a substrate 10, a driving structure layer disposed on the substrate 10, a first planarization layer 15 disposed on the driving structure layer, a metal conductive layer disposed on the first planarization layer 15, a second planarization layer 17 disposed on the metal conductive layer, a light-emitting element disposed on the second planarization layer 17, and a composite layer 99 covering the light-emitting element. The driving structure layer of the display area may include a transistor structure. Figure 7The diagram shows the film structure of the non-display area. The driving structure layer of the non-display area may include multiple inorganic insulating layers and a metal layer 98. The metal layer 98 may be disposed on the same layer as the source / drain metal layer of the display area. The metal layer 98 may be, for example, a data signal line, and this disclosure is not limited thereto. The metal conductive layer of the display area may include, for example, a connecting electrode for connecting the anode of the light-emitting element and the drain electrode of the corresponding transistor. The metal conductive layer of the non-display area may include, for example, a power structure layer 212, which may include a first power line 210 and a second power line 220. The non-display area may not include a light-emitting element. The pixel definition layer 22 of the non-display area may be disposed on the same layer as the pixel definition layer 22 located in the display area. The pixel definition layer 22 of the non-display area may serve as part of the base of the first isolation dam 410 and the second isolation dam 420. In some embodiments, the source / drain metal layer is referred to as the first source / drain metal layer (SD1), and the metal conductive layer is referred to as the second source / drain metal layer (SD2).

[0077] In an exemplary embodiment, a first isolation dam 410 and a second isolation dam 420 are disposed in a first peripheral region 200 and a second peripheral region 300, forming a ring structure surrounding the display region 100. The first isolation dam 410 and the second isolation dam 420 are configured to block moisture entering the display region 100 from its periphery. In the first peripheral region 200, the first isolation dam 410 and the second isolation dam 420 can extend along a first direction. The distance between the first isolation dam 410 and the edge 110 of the display region is less than the distance between the second isolation dam 420 and the edge 110 of the display region; that is, the second isolation dam 420 is disposed on the side of the first isolation dam 410 away from the display region 100. The first isolation dam 410 and the second isolation dam 420 are disposed on the first power line 210 and the second power line 220 and are wrapped by a composite layer 99.

[0078] In an exemplary embodiment, the first power line 210 and the second power line 220 may be disposed in a metal conductive layer. In other embodiments, the first power line 210 and the second power line 220 may be disposed in a source / drain metal layer, or may be disposed in other film layers of the drive structure layer. The first power line 210 and the second power line 220 may be disposed in the same layer or in different layers, and this disclosure does not limit this.

[0079] In an exemplary embodiment, the composite layer 99 may include an encapsulation layer and may also include a touch layer disposed on the side of the encapsulation layer away from the substrate 10, which is not limited in this disclosure.

[0080] like Figure 7As shown, on the side of the second isolation dam 420 away from the display area 100, the display substrate includes a ramp region d. The distance between the ramp region d and the substrate 10 at the end near the display area is a first distance h1, and the distance between the ramp region d and the substrate 10 at the end away from the display area is a second distance h2. Figure 7 As can be seen, the first distance h1 is smaller than the second distance h2, indicating a stepped height difference in the display substrate at the ramp region d. This stepped structure includes upper and lower steps, with the upper steps located on the side of the lower steps furthest from the display area 100. In subsequent fabrication processes, optical adhesive can be applied to the lower steps to facilitate the attachment of the polarizer. Setting the ramp region d facilitates the subsequent attachment of the polarizer to the display substrate.

[0081] The inventors of this application have discovered through research that GDSX defects in display substrates are generally caused by the fracture of the second planarization layer 17 and the composite layer 99 at the ramp region d, leading to moisture intrusion into the display area 100. Further research revealed that, on the one hand, the ramp region contains films such as the first planarization layer 15 and the second planarization layer 17, resulting in a larger height difference and a larger slope angle for the films at the ramp location, making the second planarization layer 17 and the composite layer 99 prone to fracture. On the other hand, because the ramp region is located at the edge of the polarizer, it bears significant compressive stress from the polarizer, making the second planarization layer 17 and the composite layer 99 prone to fracture. Furthermore, because the ramp region overlaps with the extension of the power line, the stress on the second planarization layer 17 and the composite layer 99 is uneven, especially when the edge of the extension is serrated. This uneven stress is exacerbated, making the second planarization layer 17 and the composite layer 99 prone to fracture at the ramp region during subsequent module reliability testing, resulting in GDSX defects.

[0082] This disclosure provides a display substrate, comprising: a substrate including a display area and a first peripheral area located on one side of the display area; the first peripheral area including a ramp area; the ramp area being at a first distance from the substrate near the display area and at a second distance away from the substrate away from the display area, the first distance being less than the second distance; the display area including a plurality of display units; a power line including an extension extending in a direction away from the display area, the extension intersecting the ramp area, and the power line being electrically connected to the display units; an encapsulation layer disposed on the side of the power line away from the substrate; and a metal protective structure disposed on the side of the encapsulation layer away from the substrate, wherein the orthographic projection of the metal protective structure on the substrate covers at least one edge where the extension intersects the first direction, the first direction being an extension direction parallel to the edge of the display area near the first peripheral area.

[0083] The display substrate provided in this embodiment provides a metal protection structure on the side of the encapsulation layer away from the substrate, and the orthogonal projection of the metal protection structure on the substrate covers at least one edge where the extension of the power line intersects with the first direction. This allows the metal protection structure to protect the ramp area of ​​the display substrate. Even if other film layers on the side of the power line away from the substrate break in the ramp area, the metal protection structure can prevent water and oxygen intrusion, thus solving the GDSX problem of the display substrate.

[0084] Figure 8 This is a schematic diagram of the structure of the display substrate provided in the embodiments of this disclosure. Figure 8 Display substrate and Figure 5 The difference between the display substrates is that Figure 8 The display substrate includes a metal protective structure 34, a main body Z of the power line, and an extension S, among other structures and areas, which can be referenced in the following text. Figure 5 The description of [the subject] will not be repeated here. For example... Figure 8 As shown, the substrate includes a display area 100 and a first peripheral area 200 located on one side of the display area 100. The first peripheral area 200 includes a ramp area 600. The distance between the ramp area 600 and the substrate at the end near the display area 100 is a first distance, and the distance between the ramp area 600 and the substrate at the end away from the display area 100 is a second distance. The first distance is less than the second distance. An isolation dam 411 is located in the first peripheral area 200, and the ramp area 600 is located on the side of the isolation dam 411 away from the display area 100. The power line includes an extension S extending in a direction away from the display area 100, and the extension S intersects with the ramp area 600. The power line 421 is electrically connected to the display unit of the display area 100. An encapsulation layer 55 is provided on the side of the power line 421 away from the substrate. The metal protective structure 34 is disposed on the side of the encapsulation layer 55 away from the substrate, and the orthographic projection of the metal protective structure 34 on the substrate covers at least one edge of the extension that intersects with the first direction X, wherein the first direction X is the extension direction parallel to the edge of the display area 100 near the first peripheral area 200.

[0085] like Figure 8 As shown, the power cord 421 includes a first power cord 210 and a second power cord 220. Within the first peripheral region 200, the second power cord 220 is disposed on both sides of the first power cord 210 along a first direction.

[0086] like Figure 8As shown, the second peripheral region 300 includes at least an isolation dam 411 and a power line 421 for transmitting voltage signals to a plurality of display units. The isolation dam 411 of the first peripheral region 200 and the second peripheral region 300 can form a ring structure surrounding the display region 100. The second power line 220 within the second peripheral region 300 can be configured to surround the display region 100. The isolation dam 411 can include a first isolation dam 410 and a second isolation dam 420, and the second isolation dam 420 can be located on the side of the first isolation dam 410 away from the display region 100. Within the second peripheral region 300, the orthographic projection of the first isolation dam 410 on the substrate can overlap with the orthographic projection of the second power line 220 on the substrate, and the orthographic projection of the second isolation dam 420 on the substrate can surround the orthographic projection of the second power line 220 on the substrate; this disclosure does not impose any limitations in this regard.

[0087] like Figure 8 As shown, within the first peripheral region 200, the power cord 421 also includes a main body Z, which is connected to the extension S, and the main body Z is located on the side of the extension S closer to the display area 100. The main body Z can extend along a first direction X, and the extension S can extend along a second direction Y.

[0088] like Figure 8 As shown, the first peripheral region 200 also includes a bending region 500, which is located on the side of the ramp region 600 away from the display region 100. The bending region 500 includes a composite insulating layer with grooves, configured to bend the bonding region 400 to the back of the display region 100. The power line 421 passes through the bending region 500 and enters the bonding region 400, where it connects to the corresponding bonding pad.

[0089] like Figure 8 As shown, the metal protection structure 34 may include a first metal protection structure 341 and a second metal protection structure 342. The orthographic projection of the first metal protection structure 341 on the substrate covers at least one edge where the extension S1 of the first power line 210 intersects with the first direction. The orthographic projection of the second metal protection structure 342 on the substrate covers at least one edge where the extension S2 of the second power line 220 intersects with the first direction. On the side of the first isolation dam 410 near the display area 100, the first power line 210 can be connected to the high-voltage power line (VDD) of the display area 100 via a fan-out routing method, and the second power line 220 can be connected to the low-voltage power line (VSS) of the display area 100 via a fan-out routing method.

[0090] Figure 9 In an exemplary implementation Figure 8 A top view of the power line and metal protective structure at area e. Figure 9As shown, the metal protection structure 34 may only cover the serrated shape of the edge of the extension S of the power line 421, or the overlapping area of ​​the orthographic projection of the metal protection structure 34 on the substrate 10 and the orthographic projection of the extension S on the substrate 10 may be set as needed. This disclosure does not limit this. Figure 8 and Figure 9 The illustration shows a case where metal protective structures are provided at the opposite side edges of the extensions of the first power line 210 and the second power line 220. According to practical research, the probability of the relevant inorganic film layer breaking at this location and causing GDSX malfunction is relatively high. Providing a metal protective structure 34 at this location can provide effective protection and save costs. In practical applications, metal protective structures 34 can be provided on both sides of the extension S along the first direction to form more comprehensive protection. Alternatively, the number and location of the metal protective structures 34 can be provided as needed; this disclosure does not impose any limitations on this.

[0091] like Figure 9 As shown, in the first direction, the edge of the extension S of the power line 421 can be serrated, and the orthographic projection of the metal protection structure 34 on the substrate covers this serrated shape. In the first direction, the serrated shape can be located at the edge of the extension S between the second isolation dam 420 and the bending area 500.

[0092] Figure 10 In an exemplary embodiment Figure 8 A cross-sectional view at point BB. (See example) Figure 10 As shown, in a plane direction perpendicular to the display substrate, the display area 100 includes: a substrate 10, a driving structure layer 51 disposed on the substrate 10, a first planarization layer 15 disposed on the driving structure layer 51, a metal conductive layer 52 disposed on the first planarization layer 15, a second planarization layer 17 disposed on the metal conductive layer 52, a light-emitting element 54 disposed on the second planarization layer 17, an encapsulation layer 55 covering the light-emitting element 54, and a touch layer 53. The driving structure layer 51 of the display area 100 includes a plurality of transistors and a storage capacitor forming a pixel driving circuit. Figure 10The illustration uses a first transistor 101 and a first storage capacitor 102 as an example. The first transistor 101 can be a driving transistor. The driving structure layer of the display area 100 may include: a first insulating layer 11 disposed on the substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, a first gate metal layer disposed on the second insulating layer 12, a third insulating layer 13 covering the first gate metal layer, a second gate metal layer disposed on the third insulating layer 13, a fourth insulating layer 14 covering the second gate metal layer, and a source / drain metal layer 56 disposed on the fourth insulating layer 14. The active layer may include at least a first active layer, the first gate metal layer may include at least a first gate electrode and a first capacitor electrode, the second gate metal layer may include at least a second capacitor electrode, and the source / drain metal layer 56 may include at least a first source electrode and a first drain electrode. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 101, and the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102. The metal conductive layer 52 of the display area 100 includes at least a connection electrode 19. The connecting electrode 19 is connected to the first drain electrode of the first transistor 101 through a via formed in the first planarization layer 15. The light-emitting element 54 of the display area 100 includes an anode 21, a pixel definition layer 22, an organic light-emitting layer 23, and a cathode 24. The anode 21 is connected to the connecting electrode 19 through a via formed in the second planarization layer 17, thus realizing the connection between the anode 21 and the first drain electrode of the first transistor 101. The encapsulation layer 55 of the display area 100 includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 stacked together, with the second encapsulation layer 26, made of organic material, disposed between the first encapsulation layer 25 and the third encapsulation layer 27, made of inorganic material. The touch layer 53 of the display area 100 includes a first touch metal layer 28, a first touch insulating layer 29, a second touch metal layer 30, and a touch protective layer 31. The first touch metal layer 28 may include multiple connecting bridges, and the second touch metal layer 30 may include multiple driving electrodes and sensing electrodes. The driving electrodes or sensing electrodes can be connected to the bridging electrodes through openings on the first touch insulating layer 29.

[0093] like Figure 10As shown, the metal conductive layer 52 of the first peripheral region 200 includes at least a power structure layer 212. The power structure layer 212 is disposed on the fourth insulating layer 14 and the first planarization layer 15, and can be disposed in the same layer as the metal conductive layer 52 of the display region 100, and formed by the same patterning process. The power structure layer 212 includes a first power line 210 and a second power line 220. In other embodiments, the display substrate may not have a metal conductive layer 52, and the anode 21 may be directly connected to the first drain electrode of the first transistor 101. In this case, the first power line 210 and the second power line 220 may be disposed in the same layer as the source and drain metal layers 56, or the positions of the first power line 210 and the second power line 220 may be set as needed. This disclosure does not limit this.

[0094] like Figure 8 and Figure 10 As shown, one end of the metal protective structure 34 can be located near the second isolation dam 420, and the other end of the metal protective structure 34 can be located near the bending area 500. Since the serrated shape of the edge of the extension is generally distributed between the second isolation dam 420 and the bending area 500, Figure 10 The metal protective structure 34 can cover the climbing area 600 and provide good protection for the edge of the extension. In other embodiments, the metal protective structure 34 can cover the second isolation dam 420, or the metal protective structure 34 can cover the first isolation dam 410 and the second isolation dam 420. The coverage area of ​​the metal protective structure 34 can be specifically set as needed, and this disclosure does not limit it.

[0095] like Figure 10 As shown, the touch layer 53 may include multiple metal film layers, and the metal protective structure 34 may be disposed in the same layer as at least one metal film layer of the touch layer 53. For example, the metal protective structure 34 may be disposed in the same layer as the first touch metal layer 28, and this disclosure does not limit this.

[0096] The first power line 210, the second power line 220, and the metal protection structure 34 can adopt a multi-layer composite structure of Ti / Al / Ti. The aluminum in the middle layer has high activity and is easily corroded by water-based liquids, but the titanium layers on both sides can effectively block water and oxygen. Figure 11 In an exemplary embodiment Figure 10 A magnified view of region f. For example... Figure 11As shown, due to the large step difference at the ramp area 600, the first touch insulating layer 29, touch protective layer 31, first encapsulation layer 25, and third encapsulation layer 27 located on the side away from the substrate are prone to breakage, leading to water and oxygen intrusion. However, by providing a metal protection structure 34 to cover the ramp area 600, even if the first touch insulating layer 29 and touch protective layer 31 break, water and oxygen will not further intrude due to the blockage of the metal protection structure 34. Even if the first encapsulation layer 25 and third encapsulation layer 27 also break, the metal protection structure 34 can effectively block water and oxygen, preventing water and oxygen from contacting the power structure layer 212, thereby forming good water and oxygen protection, reducing the risk of GDSX, avoiding display defects on the display substrate, and improving display quality.

[0097] like Figure 10 As shown, a pixel definition layer 22 is disposed on the second planarization layer 17 adjacent to the display area 100, and a plurality of spacer pillars 33 are disposed on the pixel definition layer 22. The cathode 24 surrounds the plurality of spacer pillars 33. In other embodiments, the display substrate may not be provided with spacer pillars 33, and this disclosure does not limit this.

[0098] like Figure 10 As shown, the foundation of the first isolation dam 410 and the foundation of the second isolation dam 420 may include a second flattening layer 17 and a pixel definition layer 22. In other embodiments, the foundation of the first isolation dam 410 and the foundation of the second isolation dam 420 may also include diaphragm columns 33. The foundations of the first isolation dam 410 and the second isolation dam 420 may be set as needed, and this disclosure does not impose any limitations on this.

[0099] The structure of the display substrate according to embodiments of this disclosure is illustrated below through an example of the fabrication process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process.

[0100] To prepare Figure 10Taking the display substrate shown as an example, the fabrication process of the display substrate in this embodiment includes the following steps:

[0101] (1) A substrate 10 is prepared on a glass carrier.

[0102] In an exemplary embodiment, the substrate 10 can be a flexible substrate, such as including a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The first and second flexible material layers are made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers are made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen; these first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer is made of amorphous silicon (a-Si). In some exemplary embodiments, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the fabrication process includes: firstly, coating a layer of polyimide on a glass substrate 1, curing it to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it to form a second flexible (PI2) layer; and finally depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the fabrication of the flexible substrate 10. After this process, both the display area 100 and the first peripheral area 200 include the substrate 10.

[0103] (2) A driving structure layer 51 pattern is prepared on the substrate 10. In an exemplary embodiment, the driving structure layer 51 of the display area 100 includes: a first transistor 101 and a first storage capacitor 102 constituting a pixel driving circuit, a first peripheral area 200 including a composite insulating layer, and a bending area 500 including a composite insulating layer with grooves.

[0104] In some exemplary embodiments, the fabrication process of the driving structure layer 51 can be described with reference to the following description.

[0105] A first insulating film and an active layer film are sequentially deposited on a substrate 10. The active layer film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, and an active layer pattern disposed on the first insulating layer 11. The active layer pattern includes at least the first active layer. After this patterning process, the first peripheral region 200 may include the first insulating layer 11 disposed on the substrate 10.

[0106] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer 12 covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 12. The first gate metal layer pattern may include at least a first gate electrode and a first capacitor electrode. After this patterning process, the first peripheral region 200 may include a first insulating layer 11 and a second insulating layer 12 stacked on the substrate 10.

[0107] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 13 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 13. The second gate metal layer pattern includes at least a second capacitor electrode, the position of which corresponds to the position of the first capacitor electrode. After this patterning process, the first peripheral region 200 may include the first insulating layer 11, the second insulating layer 12, and the third insulating layer 13 stacked on the substrate 10.

[0108] Subsequently, a fourth insulating film is deposited, and a patterning process is used to pattern the fourth insulating film to form a pattern of a fourth insulating layer 14 covering the second gate metal layer. Multiple first vias are formed on the fourth insulating layer 14. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the multiple first vias are etched away, exposing the surface of the first active layer. After this patterning process, the first peripheral region 200 may include the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 stacked on the substrate 10.

[0109] In an exemplary embodiment, during this patterning process, intermittent grooves can be formed in the bending area 500, and the first insulating layer 11, the second insulating layer 12, the third insulating layer 13 and the fourth insulating layer 14 in the grooves are removed to expose the surface of the substrate 10.

[0110] In an exemplary embodiment, a two-step patterning process can be used to form discontinuous grooves in the bending region 500. For example, firstly, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 are etched using a first mask (Etch Bending A Mask, abbreviated as EBA Mask) to form a discontinuous first groove 41 in the bending region 500, and a plurality of first vias are formed in the display area 100. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the first groove are etched away, exposing the surface of the first insulating layer 11. Then, the first insulating layer 11 within the first groove in the bending region 500 is etched away using a second mask (Etch Bending B Mask, abbreviated as EBB Mask), forming a second groove 42 on the first insulating layer 11. The first insulating layer 11 within the second groove 42 is etched away, exposing the surface of the substrate 10. In the bending region 500, the first groove 41 exposes the second groove 42, forming a stepped groove structure.

[0111] Subsequently, a third metal thin film is deposited, and patterned using a patterning process to form a source / drain metal layer 56 pattern on the fourth insulating layer 14. The source / drain metal layer 56 includes at least a first source electrode and a first drain electrode located in the display area 100, and a metal layer 98 located in the first peripheral area 200. The first source electrode and the first drain electrode can be connected to the first active layer through first vias, respectively. The metal layer 98 can, for example, serve as a data signal line.

[0112] At this point, the pattern of the driving structure layer 51 for the display region 100 is completed on the substrate 10. In the driving structure layer 51 of the display region 100, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode can form a first transistor 101, and the first capacitor electrode and the second capacitor electrode can form a first storage capacitor 102. After this patterning process, the first peripheral region 200 includes a composite insulating layer disposed on the substrate 10 and a metal layer 98 disposed on the composite insulating layer. The bending region 500 includes a composite insulating layer with grooves. The composite insulating layer includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked together.

[0113] In some exemplary embodiments, the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 are any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer 11 is called a buffer layer, used to improve the substrate's resistance to water and oxygen; the second insulating layer 12 and the third insulating layer 13 are called gate insulating (GI) layers; and the fourth insulating layer 14 is called an interlayer insulating (ILD) layer. The first metal thin film, the second metal thin film, and the third metal thin film are made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The active layer thin film uses one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0114] (3) A first planarization layer 15 is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, a planarization film of organic material is coated on the substrate 10 on which the aforementioned pattern is formed. The first planarization (PLN) layer 15 pattern is formed by masking, exposure, and development processes. The planarization film within the bending region 500 is developed away. The first planarization layer 15 includes a second via and a first through-hole. The second via is formed in the display region 100. The first planarization layer 15 within the second via is developed away, exposing the surface of the first drain electrode of the first transistor 101. The first through-hole is formed in the first peripheral region 200. The first planarization layer 15 within the first through-hole is developed away, exposing the surface of the fourth insulating layer 14. A portion of the first planarization layer 15 is retained on the side of the first through-hole away from the display region 100 to facilitate the subsequent formation of a stepped ramp region.

[0115] (4) A metal conductive layer 52 pattern is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, the metal conductive layer pattern is formed on the first planarization layer 15. The metal conductive layer 52 of the display area 100 includes at least a connection electrode 19. The connection electrode 19 is connected to the first drain electrode of the first transistor 101 through a second via. The metal conductive layer 52 of the first peripheral area 200 may include a power structure layer 212, which includes a first power line 210 and a second power line 220. The orthographic projection of the first power line 210 and the second power line 220 on the substrate 10 overlaps with the first planarization layer 15 retained on the side of the first via away from the display area 100.

[0116] like Figure 8 As shown, the power line of the first peripheral region 200 may include a main body and an extension. The extension direction of the main body may be approximately the same as the first direction, and the extension direction may intersect the first direction. The extension can connect the main body to the pads corresponding to the bonding region 400. The first direction is the extension direction parallel to the edge of the display region 100 near the first peripheral region 200. That is, the first direction is the extension direction parallel to the edge 110 of the display region.

[0117] like Figure 9 As shown, in the first direction, the edges of the extensions of the first power line 210 and the second power line 220 are both set in a sawtooth shape. In other embodiments, the edges of the extensions of the first power line 210 and the second power line 220 may be set in other shapes of sawtooth patterns, such as circles, ellipses, triangles, quadrilaterals, other polygonal shapes, or irregular shapes, etc., and this disclosure does not limit this.

[0118] like Figure 10 As shown, the orthographic projection of the sawtooth shape of the extension onto the substrate 10 can be located on the side of the second isolation dam 420 and the second groove 42 near the display area 100, and this disclosure does not limit this.

[0119] (5) A second organic insulating layer is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, a planar thin film of organic material is coated on the substrate 10 on which the aforementioned pattern is formed, and a second planarization (PLN) layer 17 pattern is formed by masking, exposure, and development processes. The second planarization layer 17 includes a third via and a plurality of second via patterns. A third via is formed on the second planarization layer 17 of the display area 100, and the third via can expose the surface of the connecting electrode 19. A plurality of second vias are formed on the second planarization layer 17 of the first peripheral area 200, and the second vias can expose the surface of the fourth insulating layer 14 and the surfaces of the first power line 210 and the second power line 220. The second planarization layer 17 in the first peripheral region 200 includes a portion of the base of the first isolation dam 410 and a portion of the base of the second isolation dam 420. A portion of the second planarization layer 17 is retained on the side of the second isolation dam 420 away from the display region 100. The orthographic projection of this portion of the second planarization layer 17 onto the substrate 10 covers the orthographic projection of the first planarization layer 15 on the side of the first via away from the display region 100 onto the substrate 10, further forming a stepped, sloping region 600. For example... Figure 10 As shown, the high-level steps of the climbing region 600 may include a first planarization layer 15, a power structure layer 212, and a second planarization layer 17 located on the composite insulating layer. After this patterning process, the film layer in the bending region 500 remains unchanged.

[0120] (6) An anode pattern is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, a transparent conductive film is deposited on the substrate 10 on which the aforementioned pattern is formed, and the transparent conductive film is patterned by a patterning process to form an anode 21 pattern. The anode 21 is formed on the second planarization layer 17 of the display area 100 and is connected to the connection electrode 19 through a third via. The connection electrode 19 is connected to the first drain electrode of the first transistor 101, and the anode 21 is connected to the first drain electrode of the first transistor 101 through the connection electrode 19. After this patterning process, the film structure of the first peripheral region 200 remains unchanged, and the film structure of the bending region 500 remains unchanged.

[0121] In some examples, the transparent conductive film is made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0122] (7) A pixel definition layer pattern is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, a pixel definition film is coated on the substrate 10 on which the aforementioned pattern is formed, and a pixel definition (PDL) layer 22 and a partial dam base pattern are formed by masking, exposure, and development processes. The pixel definition layer 22 is formed in the display area 100 and a portion of the first peripheral area 200 adjacent to the display area 100. Pixel openings are formed on the pixel definition layer 22 in the display area 100, and the pixel definition layer 22 within the pixel openings is developed away, exposing the surface of the anode 21. The pixel definition layer 22 located in the first peripheral area 200 forms a partial dam base for the first isolation dam 410 and the second isolation dam 420, and the film layer in the bending region 500 remains unchanged.

[0123] In some exemplary embodiments, the pixel definition layer 22 is made of materials such as polyimide, acrylic, or polyethylene terephthalate.

[0124] (8) A spacer pillar pattern is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, an organic material thin film is coated on the substrate 10 on which the aforementioned pattern is formed, and multiple spacer pillar (PS) patterns are formed by masking, exposure and development processes. The multiple spacer pillars 33 are respectively formed on the pixel definition layer 22 of the first peripheral region 200, and the film layer of the bending region 500 remains unchanged.

[0125] In an exemplary embodiment, the diaphragm column 33 may also serve as part of the foundation of the first isolation dam 410 and the second isolation dam 420, and this disclosure does not limit this. In other embodiments, the formation of diaphragm columns may be configured as needed.

[0126] (9) An organic light-emitting layer and a cathode are formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, an organic light-emitting layer 23 and a cathode 24 are sequentially formed on the substrate 10 on which the aforementioned pattern is formed. The organic light-emitting layer 23 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, and is formed within the pixel opening of the display area 100, thereby connecting the organic light-emitting layer 23 to the anode 21. The cathode 24 is formed on the pixel definition layer 22, connected to the organic light-emitting layer 23, and encapsulates a plurality of spacer pillars 33 on the pixel definition layer 22. After this patterning process, the film layer of the bending region 500 remains unchanged.

[0127] In some exemplary embodiments, the cathode is made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or an alloy made of any one or more of the aforementioned metals.

[0128] (10) An encapsulation layer 55 is formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, an encapsulation layer 55 is formed on the substrate 10 on which the aforementioned pattern is formed. The encapsulation layer 55 may include a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 stacked together. The first encapsulation layer 25 is made of inorganic material and covers the cathode 24 in the display area 100. It also wraps a plurality of spacer pillars 33 in the first peripheral area 200, covers the first power line 210 and the second power line 220, and wraps the first isolation dam 410 and the second isolation dam 420. The second encapsulation layer 26 is made of organic material and is disposed in the display area 100 and the area where the spacer pillars 33 are located in the first peripheral area 200. The third encapsulation layer 27 is made of inorganic material and covers the first encapsulation layer 25 and the second encapsulation layer 26. The first encapsulation layer 25 and the third encapsulation layer 27, which are made of inorganic material, directly cover the first power line 210 and the second power line 220, which can ensure that external moisture cannot enter the display area 100, thereby improving the encapsulation effect and process quality. After this patterning process, the film layer in the bending area 500 remained unchanged.

[0129] (11) A touch layer and a metal protective structure are formed on the substrate 10 on which the aforementioned pattern is formed. In some exemplary embodiments, forming a touch layer 53 and a metal protective structure 34 on the substrate 10 on which the aforementioned pattern is formed includes:

[0130] A first touch metal film is deposited on the substrate 10 on which the aforementioned pattern is formed. The first touch metal film is then patterned using a patterning process to form a first touch metal layer (TMA) 28 and a metal protective structure 34 pattern. The first touch metal layer 28 is located in the display area 100. The orthographic projection of the metal protective structure 34 onto the substrate 10 covers at least one edge of the connection portion of the power line 421 that intersects with the first direction.

[0131] Subsequently, a touch insulating film is deposited, and the touch insulating film is patterned using a patterning process to form a pattern of a first touch insulating (TLD) layer 29 covering the display area 100 and the first peripheral area 200. Touch layer openings are formed on the first touch insulating layer 29, and multiple touch layer openings expose the surface of the first touch metal layer 28.

[0132] Subsequently, a second touch metal film is deposited, and the second touch metal film is patterned using a patterning process to form a second touch metal layer pattern. The second touch metal layer pattern includes at least a plurality of second touch metal layers 30, which can be formed in the display area 100 and a portion of the first peripheral area 200 adjacent to the display area 100. Some of the plurality of second touch metal layers 30 are connected to the first touch metal layer 29 through touch layer openings.

[0133] Subsequently, a touch protection layer 31 is formed on the substrate 10 on which the aforementioned pattern is formed. The touch layer 53 includes a first touch metal layer 28, a first touch insulating layer 29, a second touch metal layer 30, and a touch protection layer 31, which are sequentially disposed. After this patterning process, the film layer in the bending region 500 remains unchanged.

[0134] In some exemplary embodiments, the first touch metal film and the second touch metal film can be single-layer structures, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or they can be multilayer structures, such as Ti / Al / Ti. The first touch insulating layer 29 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layer. The material of the touch protective layer 31 can be epoxy resin, or materials such as polyacrylate (acrylic) or siloxane resin, etc., which are not limited herein.

[0135] like Figure 8 As shown, the metal protection structure 34 includes a first metal protection structure 341 and a second metal protection structure 342. The orthographic projection of the first metal protection structure 341 on the substrate 10 can cover at least one edge of the extension of the first power line 210 intersecting with the first direction. The orthographic projection of the second metal protection structure 342 on the substrate 10 can cover at least one edge of the extension of the second power line 220 intersecting with the first direction.

[0136] like Figure 8 and Figure 10 As shown, one end of the metal protective structure 34 can be positioned near the second isolation dam 420, and the other end can be positioned near the bending area 500. Since the serrated shape of the edge of the extension is generally distributed between the second isolation dam 420 and the bending area 500, the metal protective structure 34 can cover the climbing area 600 and provide good protection for the edge of the extension. In other embodiments, the metal protective structure 34 can cover the second isolation dam 420, or the metal protective structure 34 can cover the first isolation dam 410 and the second isolation dam 420. The coverage area of ​​the metal protective structure 34 can be specifically set as needed, and this disclosure does not limit it.

[0137] Thus, as Figure 10 The display substrate shown has been fabricated.

[0138] In other embodiments, the display substrate may also include other film layer structures, which are not limited in this disclosure. After preparation is completed, the glass substrate can be peeled off.

[0139] This disclosure also provides a method for fabricating a display substrate, comprising: providing a substrate, the substrate including a display area and a first peripheral area located on one side of the display area, the first peripheral area including a ramp area, the ramp area being a first distance from the substrate near the display area and a second distance from the substrate away from the display area, the first distance being less than the second distance; forming a power line in the first peripheral area, the power line being electrically connected to a display unit of the display area; the power line including an extension extending in a direction away from the display area, the extension intersecting the ramp area; forming an encapsulation layer on the side of the power line away from the substrate; forming a metal protection structure on the side of the encapsulation layer away from the substrate, the orthographic projection of the metal protection structure on the substrate covering at least one edge of the extension intersecting the first direction, the first direction being an extension direction parallel to the edge of the display area near the first peripheral area.

[0140] This disclosure also provides a display device, including the display substrate described in any of the above embodiments. The display device can be any product or component with display function, such as an OLED display, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and this disclosure is not limited thereto.

[0141] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a first peripheral area located on one side of the display area. The first peripheral area is located at the lower edge of the display substrate and includes a ramp area. The ramp area is at a first distance from the substrate at the end near the display area and at a second distance from the substrate at the end away from the display area. The first distance is less than the second distance. The display area includes a plurality of display units. A power cord, located in the first peripheral area, includes an extension extending in a direction away from the display area, the extension overlapping the climbing area, and the power cord being electrically connected to the display unit; An encapsulation layer is disposed on the side of the power line away from the substrate. A metal protective structure is disposed on the side of the encapsulation layer away from the substrate, and the orthographic projection of the metal protective structure on the substrate covers at least one edge of the extension that intersects with a first direction, wherein the first direction is the extension direction parallel to the edge of the display area near the first peripheral area.

2. The display substrate according to claim 1, characterized in that, The first peripheral area also includes a bend area, which is located on the side of the climbing area away from the display area.

3. The display substrate according to claim 1, characterized in that, The first surrounding area also includes an isolation dam, which is located on the side of the climbing area closer to the display area.

4. The display substrate according to claim 1, characterized in that, In the first direction, the edge of the extension is serrated, and the orthographic projection of the metal protective structure on the substrate covers the orthographic projection of the serrated shape on the substrate.

5. The display substrate according to claim 3, characterized in that, The power cord includes a first power cord and a second power cord. In the first peripheral area, the second power cord is disposed on both sides of the first power cord along a first direction.

6. The display substrate according to claim 5, characterized in that, The metal protection structure includes a first metal protection structure and a second metal protection structure. The orthographic projection of the first metal protection structure on the substrate covers at least one edge where the extension of the first power line intersects with the first direction. The orthographic projection of the second metal protection structure on the substrate covers at least one edge where the extension of the second power line intersects with the first direction.

7. The display substrate according to claim 6, characterized in that, The orthographic projection of the first metal protective structure onto the substrate covers the edge of the extension of the first power line near the extension of the second power line. The orthographic projection of the second metal protective structure onto the substrate covers the edge of the extension of the second power line near the side of the extension of the first power line.

8. The display substrate according to claim 5, characterized in that, In a plane direction perpendicular to the display substrate, the display substrate includes the substrate, a driving structure layer disposed on the substrate, a first planarization layer disposed on the driving structure layer, a metal conductive layer disposed on the first planarization layer, a second planarization layer disposed on the metal conductive layer, and a light-emitting element disposed on the second planarization layer; the light-emitting element is connected to the driving structure layer through the metal conductive layer. The drive structure layer includes a source / drain metal layer, and at least one of the first power line and the second power line is disposed in the same layer as the metal conductive layer or the source / drain metal layer.

9. The display substrate according to claim 1, characterized in that, In a plane direction perpendicular to the display substrate, the display substrate further includes a touch layer disposed on the side of the encapsulation layer away from the substrate. The touch layer includes multiple metal film layers, and the metal protective structure is disposed in the same layer as any one of the multiple metal film layers.

10. The display substrate according to claim 9, characterized in that, The touch layer includes a first touch metal layer, a first touch insulating layer, a second touch metal layer, and a touch protective layer, wherein the metal protective structure is disposed in the same layer as the first touch metal layer.

11. The display substrate according to claim 5, characterized in that, On the side of the isolation dam closest to the display area, the first power line is connected to the high-voltage power line of the display area, and the second power line is connected to the low-voltage power line of the display area.

12. The display substrate according to claim 3, characterized in that, The isolation dam includes a first isolation dam and a second isolation dam, with the second isolation dam located on the side of the first isolation dam away from the display area; the climbing area is located on the side of the second isolation dam away from the display area.

13. The display substrate according to claim 5, characterized in that, The substrate further includes a second peripheral region located on the periphery of the display area and away from the ramp area, and the first peripheral region and the second peripheral region are connected and surround the display area; Within the second peripheral area, the second power line is configured to surround the display area.

14. A method for preparing a display substrate, characterized in that, include: A substrate is provided, the substrate including a display area and a first peripheral area located on one side of the display area, the first peripheral area being located at the lower border of the display substrate, and the first peripheral area including a ramp area, the ramp area being a first distance from the substrate at the end near the display area, the ramp area being a second distance from the substrate at the end away from the display area, and the first distance being less than the second distance. A power line is formed in the first peripheral area, and the power line is electrically connected to the display unit of the display area; the power line includes an extension extending in a direction away from the display area, and the extension overlaps with the climbing area; An encapsulation layer is formed on the side of the power line away from the substrate. A metal protective structure is formed on the side of the encapsulation layer away from the substrate. The orthographic projection of the metal protective structure on the substrate covers at least one edge of the extension that intersects with a first direction, where the first direction is the extension direction parallel to the edge of the display area near the first peripheral area.

15. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 13.

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