Display device

Abstract

According to an aspect of the disclosure, a display device includes a display panel in which a plurality of subpixels are disposed. Further, the display device includes a data driver configured to supply a plurality of data voltages to the plurality of subpixels through a plurality of data lines. Further, the display device includes a gate driver configured to supply a plurality of gate signals to the plurality of subpixels through a plurality of gate lines. Each of the plurality of subpixels includes a light emitting diode, a driving transistor, and a variable resistance circuit disposed in series between a low potential voltage terminal and a high potential voltage terminal. When each of the plurality of subpixels implements a low gray scale, the variable resistance circuit increases resistance between the high potential voltage terminal and the driving transistor. Accordingly, the low gray scale can be normally implemented.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0175466, filed on December 9, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of controlling the voltage applied to a driving transistor. Background Technology

[0004] Display devices used in computer monitors, TVs, mobile phones, etc. include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0005] An OLED includes a display panel comprising multiple subpixels and a driver unit for driving the display panel. The driver unit includes a gate driver for providing gate signals to the display panel via gate lines and a data driver for providing data voltages to the display panel via data lines. When signals such as gate signals and data voltages are provided to the subpixels of the OLED, selected subpixels emit light and thus display an image.

[0006] Here, each of the multiple sub-pixels includes a light-emitting diode (LED) and a driving transistor positioned between a low-potential voltage and a high-potential voltage. A relatively low voltage is applied to the LED to achieve low grayscale, while a relatively high voltage is applied to the LED to achieve high grayscale.

[0007] Therefore, when achieving low grayscale, a relatively high voltage is applied to the driving transistor, and when achieving high grayscale, a relatively low voltage is applied to the driving transistor.

[0008] In other words, when achieving low grayscale, the voltage between the source and drain electrodes of the driving transistor increases, which leads to a kinking effect where the current between the source and drain electrodes of the driving transistor increases rapidly. Therefore, sub-pixels cannot achieve low grayscale, and thus cannot achieve relatively high grayscale. Summary of the Invention

[0009] The objective of this disclosure is to provide a display device capable of suppressing kinking effects.

[0010] Another objective of this disclosure is to provide a display device capable of stably achieving low grayscale.

[0011] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above can be clearly understood by those skilled in the art from the following description.

[0012] According to one aspect of this disclosure, a display device includes a display panel in which a plurality of sub-pixels are disposed. Furthermore, the display device includes a data driver configured to provide a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines. Additionally, the display device includes a gate driver configured to provide a plurality of gate signals to the plurality of sub-pixels via a plurality of gate lines. Each of the plurality of sub-pixels includes a light-emitting diode, a driving transistor, and a variable resistor circuit connected in series between a low-potential voltage terminal and a high-potential voltage terminal. When each of the plurality of sub-pixels achieves low grayscale, the variable resistor circuit increases the resistance between the high-potential voltage terminal and the driving transistor. Thus, low grayscale can be properly achieved.

[0013] Other aspects of the exemplary embodiments are included in the detailed implementation and the accompanying drawings.

[0014] According to this disclosure, when a sub-pixel achieves low grayscale, the voltage of the drain electrode of the driving transistor shifts. Therefore, it is possible to suppress kinking effects in the driving transistor.

[0015] According to this disclosure, a low driving current can flow within the light-emitting diode. Therefore, sub-pixels can achieve low grayscale correctly.

[0016] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0017] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0018] Figure 1 This is a schematic diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 2 and Figure 3 This is a circuit diagram illustrating sub-pixels of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figures 4A to 4D This is a waveform diagram showing the gate signal of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 5 This is a circuit diagram for explaining the operation of the variable resistor circuit of the display device according to exemplary embodiments of the present disclosure; and

[0022] Figure 6 This is a circuit diagram used to explain the relationship between the drive current and voltage of a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0023] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0024] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0025] Even if not explicitly stated, components are interpreted as including a general error range.

[0026] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “directly” or “directly.”

[0027] When an element or layer is placed "on" another element or layer, the other layer or another element can be directly inserted on or between the other element.

[0028] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0029] Throughout the specification, similar reference numerals generally denote similar elements.

[0030] The dimensions and thicknesses of each component shown in the figures are for illustrative purposes only, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0031] Features of the various embodiments of this disclosure may be partially or wholly adhered to or combined with each other, and may be technically interlocked and operated in various ways, and embodiments may be performed independently or in association with each other.

[0032] The transistors used in the display device of this disclosure can be implemented as at least one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented as an oxide semiconductor transistor having an oxide semiconductor as the active layer or an LTPS transistor having a low-temperature polycrystalline silicon (LTPS) as the active layer. The transistor can include at least a gate electrode, a source electrode, and a drain electrode. The transistor can be implemented as a thin-film transistor (TFT) on a display panel. In the transistor, charge carriers flow from the source electrode to the drain electrode. In NMOS, the charge carriers are electrons, and thus, the source voltage is lower than the drain voltage, allowing electrons to flow from the source electrode to the drain electrode. In NMOS, current can flow from the drain electrode to the source electrode, and the source electrode can be an output terminal. In PMOS, the charge carriers are holes, and thus, the source voltage is higher than the drain voltage, allowing holes to flow from the source electrode to the drain electrode. In PMOS, holes flow from the source electrode to the drain electrode, and thus, current flows from the source to the drain, and the drain electrode can be an output terminal. Therefore, it should be noted that the source and drain of a transistor are not fixed, as they can change depending on the applied voltage. In this disclosure, it is assumed that the transistor is an NMOS, but this is not a limitation, and a PMOS can also be used. Therefore, the circuit configuration can be varied.

[0033] The gate signal of a transistor used as a switching element oscillates between a turn-on voltage and a turn-off voltage. The turn-on voltage is set to a voltage higher than the transistor's threshold voltage, and the turn-off voltage is set to a voltage lower than the transistor's threshold voltage. The transistor turns on in response to the turn-on voltage and turns off in response to the turn-off voltage. In NMOS, the turn-on voltage can be high, and the turn-off voltage can be low. In PMOS, the turn-on voltage can be low, and the turn-off voltage can be high.

[0034] Various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0035] Figure 1 This is a schematic diagram illustrating a display device according to an exemplary embodiment of the present disclosure. Reference Figure 1 The display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0036] Display panel 110 is a panel for displaying images. Display panel 110 may include various circuits, lines, and light-emitting diodes disposed on a substrate. Display panel 110 may include a plurality of pixels PX defined by multiple data lines DL and multiple gate lines GL that intersect each other. Furthermore, the plurality of pixels PX are connected to the multiple data lines DL and multiple gate lines GL. Display panel 110 may include a display area defined by the plurality of pixels PX and a non-display area where various signal lines or pads are formed. Display panel 110 can be implemented using display panels 110 used in various display devices such as liquid crystal display devices, organic light-emitting display devices, or electrophoretic display devices. In the following description, display panel 110 is described as a panel for use in organic light-emitting display devices, but is not limited thereto.

[0037] The timing controller 140 receives timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, and point clocks via a receiver circuit such as an LVDS (Low Voltage Differential Signaling) or TMDS (Transition Minimum Differential Signaling) interface connected to the host system. Based on the received timing signals, the timing controller 140 generates timing control signals for controlling the data driver 130 and the gate driver 120.

[0038] Data driver 130 provides data voltages to multiple sub-pixels SP. Data driver 130 may include multiple source driver integrated circuits (ICs). The multiple source driver ICs can receive digital video data and source timing control signals from timing controller 140. The multiple source driver ICs can convert digital video data into gamma voltages to generate data voltages in response to the source timing control signals. In addition, the multiple source driver ICs can provide data voltages via data lines DL of display panel 110. The multiple source driver ICs can be connected to the data lines DL of display panel 110 via chip-on-glass (COG) technology or tape automated bonding (TAB) technology. Furthermore, the source driver ICs can be formed on display panel 110, or they can be formed on a separate PCB and connected to display panel 110.

[0039] Gate driver 120 provides gate signals to a plurality of sub-pixels SP. Gate driver 120 may include a level shifter and a shift register. The level shifter may shift the level of a clock signal input from timing controller 140 at transistor-transistor-logic (TTL) levels and then provide it to the shift register. The shift register may be formed in a non-display area of ​​display panel 110 using GIP technology, but is not limited thereto. The shift register may include multiple stages for shifting the gate signals in response to clock and drive signals to output them. The multiple stages included in the shift register may sequentially output the gate signals through multiple output terminals. As described later, the gate signals may include scan signals, sensing signals, and initialization signals.

[0040] The display panel 110 may include multiple subpixels SP. The multiple subpixels SP can emit light of different colors. For example, the multiple subpixels SP may include red subpixels, green subpixels, and blue subpixels, but are not limited to these. The multiple subpixels SP can form a pixel PX. That is, red subpixels, green subpixels, and blue subpixels can form a single pixel PX, and the display panel 110 may include multiple pixel PXs.

[0041] In the following text, reference will be made to Figure 2 and Figure 3 Describe in detail the driver circuitry used to drive a single subpixel SP.

[0042] Figure 2 and Figure 3 This is a circuit diagram illustrating sub-pixels of a display device according to an exemplary embodiment of the present disclosure.

[0043] Figure 2 and Figure 3 This is a circuit diagram showing one of the multiple sub-pixels SP of the display device 100. Specifically, Figure 2 The diagram shows the case where the control capacitor Cct is connected to the reference voltage line, while Figure 3 The diagram illustrates the case where the control capacitor Cct is connected to the drive transistor.

[0044] refer to Figure 2 Each sub-pixel SP includes a light-emitting diode (LED), a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SST), an initialization transistor (INT), a storage capacitor (Cst), and variable resistor circuits (CTT1, CTT2, R, and Cct).

[0045] A light-emitting diode (LED) emits light through a drive current supplied from a driving transistor (DRT). The anode of the LED is connected to a storage capacitor (Cst), the driving transistor (DRT), and a sensing transistor (SST). Furthermore, the cathode of the LED is connected to a low-potential voltage terminal, to which a low-potential voltage (EVSS) is applied.

[0046] The driving transistor DRT controls the driving current applied to the light-emitting diode (LED) based on its source-gate voltage Vsg. Furthermore, the gate electrode of the driving transistor DRT is connected to the first node N1, its source electrode is connected to the second node N2, and its drain electrode is connected to the third node N3.

[0047] The switching transistor SWT applies the data voltage Vdata provided from the data line DL to the first node N1, which is the gate electrode of the driving transistor DRT. The switching transistor SWT includes a drain electrode connected to the data line DL, a source electrode connected to the first node N1, and a gate electrode connected to the gate line used to transmit the scan signal SCAN. Therefore, in response to a high-level scan signal SCAN (which is on), the switching transistor SWT applies the data voltage Vdata provided from the data line DL to the first node N1, which is the gate electrode of the driving transistor DRT.

[0048] The sensing transistor SST applies a reference voltage Vref to the anode electrode of the light-emitting diode (LED). The sensing transistor SST includes a drain electrode connected to a reference voltage line RL for transmitting the reference voltage Vref. The sensing transistor SST also includes a source electrode connected to the anode electrode of the LED and a gate electrode connected to a gate line for transmitting a sensing signal SENSE. Therefore, the sensing transistor SST applies the reference voltage Vref to the anode electrode of the LED in response to a high-level sensing signal SENSE, which is an on-state signal. Thus, the sensing transistor SST senses the voltage at the anode electrode of the LED.

[0049] The initialization transistor INT applies an initialization voltage Vinit to the first node N1, which is the gate electrode of the driving transistor DRT. The initialization transistor INT includes a drain electrode connected to an initialization voltage line IL for transmitting the initialization voltage Vinit. The initialization transistor INT also includes a drain electrode connected to the first node N1, which is the gate electrode of the driving transistor DRT, and a gate electrode connected to an initialization signal line IL for transmitting the initialization signal INI. Therefore, in response to a high-level initialization signal INI (which is an on-state), the initialization transistor INT applies the initialization voltage Vinit to the first node N1, which is the gate electrode of the driving transistor DRT. Thus, the initialization transistor INT initializes the driving transistor DRT.

[0050] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the second node N2. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DRT, and the other electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor DRT.

[0051] When each of the multiple sub-pixels achieves a low grayscale, the variable resistor circuits CTT1, CTT2, R, and Cct increase the resistance between the high-potential voltage terminal and the driving transistor DRT.

[0052] The variable resistor circuit CTT1, CTT2, R and Cct includes a first control transistor CTT1, a second control transistor CTT2, a resistor R and a control capacitor Cct.

[0053] The first control transistor CTT1 includes a drain electrode connected to a high-potential voltage terminal of the applied high-potential voltage EVSS, and a source electrode connected to a third node N3 connected to the driving transistor DRT. The first control transistor CTT1 also includes a gate electrode connected to a fourth node N4, which is connected to the second control transistor CTT2.

[0054] One electrode of resistor R is connected to the third node N3 and the other electrode is connected to the fourth node N4. Resistor R is positioned between the source and drain electrodes of the first control transistor CTT1.

[0055] In other words, the first control transistor CTTl and the resistor R can be connected in parallel between the high-potential voltage terminal and the drive transistor DRT.

[0056] Furthermore, the source electrode of the second control transistor CTT2 is connected to the fourth node N4, and the gate electrode of the second control transistor CTT2 is connected to the gate line for transmitting the scan signal SCAN. Additionally, the drain electrode of the second control transistor CTT2 is connected to the control line CL for transmitting the control voltage Vct.

[0057] Therefore, the second control transistor CTT2 can control the first control transistor CTT1.

[0058] Specifically, in response to a high-level scan signal SCAN that is at the on level, the second control transistor CTT2 applies a control voltage Vct provided from the control line CL to the fourth node N4, which is the gate electrode of the first control transistor CTT1.

[0059] Then, the first control transistor CTT1 operates according to the level of the control voltage Vct transmitted through the second control transistor CTT2. Specifically, when the control voltage Vct has a high level (on-state), the first control transistor CTT1 is turned on. Furthermore, a current path in parallel with resistor R is formed between the high-potential voltage terminal and the drive transistor DRT. Therefore, the resistance value between the high-potential voltage terminal and the drive transistor DRT can be reduced. Conversely, when the control voltage Vct has a low level (off-state), the first control transistor CTT1 is turned off. Furthermore, no current path in parallel with resistor R is formed between the high-potential voltage terminal and the drive transistor DRT. Therefore, the resistance value between the high-potential voltage terminal and the drive transistor DRT can be increased.

[0060] At the same time, refer to Figure 2 The control capacitor Cct includes a first electrode connected to the fourth node N4 and a second electrode connected to the reference voltage line RL. That is, one electrode of the storage control capacitor Cct is connected to the gate electrode of the first control transistor CTT1, and the other electrode of the control capacitor Cct is connected to the reference voltage line RL, which is used to transmit a reference voltage Vref as a constant voltage.

[0061] refer to Figure 3 The control capacitor Cct includes a first electrode connected to the fourth node N4 and a second electrode connected to the third node N3. That is, one electrode of the storage control capacitor Cct is connected to the gate electrode of the first control transistor CTT1, and the other electrode of the control capacitor Cct is connected to the source electrode of the first control transistor CTT1.

[0062] Therefore, the control capacitor Cct can maintain the control voltage Vct stored in the fourth node N4 for a predetermined period of time. In other words, the control capacitor Cct can maintain the control voltage Vct applied to the gate electrode of the first control transistor CTT1 for a predetermined period of time to maintain the operation of the first control transistor CTT1.

[0063] Figures 4A to 4D This is a waveform diagram showing the gate signal of a display device according to an exemplary embodiment of the present disclosure.

[0064] exist Figures 4A to 4D In this context, all signals and voltages except for the control voltage Vct applied to the fourth node N4 have the same level. Figure 4A The waveform is shown when the gray level of a sub-pixel changes from high gray level to low gray level. Figure 4B The waveform is shown when the gray level of a sub-pixel changes from low gray level to high gray level. Figure 4C The waveform is shown when the grayscale of the subpixel remains high, and Figure 4DThe waveform is shown when the grayscale of the subpixel remains low.

[0065] Reference Figures 2 to 4D Describes the driving of a display device according to exemplary embodiments of the present disclosure.

[0066] refer to Figures 4A to 4D During the initial period, the initialization signal INI has a high level (on level) and the sensing signal SENSE has a high level (on level). Furthermore, during the initial period, the scan signal SCAN has a low level (off level). Thus, the initialization transistor INT turns on and applies the initialization voltage Vinit to the first node N1. As a result, the gate electrode of the driving transistor DRT is initialized to the initialization voltage Vinit. The initialization voltage Vinit can be selected within a range sufficiently lower than the operating voltage of the LED and is set to be equal to or lower than the low potential voltage VSS. Additionally, during the initial period, the sensing transistor SST turns on and applies the reference voltage Vref to the second node N2. As a result, the sensing transistor SST applies the reference voltage Vref to the anode electrode of the LED and senses the voltage at the anode electrode of the LED. The reference voltage Vref can be selected within a range sufficiently lower than the operating voltage of the LED and is set to be equal to or lower than the low potential voltage VSS.

[0067] In addition, refer to Figures 4A to 4D During the sampling period, the initialization signal INI is at a high level (on), and the sensing signal SENSE is at a low level (off). Furthermore, during the sampling period, the scan signal SCAN is at a low level (off). Additionally, during the sampling period, the initialization transistor INT remains on, maintaining the initialization voltage Vinit at the first node N1. However, during the sampling period, the sensing transistor SST is off, and thus, the voltage at the second node N2 increases from the reference voltage Vref to a voltage equal to the difference between the initialization voltage Vinit and the threshold voltage Vth. In other words, the voltage at the second node N2 increases through the current flowing from the source to the drain of the driving transistor DRT until the gate-source voltage Vgs of the driving transistor DRT reaches the threshold voltage Vth. Therefore, the threshold voltage Vth of the driving transistor is sampled in the storage capacitor Cst.

[0068] In addition, refer to Figures 4A to 4DDuring the write phase, the initialization signal INI is at a low level (off), and the sensing signal SENSE is also at a low level (off). Furthermore, during the write phase, the scan signal SCAN is at a high level (on). Additionally, during the write phase, the switching transistor SWT is turned on and applies the data voltage Vdata to the first node N1. The threshold voltage Vth of the driving transistor is stored in the storage capacitor Cst. Consequently, the voltage at the second node N2 increases, maintaining the voltage difference between the second node N2 and the first node N1 at the threshold voltage Vth, which is the gate-source voltage Vgs of the driving transistor DRT.

[0069] In addition, refer to Figures 4A to 4D During the boost phase, the data voltage Vdata is applied to the first node N1, which is the gate electrode of the driving transistor DRT. Therefore, the voltage at the second node N2 increases due to the current flowing from the source electrode to the drain electrode. Furthermore, the gate-source voltage Vgs of the driving transistor DRT is stored in the storage capacitor Cst. Thus, the voltage at the first node N1 increases, maintaining the voltage difference between the first node N1 and the second node N2 at a threshold voltage Vth, which is the gate-source voltage Vgs of the driving transistor DRT.

[0070] During the light-emitting period, a current path is formed between the driving transistor DRT and the light-emitting diode LED through the boost voltage of the second node N2. As a result, the driving current flowing through the source and drain electrodes of the driving transistor DRT is applied to the light-emitting diode LED.

[0071] Meanwhile, during the write period when the data voltage is written to the driving transistor, the voltage of the fourth node N4 can be changed.

[0072] As described above, the scan signal SCAN is on during the write period, and thus, the second control transistor CTT2 is turned on. Therefore, the change in the control voltage Vct during the write period is reflected in the fourth node N4.

[0073] For example, such as Figure 4A As shown, when the grayscale of a sub-pixel changes from high grayscale to low grayscale, the data voltage Vdata changes to a data voltage Vdata equal to or lower than the threshold voltage, thus achieving low grayscale. Therefore, the control voltage Vct changes to a low level. Consequently, the voltage of the fourth node N4 decreases to the low level control voltage Vct during the write period.

[0074] However, as Figure 4BAs shown, when the grayscale of a sub-pixel changes from low to high, the data voltage Vdata changes to a data voltage Vdata equal to or higher than the threshold voltage, thus achieving high grayscale. Therefore, the control voltage Vct changes to a high level. Consequently, the voltage of the fourth node N4 increases to a high level control voltage Vct during the write period.

[0075] like Figure 4C As shown, when the grayscale of a subpixel remains high, the data voltage Vdata remains equal to or higher than the threshold voltage, thus achieving high grayscale. Therefore, the control voltage Vct remains at a high level. Consequently, the voltage of the fourth node N4 remains at a high level during the write period.

[0076] However, as Figure 4D As shown, when the grayscale of a subpixel remains low, the data voltage Vdata remains equal to or lower than the threshold voltage Vdata, thus achieving low grayscale. Therefore, the control voltage Vct remains at a low level. Consequently, the voltage of the fourth node N4 remains at a low level during the write period.

[0077] Threshold voltage can refer to a predetermined voltage level between low grayscale data voltage and high grayscale data voltage.

[0078] To achieve the above operation, when the data voltage Vdata is lower than the threshold voltage before the write phase, the control voltage Vct can be output as a low level (off level). Conversely, when the data voltage Vdata is higher than the threshold voltage before the write phase, the control voltage Vct can be output as a high level (on level).

[0079] In the following, reference will be made to exemplary embodiments of the present disclosure. Figure 5 and Figure 6 This describes the drivers for display devices that implement low grayscale and the drivers for display devices that implement high grayscale.

[0080] Figure 5 This is a circuit diagram used to explain the operation of a variable resistor circuit of a display device according to an exemplary embodiment of the present disclosure.

[0081] Figure 6 This is a circuit diagram used to explain the relationship between the drive current and voltage of a display device according to an exemplary embodiment of the present disclosure.

[0082] Figure 6 The voltage relationship is shown, for example, when the high potential voltage EVDD applied to the high potential voltage terminal is set to 13V and the low potential voltage EVSS applied to the low potential voltage terminal is set to 0V.

[0083] like Figure 5 As shown, when a sub-pixel achieves high grayscale, the control voltage Vct is at a high level. Consequently, the first control transistor CTT1 is turned on. Therefore, current flows through the first control transistor CTT1 between the high-potential voltage terminal and the third node N3. Thus, the voltage drop between the high-potential voltage terminal and the third node N3 is insignificant. That is, the resistance between the high-potential voltage terminal and the driving transistor DRT is close to zero. Therefore, when line resistance is ignored, the voltage at the third node N3 can be the high-potential voltage EVDD.

[0084] Therefore, as Figure 6 As shown, when a sub-pixel achieves high grayscale, the voltage between the source and drain electrodes (second node N2 and third node N3) of the driving transistor DRT is 3V in the VI curve. Therefore, the voltage at the second node N2 is 10V. Similarly, in the VI curve of a light-emitting diode (LED), the voltage between the anode and cathode electrodes is 10V. Therefore, a high driving current flows in the LED, making it possible to achieve high grayscale.

[0085] However, as Figure 5 As shown, when a sub-pixel achieves low grayscale, the control voltage Vct is at a low level. Consequently, the first control transistor CTT1 is turned off. Therefore, current flows through resistor R between the high-potential voltage terminal and the third node N3. Thus, a predetermined voltage drop occurs between the high-potential voltage terminal and the third node N3. That is, the resistance value between the high-potential voltage terminal and the driving transistor DRT can be increased. Therefore, the voltage at the third node N3 can have a level obtained by reflecting the level of the voltage drop caused by resistor R onto the high-potential voltage.

[0086] Therefore, as Figure 6 As shown, when a sub-pixel achieves low grayscale, a 2V voltage drop occurs due to resistor R in the VI curve of the driving transistor DRT. Therefore, the voltage at the third node N3, the source electrode of the driving transistor DRT, is 11V. Furthermore, the voltage between the source and drain electrodes (second node N2 and third node N3) of the driving transistor DRT is 10V. Therefore, the voltage at the second node N2 is 1V. Additionally, in the VI curve of the light-emitting diode (LED), the voltage between the anode and cathode electrodes of the LED is 1V. Therefore, a low driving current flows in the LED, making it possible to achieve low grayscale.

[0087] In traditional display devices, even when sub-pixels achieve low grayscale, no variable resistor circuit is provided. Therefore, the drain electrode of the driving transistor has a high potential voltage. Thus, as... Figure 6 As shown, when a sub-pixel achieves low grayscale, the voltage between the source and drain electrodes of the driving transistor (DRT) is 11V in the VI curve. Therefore, the voltage at the anode electrode of the LED is 2V. In this case, the driving current cannot remain constant in the VI curve of the driving transistor, and a kinking effect occurs, causing the driving current to increase rapidly. Consequently, the LED outputs relatively high brightness light. Therefore, in conventional display devices, sub-pixels cannot properly achieve low grayscale.

[0088] However, in the display device of this disclosure, a variable resistor circuit is disposed between the high-potential voltage terminal and the driving transistor. Therefore, when a sub-pixel achieves low grayscale, the voltage of the drain electrode of the driving transistor shifts to suppress kinking effects in the driving transistor.

[0089] Therefore, in the display device of this disclosure, a low driving current can flow in the light-emitting diode, and thus the sub-pixels can normally achieve low grayscale.

[0090] Exemplary embodiments of this disclosure can also be described as follows:

[0091] According to one aspect of this disclosure, a display device includes a display panel in which a plurality of sub-pixels are disposed. Furthermore, the display device includes a data driver configured to provide a plurality of data voltages to the plurality of sub-pixels via a plurality of data lines. Additionally, the display device includes a gate driver configured to provide a plurality of gate signals to the plurality of sub-pixels via a plurality of gate lines. Each of the plurality of sub-pixels includes a light-emitting diode, a driving transistor, and a variable resistor circuit connected in series between a low-potential voltage terminal and a high-potential voltage terminal. When each of the plurality of sub-pixels achieves low grayscale, the variable resistor circuit increases the resistance between the high-potential voltage terminal and the driving transistor. Thus, low grayscale can be properly achieved.

[0092] The variable resistor circuit may include a first control transistor, a second control transistor, and a resistor. The first control transistor and the resistor are connected in parallel between a high-potential voltage terminal and a driving transistor, and the second control transistor controls the first control transistor.

[0093] The first control transistor can be turned off when each of the multiple sub-pixels achieves a low grayscale and turned on when each of the multiple sub-pixels achieves a high grayscale.

[0094] The gate electrode of the first control transistor can be connected to the second control transistor, the drain electrode of the first control transistor is connected to a high-potential voltage terminal, and the source electrode of the first control transistor is connected to the driving transistor.

[0095] A resistor can be placed between the source and drain electrodes of the first control transistor.

[0096] The gate electrode of the second control transistor can be connected to one of a plurality of gate lines for transmitting scan signals, the drain electrode of the second control transistor can be connected to a control line for transmitting control voltage, and the source electrode of the second control transistor can be connected to the first control transistor.

[0097] The control voltage has a turn-off level when the data voltage can be below the threshold voltage, and a turn-on level when the data voltage is above the threshold voltage.

[0098] The level of the control voltage can be changed before the write period when data voltage is written to multiple sub-pixels.

[0099] The voltage level of the gate electrode of the first control transistor can be changed during the write period.

[0100] The variable resistor circuit may also include a control capacitor connected to the gate electrode of the first control transistor.

[0101] The control capacitor can be connected to the source electrode of the first control transistor.

[0102] The control capacitor can be connected to a reference voltage line used to apply a constant voltage.

[0103] Each of the plurality of sub-pixels may further include a switching transistor that applies a data voltage to a driving transistor, a storage transistor that stores the gate-source voltage of the driving transistor therein, and a sensing transistor that applies a reference voltage to a light-emitting diode and thereby senses the light-emitting diode.

[0104] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: The display panel contains multiple sub-pixels; The data driver is configured to provide multiple data voltages to the multiple sub-pixels via multiple data lines; as well as A gate driver is configured to provide multiple gate signals to the multiple sub-pixels via multiple gate lines. Each of the plurality of sub-pixels includes a light-emitting diode, a driving transistor, and a variable resistor circuit connected in series between a low-potential voltage terminal and a high-potential voltage terminal. When each of the plurality of sub-pixels achieves a low grayscale, the variable resistor circuit increases the resistance between the high-potential voltage terminal and the driving transistor. The variable resistor circuit includes a first control transistor, a second control transistor, and a resistor, wherein the first control transistor and the resistor are connected in parallel between the high-potential voltage terminal and the driving transistor. In this configuration, the gate electrode of the second control transistor is connected to one of the plurality of gate lines, the drain electrode of the second control transistor is connected to a control line for transmitting control voltage, and the source electrode of the second control transistor is connected to the gate electrode of the first control transistor. The first control transistor is turned off when each of the plurality of sub-pixels achieves low grayscale, and turned on when each of the plurality of sub-pixels achieves high grayscale.

2. The display device according to claim 1, wherein, Each of the plurality of sub-pixels also includes an initialization transistor having a drain electrode connected to the gate electrode of the driving transistor.

3. The display device according to claim 2, wherein, The initialization transistor is configured to apply an initialization voltage to the gate electrode of the drive transistor.

4. The display device according to claim 1, wherein, The drain electrode of the first control transistor is connected to the high-potential voltage terminal, and The source electrode of the first control transistor is connected to the drive transistor.

5. The display device according to claim 1, wherein, The resistor is disposed between the source electrode and the drain electrode of the first control transistor.

6. The display device according to claim 1, wherein, One of the plurality of gate lines is configured to transmit a scan signal.

7. The display device according to claim 1, wherein, The control voltage has a shutdown level when the data voltage is below a threshold voltage and a conduction level when the data voltage is above the threshold voltage.

8. The display device according to claim 6, wherein, The level of the control voltage is changed before the data voltage is written to the plurality of sub-pixels during the writing period.

9. The display device according to claim 8, wherein, The voltage level of the gate electrode of the first control transistor changes during the write period.

10. The display device according to claim 1, wherein, The variable resistor circuit also includes a control capacitor connected to the gate electrode of the first control transistor.

11. The display device according to claim 10, wherein, The control capacitor is connected to the source electrode of the first control transistor.

12. The display device according to claim 10, wherein, The control capacitor is connected to a reference voltage line, which is used to apply a reference voltage that is constant.

13. The display device according to claim 1, wherein, Each of the plurality of sub-pixels also includes: A switching transistor is used to apply the data voltage to the driving transistor; A storage capacitor, wherein the gate-source voltage of the driving transistor is stored; and A sensing transistor is used to apply a reference voltage to the light-emitting diode and thereby sense the light-emitting diode.

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