Epitaxial structure and method of manufacturing the same

Abstract

The present disclosure provides an epitaxial structure and a preparation method thereof, and belongs to the technical field of optoelectronic manufacturing. The epitaxial structure comprises a substrate, a silicon atom blocking layer and an epitaxial layer, the silicon atom blocking layer and the epitaxial layer are sequentially stacked on the substrate, and the silicon atom blocking layer is used for blocking the diffusion of silicon atoms in the substrate to the epitaxial layer. The embodiment of the present disclosure can improve the problem that silicon atoms are easily diffused from the substrate to the epitaxial layer, and improve the crystal quality of the epitaxial layer.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an epitaxial structure and its preparation method. Background Technology

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field-effect transistor, also known as modulation-doped field-effect transistor, two-dimensional electron gas field-effect transistor, selectively doped heterojunction transistor, etc. The core structure of HEMT devices is the epitaxial structure, and the fabrication of the epitaxial structure has a significant impact on the crystal quality of HEMT devices.

[0003] Epitaxial structures typically consist of a substrate and epitaxial layers stacked sequentially. Due to the advantages of Si substrates, such as low cost, ease of large-size fabrication, and good thermal conductivity, Si substrates are commonly used as substrates in related technologies.

[0004] However, under high-temperature conditions, Si atoms can diffuse into the subsequent epitaxial layers, which can adversely affect the crystal quality of the epitaxial layers and reduce the reliability of HEMT devices. Summary of the Invention

[0005] This disclosure provides an epitaxial structure and its fabrication method, which can improve the problem of silicon atoms easily diffusing from the substrate to the epitaxial layer and enhance the crystal quality of the epitaxial layer. The technical solution is as follows:

[0006] On one hand, this disclosure provides an epitaxial structure comprising a substrate, a silicon atom barrier layer, and an epitaxial layer, wherein the silicon atom barrier layer and the epitaxial layer are sequentially stacked on the substrate, and the silicon atom barrier layer is used to prevent silicon atoms in the substrate from diffusing into the epitaxial layer.

[0007] Optionally, the silicon atom barrier layer comprises a first sublayer, a second sublayer, and a third sublayer stacked sequentially; the first sublayer comprises an AlN layer, the second sublayer comprises a Mg-doped AlN layer, and the third sublayer comprises a Mg-doped AlN layer. x In y Ga (1-x-y) N layers, where 0.1 < x < 0.5, 0 < y < 0.2.

[0008] Optionally, the thickness of the first sublayer is 5nm to 50nm, the thickness of the second sublayer is 10nm to 100nm, and the thickness of the third sublayer is 100nm to 200nm.

[0009] Optionally, the Mg doping concentration of the second sublayer is 1×10⁻⁶. 17 cm -3Up to 1×10 18 cm -3 The Mg doping concentration of the third sublayer is 1×10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 .

[0010] Optionally, the epitaxial layer includes an AlGaN buffer layer stacked on the silicon atom barrier layer, wherein the mass percentage of Al in the AlGaN buffer layer is 10% to 70%.

[0011] Optionally, the thickness of the AlGaN buffer layer is from 100 nm to 1500 nm.

[0012] Optionally, the epitaxial layer includes an AlGaN high-resistivity layer, a GaN channel layer, an AlGaN barrier layer, and a GaN cap layer sequentially stacked on the silicon atom barrier layer.

[0013] On the other hand, this disclosure also provides a method for preparing an epitaxial structure, the method comprising: providing a substrate; forming a silicon atom barrier layer on the substrate; and forming an epitaxial layer on the silicon atom barrier layer, wherein the silicon atom barrier layer is used to prevent silicon atoms in the substrate from diffusing into the epitaxial layer.

[0014] Optionally, forming a silicon atom barrier layer on the substrate includes: sequentially forming a first sublayer, a second sublayer, and a third sublayer on the substrate, wherein the first sublayer comprises an AlN layer, the second sublayer comprises a Mg-doped AlN layer, and the third sublayer comprises a Mg-doped AlN layer. x In y Ga (1-x-y) N layers, where 0.1 < x < 0.5, 0 < y < 0.2.

[0015] Optionally, when growing the first sublayer, the growth temperature is 800°C to 900°C, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere; when growing the second sublayer, the growth temperature is 850°C to 1000°C, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere; when growing the third sublayer, the growth temperature is 950°C to 1050°C, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The epitaxial structure provided in this disclosure provides a silicon atom barrier layer between the substrate and the epitaxial layer. This silicon atom barrier layer prevents silicon atoms in the substrate from diffusing into the epitaxial layer under high temperature conditions, thus improving the problem of silicon atoms easily diffusing from the substrate to the epitaxial layer and enhancing the crystal quality of the epitaxial layer and the reliability of HEMT devices. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the epitaxial structure of a high electron mobility transistor provided in an embodiment of this disclosure;

[0020] Figure 2 This is a flowchart of a method for fabricating an epitaxial structure of a high electron mobility transistor according to an embodiment of this disclosure.

[0021] The markings in the diagram are explained as follows:

[0022] 10. Substrate;

[0023] 20. Silicon atom barrier layer;

[0024] 21. First sub-layer; 22. Second sub-layer; 23. Third sub-layer;

[0025] 30. Epitaxial layer;

[0026] 31. AlGaN buffer layer; 32. AlGaN high-resistivity layer; 33. GaN channel layer; 34. AlGaN barrier layer; 35. GaN cap layer. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0028] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0029] In related technologies, gallium nitride (GaN) is the primary material for the epitaxial layer in the epitaxial structure of high electron mobility transistors (HETTs). Therefore, the key to improving the quality of HETTs lies in producing high-quality GaN material layers. Due to the characteristics of the GaN crystal lattice, there is a lack of a substrate material in nature that can match the GaN lattice similarly and has a relatively low manufacturing cost. Currently, commonly used substrates are silicon carbide, sapphire, and silicon substrates.

[0030] Because silicon carbide (SiC) has the smallest lattice mismatch with gallium nitride (GaN), GaN films epitaxially grown on SiC substrates have the best quality. However, using SiC substrates is far more expensive than using sapphire substrates. Silicon substrates, on the other hand, are inexpensive, easy to fabricate in large sizes, have good thermal conductivity, and are compatible with traditional silicon processes, making them the preferred substrate for HEMT epitaxial growth.

[0031] However, silicon atoms can diffuse into the subsequent epitaxial layer under high temperature conditions, which can adversely affect the crystal quality of the epitaxial layer and reduce the reliability of HEMT devices.

[0032] In addition, there is a 16.9% lattice mismatch and a 56% thermal mismatch between silicon and gallium nitride. The huge lattice and thermal mismatch between GaN and silicon substrates leads to problems such as high dislocation density, large warpage and easy cracking of GaN thin films, making the fabrication of GaN electronic devices difficult and limiting the widespread application of GaN-based HEMT devices.

[0033] Figure 1 This is a schematic diagram of the epitaxial structure of a high electron mobility transistor provided in an embodiment of this disclosure. Figure 1As shown, the epitaxial structure includes a substrate 10, a silicon atom barrier layer 20, and an epitaxial layer 30. The silicon atom barrier layer 20 and the epitaxial layer 30 are stacked sequentially on the substrate 10. The silicon atom barrier layer 20 is used to prevent silicon atoms in the substrate 10 from diffusing into the epitaxial layer 30.

[0034] The epitaxial structure provided in this embodiment of the present disclosure, by providing a silicon atom barrier layer 20 between the substrate 10 and the epitaxial layer 30, prevents silicon atoms in the substrate 10 from diffusing into the epitaxial layer 30. This avoids the diffusion of silicon atoms from the substrate 10 into the subsequent epitaxial layer 30 under high-temperature conditions, improves the problem of silicon atoms easily diffusing from the substrate 10 to the epitaxial layer 30, and enhances the crystal quality of the epitaxial layer 30 and the reliability of HEMT devices.

[0035] For example, substrate 10 includes a silicon substrate. Substrate 10 can be a flat substrate or a patterned substrate.

[0036] As an example, in this embodiment of the disclosure, the substrate 10 is a flat silicon substrate. Silicon substrates are inexpensive, have good thermal conductivity, and are relatively easy to fabricate in large sizes.

[0037] Optionally, such as Figure 1 As shown, the silicon atom barrier layer 20 includes a first sublayer 21, a second sublayer 22, and a third sublayer 23 stacked sequentially.

[0038] The first sublayer 21 includes an AlN layer, the second sublayer 22 includes a Mg-doped AlN layer, and the third sublayer 23 includes a Mg-doped AlN layer. x In y Ga (1-x-y) N layers, where 0.1 < x < 0.5, 0 < y < 0.2.

[0039] In the above implementation, the first sublayer 21 can provide AlN crystal nuclei; the second sublayer 22 is a Mg-doped AlN layer, which can form a dense thin film to block Si atoms; the third sublayer 23 is a Mg-doped AlN layer. x In y Ga (1-x-y) The N layer can generate activated holes that consume Si electrons, reducing the probability of Si atoms diffusing into the subsequent epitaxial layer 30.

[0040] Meanwhile, Mg-doped Al x In y Ga (1-x-y) In the N layer, In atoms can be trapped and segregated by the stress field around the dislocation or defect center, creating a mask for the dislocation or defect. This can prevent Ga atoms from migrating to the monolayer to form a smooth surface, enhance three-dimensional growth, reduce dislocation or defect density, and improve problems such as large warpage and easy cracking.

[0041] Optionally, the thickness of the first sublayer 21 is 5 nm to 50 nm. For example, the thickness of the first sublayer 21 is 20 nm.

[0042] By setting the thickness of the first sublayer 21 within the above range, it is possible to avoid the first sublayer 21 being too thin, thus failing to provide AlN crystal nuclei; it is also possible to avoid the first sublayer 21 being too thick, thus increasing the preparation cost.

[0043] Optionally, the thickness of the second sublayer 22 is from 10 nm to 100 nm. For example, the thickness of the second sublayer 22 is 50 nm.

[0044] By limiting the thickness of the second sublayer 22 within the above range, a dense thin film layer of sufficient thickness can be formed, thereby ensuring the blocking effect of the second sublayer 22 on Si atoms.

[0045] For example, the Mg doping concentration of the second sublayer 22 is 1×10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3 For example, the Mg doping concentration of the second sublayer 22 is 2 × 10⁻⁶. 17 cm -3 .

[0046] By controlling the Mg doping concentration of the AlN layer within the above range, it is possible to avoid the AlN layer being set too low and thus failing to block Si atoms; it is also possible to avoid the AlN layer being set too high and thus increasing the manufacturing cost.

[0047] Optionally, the thickness of the third sublayer 23 is 100 nm to 200 nm. For example, the thickness of the third sublayer 23 is 150 nm.

[0048] By limiting the thickness of the third sublayer 23 within the aforementioned range, a sufficiently thick Mg-doped Al layer can be formed. x In y Ga (1-x-y) N-layer, fully utilizing Mg-doped Al x In y Ga (1-x-y) The N layer can generate activated holes that consume Si electrons, thereby reducing the probability of Si atoms diffusing into the subsequent epitaxial layer 30.

[0049] For example, the Mg doping concentration of the third sublayer 23 is 1×10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3For example, the Mg doping concentration of the third sublayer 23 is 3 × 10⁻⁶. 17 cm -3 .

[0050] By controlling Al x In y Ga (1-x-y) Within the above-mentioned range, the Mg doping concentration in the N-layer can avoid Al x In y Ga (1-x-y) If the Mg doping concentration in the N layer is set too low, it will not be able to generate activated holes that consume Si electrons; it can also avoid Al x In y Ga (1-x-y) Setting the Mg doping concentration in the N layer too high increases the manufacturing cost.

[0051] Optionally, such as Figure 1 As shown, the epitaxial layer 30 includes an AlGaN buffer layer 31 stacked on the silicon atom barrier layer 20, wherein the mass percentage of Al in the AlGaN buffer layer 31 is 10% to 70%.

[0052] The mass percentage of Al in the AlGaN buffer layer 31 can be 30%.

[0053] In the above implementation, the AlGaN buffer layer 31 can be first grown in three dimensions and then gradually transitioned to two-dimensional growth to reduce dislocation density and improve crystal quality.

[0054] Optionally, the thickness of the AlGaN buffer layer 31 is from 100 nm to 1500 nm. For example, the thickness of the AlGaN buffer layer 31 can be 1000 nm.

[0055] By setting the thickness of the AlGaN buffer layer 31 within the above range, it is possible to avoid the AlGaN buffer layer 31 being too thin, which would reduce the crystal quality of the epitaxial layer 30 grown on the thinner AlGaN buffer layer 31.

[0056] Optionally, such as Figure 1 As shown, the epitaxial layer 30 includes an AlGaN high-resistivity layer 32, a GaN channel layer 33, an AlGaN barrier layer 34, and a GaN cap layer 35, which are sequentially stacked on the silicon atom barrier layer 20.

[0057] For example, the thickness of the AlGaN high-resistivity layer 32 is from 100 nm to 1500 nm. For instance, the thickness of the AlGaN high-resistivity layer 32 can be 800 nm.

[0058] For example, the thickness of the GaN channel layer 33 is from 50 nm to 500 nm. For instance, the thickness of the GaN channel layer 33 can be 200 nm.

[0059] For example, the thickness of the AlGaN barrier layer 34 is from 10 nm to 100 nm. For instance, the thickness of the AlGaN barrier layer 34 can be 80 nm.

[0060] For example, the thickness of the GaN cap layer 35 is from 10 nm to 1000 nm. For instance, the thickness of the GaN cap layer 35 can be 500 nm.

[0061] Figure 2 This is a flowchart illustrating a method for fabricating an epitaxial structure of a high electron mobility transistor according to an embodiment of this disclosure. This method is used to fabricate... Figure 1 The extensional structure shown. For example... Figure 2 As shown, the preparation method includes:

[0062] S11: Provide a substrate 10.

[0063] S12: A silicon atom barrier layer 20 is formed on the substrate 10.

[0064] S13: An epitaxial layer 30 is formed on the silicon atom barrier layer 20.

[0065] The silicon atom barrier layer 20 is used to prevent silicon atoms in the substrate 10 from diffusing into the epitaxial layer 30.

[0066] The epitaxial structure prepared by this method has a silicon atom barrier layer 20 between the substrate 10 and the epitaxial layer 30. The silicon atom barrier layer 20 prevents silicon atoms in the substrate 10 from diffusing into the epitaxial layer 30 under high temperature conditions. This improves the problem of silicon atoms easily diffusing from the substrate 10 to the epitaxial layer 30, thereby improving the crystal quality of the epitaxial layer 30 and the reliability of HEMT devices.

[0067] In step S11, the substrate 10 can be a sapphire substrate or a silicon substrate. The substrate 10 can be a flat substrate or a patterned substrate.

[0068] As an example, in this embodiment of the disclosure, substrate 10 is a silicon substrate. Silicon substrates are inexpensive, have good thermal conductivity, and are relatively easy to fabricate in large sizes.

[0069] Step S11 may also include performing a high-temperature annealing treatment on the substrate 10.

[0070] Annealing methods may include: introducing hydrogen gas into the reaction chamber of an MOCVD (Metal-organic Chemical Vapor Deposition) device and treating the substrate at high temperature for 1 to 10 minutes under a hydrogen atmosphere.

[0071] The reaction chamber temperature is between 1000℃ and 1100℃, and the reaction chamber pressure is controlled between 100 torr and 500 torr.

[0072] The formation of the silicon atom barrier layer 20 in step S12 may include: sequentially forming a first sublayer 21, a second sublayer 22 and a third sublayer 23 on the substrate 10.

[0073] The first sublayer 21 includes an AlN layer, the second sublayer 22 includes a Mg-doped AlN layer, and the third sublayer 23 includes a Mg-doped AlN layer. x In y Ga (1-x-y) N layers, where 0.1 < x < 0.5, 0 < y < 0.2.

[0074] In the above implementation, the first sublayer 21 can provide AlN crystal nuclei; the second sublayer 22 is a Mg-doped AlN layer, which can form a dense thin film to block Si atoms; the third sublayer 23 is a Mg-doped AlN layer. x In y Ga (1-x-y) The N layer can generate activated holes that consume Si electrons, reducing the probability of Si atoms diffusing into the subsequent epitaxial layer 30.

[0075] Meanwhile, Mg-doped Al x In y Ga (1-x-y) In the N layer, In atoms can be trapped and segregated by the stress field around the dislocation or defect center, creating a mask for the dislocation or defect. This can prevent Ga atoms from migrating to the monolayer to form a smooth surface, enhance three-dimensional growth, reduce dislocation or defect density, and improve problems such as large warpage and easy cracking.

[0076] During the growth of the first sublayer 21, the growth temperature was 800℃ to 900℃, the growth pressure was 25 Torr to 100 Torr, and the growth atmosphere was pure nitrogen.

[0077] For example, the thickness of the first sublayer 21 can be from 5 nm to 50 nm.

[0078] By setting the thickness of the first sublayer 21 within the above range, it is possible to avoid the first sublayer 21 being too thin, thus failing to provide AlN crystal nuclei; it is also possible to avoid the first sublayer 21 being too thick, thus increasing the preparation cost.

[0079] When growing the second sublayer 22, the growth temperature was 850℃ to 1000℃, the growth pressure was 25 Torr to 100 Torr, and the growth atmosphere was pure nitrogen.

[0080] For example, the thickness of the second sublayer 22 can be from 10 nm to 100 nm.

[0081] By limiting the thickness of the second sublayer 22 within the above range, a dense thin film layer of sufficient thickness can be formed, thereby ensuring the blocking effect of the second sublayer 22 on Si atoms.

[0082] For example, the Mg doping concentration of the second sublayer 22 is 1×10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3 For example, the Mg doping concentration of the second sublayer 22 is 2 × 10⁻⁶. 17 cm -3 .

[0083] By controlling the Mg doping concentration of the AlN layer within the above range, it is possible to avoid the AlN layer being set too low and thus failing to block Si atoms; it is also possible to avoid the AlN layer being set too high and thus increasing the manufacturing cost.

[0084] When growing the third sublayer 23, the growth temperature was 950℃ to 1050℃, the growth pressure was 25 Torr to 100 Torr, and the growth atmosphere was pure nitrogen.

[0085] For example, the thickness of the third sublayer 23 can be from 100 nm to 200 nm.

[0086] By limiting the thickness of the third sublayer 23 within the aforementioned range, a sufficiently thick Mg-doped Al layer can be formed. x In y Ga (1-x-y) N-layer, fully utilizing Mg-doped Al x In y Ga (1-x-y) The N layer can generate activated holes that consume Si electrons, thereby reducing the probability of Si atoms diffusing into the subsequent epitaxial layer 30.

[0087] For example, the Mg doping concentration of the third sublayer 23 is 1×10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 For example, the Mg doping concentration of the third sublayer 23 is 3 × 10⁻⁶. 17 cm -3 .

[0088] By controlling Al x In y Ga (1-x-y) Within the above-mentioned range, the Mg doping concentration in the N-layer can avoid Al x Iny Ga (1-x-y) If the Mg doping concentration in the N layer is set too low, it will not be able to generate activated holes that consume Si electrons; it can also avoid Al x In y Ga (1-x-y) Setting the Mg doping concentration in the N layer too high increases the manufacturing cost.

[0089] In this embodiment of the disclosure, the epitaxial layer 30 may include an AlGaN buffer layer 31, an AlGaN high-resistivity layer 32, a GaN channel layer 33, an AlGaN barrier layer 34, and a GaN cap layer 35 sequentially stacked on the silicon atom barrier layer 20.

[0090] The preparation method of epitaxial layer 30 may include the following steps:

[0091] The first step is to form an AlGaN buffer layer 31.

[0092] The specific preparation process may include: under a pure nitrogen atmosphere, the pressure in the reaction chamber is controlled at 50 torr to 200 torr, the low temperature range of the growth temperature is 900℃ to 1000℃, and the high temperature range of the growth temperature is 1000℃ to 1150℃.

[0093] In the AlGaN buffer layer 31, the mass percentage of Al is 10% to 70%.

[0094] The AlGaN buffer layer 31 can be first grown in three dimensions and then gradually transitioned to two-dimensional growth to reduce dislocation density and improve crystal quality.

[0095] For example, the thickness of the AlGaN buffer layer 31 is from 100 nm to 1500 nm. For example, the thickness of the AlGaN buffer layer 31 can be 1000 nm.

[0096] By setting the thickness of the AlGaN buffer layer 31 within the above range, it is possible to avoid the AlGaN buffer layer 31 being too thin, which would reduce the crystal quality of the epitaxial layer 30 grown on the thinner AlGaN buffer layer 31.

[0097] The second step is to form an AlGaN high-resistivity layer 32.

[0098] The specific preparation process may include: under a pure nitrogen atmosphere, the reaction chamber pressure is controlled at 50 to 100 torr, the growth thickness is 100 nm to 1500 nm, and the growth temperature ranges from 950 °C to 1100 °C.

[0099] In the AlGaN high-resistivity layer 32, the mass percentage of Al is 30% to 70%.

[0100] For example, the thickness of the AlGaN high-resistivity layer 32 is from 100 nm to 1500 nm. For instance, the thickness of the AlGaN high-resistivity layer 32 can be 800 nm.

[0101] The third step is to form the GaN channel layer 33.

[0102] The specific preparation process may include: under a mixed atmosphere of nitrogen and hydrogen, the pressure in the reaction chamber is controlled at 100 torr to 500 torr, the growth thickness is 50 nm to 500 nm, and the growth temperature ranges from 1000℃ to 1200℃.

[0103] For example, the thickness of the AlGaN high-resistivity layer 32 is from 50 nm to 500 nm. For instance, the thickness of the GaN channel layer 33 can be 200 nm.

[0104] The fourth step is to form an AlGaN barrier layer 34.

[0105] The specific preparation process may include: under a pure nitrogen atmosphere, the pressure in the reaction chamber is controlled at 50 to 100 torr, the growth thickness is 10 nm to 100 nm, and the growth temperature ranges from 950 °C to 1000 °C.

[0106] In AlGaN barrier layer 34, the mass percentage of Al ranges from 10% to 70%.

[0107] For example, the thickness of the AlGaN barrier layer 34 is from 10 nm to 100 nm. For instance, the thickness of the AlGaN barrier layer 34 can be 80 nm.

[0108] The fifth step is to form the GaN cap layer 35.

[0109] The specific preparation process may include: under a mixed atmosphere of nitrogen and hydrogen, the pressure in the reaction chamber is controlled at 100 torr to 500 torr, the growth thickness is 10 nm to 1000 nm, and the growth temperature ranges from 1000℃ to 1200℃.

[0110] For example, the thickness of the GaN cap layer 35 is from 10 nm to 1000 nm. For instance, the thickness of the GaN cap layer 35 can be 500 nm.

[0111] After step S13, the preparation method may further include annealing the epitaxial structure.

[0112] After epitaxial growth is completed, the temperature of the reaction chamber is lowered to 550°C to 750°C and annealed in an N2 atmosphere for 5 to 15 minutes. Then, it is gradually lowered to room temperature. Subsequently, the chip is fabricated through cleaning, deposition, photolithography and etching processes.

[0113] In specific implementation, embodiments of this disclosure may use high-purity H2 and / or N2 as carrier gas, TEGa or TMGa as Ga source, TMIn as In source, SiH4 as n-type dopant, TMAl as aluminum source, ammonia as N source, and Cp2Mg as p-type dopant.

[0114] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An epitaxial structure, characterized in that, The epitaxial structure includes a substrate (10), a silicon atom barrier layer (20), and an epitaxial layer (30). The silicon atom barrier layer (20) and the epitaxial layer (30) are stacked sequentially on the substrate (10). The silicon atom barrier layer (20) is used to block silicon atoms in the substrate (10) from diffusing into the epitaxial layer (30). The silicon atom barrier layer (20) includes a first sublayer (21), a second sublayer (22) and a third sublayer (23) stacked sequentially. The first sublayer (21) comprises an AlN layer, the second sublayer (22) comprises a Mg-doped AlN layer, and the third sublayer (23) comprises a Mg-doped AlN layer. x In y Ga （1-x-y） N layers, wherein 0.1 < x < 0.5, 0 < y < 0.2, the thickness of the first sublayer (21) is 5 nm to 50 nm, the thickness of the second sublayer (22) is 10 nm to 100 nm, the thickness of the third sublayer (23) is 100 nm to 200 nm, and the Mg doping concentration of the second sublayer (22) is 1 × 10⁻⁶. 17 cm -3 Up to 1×10 18 cm -3 The Mg doping concentration of the third sublayer (23) is 1×10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 .

2. The epitaxial structure according to claim 1, characterized in that, The epitaxial layer (30) includes an AlGaN buffer layer (31) stacked on the silicon atom barrier layer (20), wherein the mass percentage of Al in the AlGaN buffer layer (31) is 10% to 70%.

3. The epitaxial structure according to claim 2, characterized in that, The thickness of the AlGaN buffer layer (31) is 100 nm to 1500 nm.

4. The epitaxial structure according to claim 1, characterized in that, The epitaxial layer (30) includes an AlGaN high-resistivity layer (32), a GaN channel layer (33), an AlGaN barrier layer (34) and a GaN cap layer (35) sequentially stacked on the silicon atom barrier layer (20).

5. A method for preparing an epitaxial structure, characterized in that, The preparation method is used to prepare the epitaxial structure as described in any one of claims 1 to 4, comprising: Provide a substrate; A silicon atom barrier layer is formed on the substrate; An epitaxial layer is formed on the silicon atom barrier layer, the silicon atom barrier layer being used to prevent silicon atoms in the substrate from diffusing into the epitaxial layer.

6. The preparation method according to claim 5, characterized in that, The formation of the silicon atom barrier layer on the substrate includes: A first sublayer, a second sublayer, and a third sublayer are sequentially formed on the substrate. The first sublayer comprises an AlN layer, the second sublayer comprises a Mg-doped AlN layer, and the third sublayer comprises a Mg-doped AlN layer. x In y Ga （1-x-y） N layers, where 0.1 < x < 0.5, 0 < y < 0.

2.

7. The preparation method according to claim 6, characterized in that, During the growth of the first sublayer, the growth temperature is 800℃ to 900℃, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere. During the growth of the second sublayer, the growth temperature is 850°C to 1000°C, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere. During the growth of the third sublayer, the growth temperature is 950°C to 1050°C, the growth pressure is 25 Torr to 100 Torr, and the growth atmosphere is a pure nitrogen atmosphere.

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