Communication method and system based on high-order LDPC long code

Abstract

The application discloses a communication method and system based on high-order LDPC long code, and the communication method based on high-order LDPC long code is applied to a communication system, the communication system comprises a sending end and a receiving end, and the communication method based on high-order LDPC long code comprises the following steps: constructing a high-order LDPC long code check matrix. Encoding is carried out based on the high-order LDPC long code check matrix, and a high-order LDPC long code is generated. The sending end sends the high-order LDPC long code to the receiving end. The receiving end receives the high-order LDPC long code. Decoding is carried out on the high-order LDPC long code, and a decision bit sequence is generated. Therefore, the communication method based on high-order LDPC long code improves coding gain, anti-deletion gain, and reduces the loss of soft information extraction when high-order modulation or space-time coding is cascaded.

Description

Technical Field

[0001] This invention relates to the field of channel coding technology, and in particular to a communication method and system based on high-order LDPC long codes. Background Technology

[0002] In 1962, RG Gallager creatively proposed the concept of LDPC (Low Density Parity Check) codes, but it was shelved for a long time due to the limitations of hardware conditions at the time. Inspired by Turbo codes[2], in 1995, DJC MacKay explored the value of LDPC codes in depth, constructed long codes and adopted iterative decoding to obtain extremely high coding gain. Although Turbo codes and Polar codes compete strongly in error correction capability, LDPC codes are the best channel coding scheme that balances high reliability and low latency. LDPC codes have been applied to IEEE 802.16E, DVB-S2 and 5G standards and are currently the most popular channel coding.

[0003] Higher-order channel coding possesses stronger resistance to random noise and burst interference, and can reduce the loss of soft information when concatenating higher-order modulation and space-time coding, making it an important candidate for future channel coding. Higher-order LDPC codes have already been successfully applied in the BeiDou satellite navigation system. However, research on higher-order LDPC codes has mainly focused on short to medium-length codes resistant to random noise; their error correction capabilities are insufficient compared to second-order LDPC long codes, and their potential for resisting burst interference remains to be developed. Currently, there is a need for effective construction and encoding / decoding methods for higher-order LDPC long codes, especially codeword structures with strong resistance to burst interference.

[0004] The channel coding used in the BeiDou satellite navigation system is a typical medium-length high-order LDPC code. It is obtained by randomly replacing the non-zero elements of the entire second-order parity-check matrix with non-zero elements of a high-order finite field, thus producing a high-order LDPC code with full row rank. Due to its relatively short code length, there is still considerable room for improvement in the coding gain.

[0005] Both IEEE 802.16E and 5G NR use second-order LDPC long codes, with the parity-check matrix generated by semi-random design, and the extended parity-check matrix generated by the spread factor. The LDPC codes in the standard need to cover various code lengths and rates, and are not optimal for any specific code length or rate. In engineering, specific code lengths and rates are often required, which the standard cannot perfectly match, leading to wasted resources. Basic knowledge of coding theory tells us that using higher-order coding can further improve the coding gain.

[0006] The basic idea behind current high-order LDPC long codes is to maintain the fixed structure of the second-order parity-check matrix in existing standards, while randomly replacing the non-zero elements of the randomized design part with non-zero elements of a higher-order finite field, and appropriately reducing the spread factor to keep the overall code length constant. This design also suffers from limitations in code length and code rate types, and the fixed structure may also be randomized during high-order encoding.

[0007] Furthermore, existing high-order decoding algorithms are all symbol-by-symbol operations, making it difficult to directly achieve parallelism at the encoding order and at the expansion factor level.

[0008] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to provide a communication method and system based on high-order LDPC long codes, which improves coding gain and anti-deletion gain, and reduces the loss of soft information extraction when concatenated with high-order modulation or space-time coding.

[0010] To achieve the above objectives, in a first aspect, the present invention provides a communication method and system based on high-order LDPC long codes. The communication method based on high-order LDPC long codes is applied to a communication system, which includes a transmitter and a receiver. The communication method based on high-order LDPC long codes includes: constructing a high-order LDPC long code parity-check matrix; encoding based on the high-order LDPC long code parity-check matrix to generate a high-order LDPC long code; transmitting the high-order LDPC long code to the receiver; receiving the high-order LDPC long code; and decoding the high-order LDPC long code to generate a decision bit sequence.

[0011] In one embodiment of the present invention, constructing a high-order LDPC long code parity-check matrix at the transmitting end specifically includes: constructing a second-order basis matrix at the transmitting end; expanding the second-order basis matrix to generate a high-order parity-check matrix; determining the expansion factor, generating the expansion factor matrix, and generating the long code; and generating a high-order LDPC long code parity-check matrix based on the high-order parity-check matrix and the long code.

[0012] In one embodiment of the present invention, the construction of the second-order basis matrix at the transmitting end is specifically as follows: the second-order basis matrix is ​​represented as H0 = [A0, B0]. A0 and B0 are M0×K0 matrices and M0×M0 square matrices, respectively, and the submatrix B0 has a double diagonal structure. Let K0 = N0 - M0, and the M0×K0 matrix A0 is constructed using a random method based on the degree distribution of the symbol nodes. The M0×M0 square matrix B0 is the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, and the non-zero elements are set to... To ensure that the square matrix B0 is full rank and m′0∈{1,...,M0-2}, the submatrix B0 consists of its main diagonal elements and elements. Confirmed. Extending the second-order basis matrix to generate the higher-order parity-check matrix specifically involves: increasing the encoding order of the second-order basis matrix H0 to generate an M0×N0 higher-order parity-check matrix H. H To determine the expansion factor, generate the expansion factor matrix, and generate the long code, specifically: determine the expansion factor Z, and generate an M0×N0 expansion factor matrix H. Z To generate long code H Z The generation of the high-order LDPC long code parity matrix based on the high-order parity check matrix and the long code is specifically as follows: Based on the high-order parity check matrix H... H and long code H Z Generate a high-order LDPC long code check matrix H.

[0013] In one embodiment of the present invention, the transmitting end encodes based on a high-order LDPC long code parity-check matrix to generate a high-order LDPC long code. Specifically, this includes: performing calculations on the high-order LDPC long code parity-check matrix using a preset calculation method to generate the high-order LDPC long code. The preset calculation method includes column vector summation, inversion of a weighted cyclic shift matrix, the product of a weighted cyclic shift matrix and column vectors, and the product of two weighted cyclic shift matrices.

[0014] In one embodiment of the present invention, the receiving end decodes the high-order LDPC long code to generate a decision bit sequence, specifically including:

[0015] The receiver decodes the high-order LDPC long code using a block decoding algorithm based on a cyclic shift matrix to generate a decision bit sequence;

[0016] Specifically, the receiving end decodes the high-order LDPC long code using a block decoding algorithm based on a cyclic shift matrix to generate a decision bit sequence, including:

[0017] Step 1, Initialization:

[0018] The second step is to update the symbol node metric:

[0019]

[0020] The third step is to update the verification node metrics:

[0021]

[0022] Fourth step: Repeat steps two and three until the maximum number of iterations is reached, and calculate the log-likelihood value:

[0023]

[0024] The decision symbol sequence is determined by the row order corresponding to the maximum value in each column, using the log-likelihood value. This generates a decision bit sequence.

[0025] Secondly, this invention provides a method for transmitting high-order LDPC long codes, applied to a communication system. The communication system includes a transmitting end, and the method includes: constructing a high-order LDPC long code parity-check matrix; encoding based on the high-order LDPC long code parity-check matrix to generate a high-order LDPC long code; and transmitting the high-order LDPC long code. A receiving end, receiving the high-order LDPC long code, decodes the high-order LDPC long code to generate a decision bit sequence.

[0026] Thirdly, this invention provides a method for receiving high-order LDPC long codes, applied to a communication system. The communication system includes a receiving end. The method comprises: receiving a high-order LDPC long code; decoding the high-order LDPC long code to generate a decision bit sequence. The high-order LDPC long code is generated by the transmitting end based on a high-order LDPC long code parity-check matrix, and the high-order LDPC long code parity-check matrix is ​​constructed by the transmitting end.

[0027] Fourthly, the present invention provides a communication system based on high-order LDPC long codes, comprising: a transmitter and a receiver. The transmitter includes a channel coding module and a spatiotemporal mapping module connected by communication. The receiver is connected to the transmitter by communication, and the receiver includes a spatiotemporal detection module and a channel decoding module connected by communication.

[0028] Fifthly, the present invention provides a communication device, including a communication interface and a processor, the processor being configured to execute computer programs or instructions, causing the communication device to perform the communication method as described above.

[0029] In a sixth aspect, the present invention provides a computer-readable storage medium including a computer program and instructions, which, when executed on a computer, cause the computer to perform the communication method described above.

[0030] Compared with the prior art, the communication method and system based on high-order LDPC long codes according to the present invention have the following advantages:

[0031] 1. An extended high-order LDPC long code is constructed using an indirect semi-random method, which has higher coding gain and anti-deletion gain;

[0032] 2. The error correction performance of second-order LDPC long codes, represented by IEEE 802.16E and 5G NR, still has room for improvement. This invention fills this gap by utilizing the gain of higher-order coding.

[0033] 3. It can better adapt to the code length and code rate in practical applications;

[0034] 4. It reduces the loss of soft information when concatenated with higher-order modulation or space-time coding. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a communication method based on a high-order LDPC long code according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the structure of the LDPC check matrix in a communication method based on high-order LDPC long codes according to an embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of the structure of submatrix B in a communication method based on high-order LDPC long codes according to an embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram of the architecture of a communication system based on high-order LDPC long codes according to an embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram illustrating the concatenation of channel coding and space-time transmission in a communication system based on high-order LDPC long codes according to an embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of the bit error rate performance of BPSK modulation and 1 / 2 code rate high-order LDPC code in an AWGN channel according to an embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of the error rate performance of BPSK modulation and 1 / 2 code rate high-order LDPC code in an AWGN channel of a communication method based on high-order LDPC long code according to an embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram of the bit error rate performance of Alamouti STBC, QPSK modulation, and 1 / 2 code rate high-order LDPC code in a Rayleigh flat fading channel according to an embodiment of the present invention.

[0043] Figure 9 This is a schematic diagram of the error rate performance of Alamouti STBC, QPSK modulation, and 1 / 2 code rate high-order LDPC code in a Rayleigh flat fading channel according to an embodiment of the present invention.

[0044] Figure 10This is a schematic diagram of the structure of a communication device according to an embodiment of the present invention.

[0045] Figure 11 This is a schematic diagram of the structure of the extended matrix of the LDPC parity check matrix in IEEE 802.16E according to an embodiment of the present invention.

[0046] Figure 12 This is a schematic diagram of the structure of a higher-order basis matrix of a 4th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0047] Figure 13 This is a schematic diagram of the structure of an extended matrix of a 4th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0048] Figure 14 This is a schematic diagram of the structure of a higher-order basis matrix of an 8th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0049] Figure 15 This is a schematic diagram of the structure of an extended matrix of an 8th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0050] Figure 16 This is a schematic diagram of the structure of a higher-order basis matrix of a 16th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0051] Figure 17 This is a schematic diagram of the structure of an extended matrix of a 16th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0052] Figure 18 This is a schematic diagram of the structure of a higher-order basis matrix of a 64th-order LDPC parity-check matrix according to an embodiment of the present invention.

[0053] Figure 19 This is a schematic diagram of the structure of an extended matrix of a 64th-order LDPC parity-check matrix according to an embodiment of the present invention. Detailed Implementation

[0054] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0055] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0056] Figure 1 This is a flowchart illustrating a communication method based on a high-order LDPC long code according to an embodiment of the present invention. Figure 2This is a schematic diagram of the structure of the LDPC check matrix in a communication method based on high-order LDPC long codes according to an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of submatrix B in a communication method based on high-order LDPC long codes according to an embodiment of the present invention.

[0057] like Figures 1 to 3 As shown, in a first aspect, according to a preferred embodiment of the present invention, a communication method and system based on a high-order LDPC long code are provided. The communication method based on the high-order LDPC long code is applied to a communication system, which includes a transmitter 100 and a receiver 2. The communication method based on the high-order LDPC long code includes: Step S1, constructing a high-order LDPC long code parity check matrix; Step S2, encoding based on the high-order LDPC long code parity check matrix to generate a high-order LDPC long code; Step S3, transmitting the high-order LDPC long code from the transmitter 100 to the receiver 2; Step S4, receiving the high-order LDPC long code; Step S5, decoding the high-order LDPC long code to generate a decision bit sequence.

[0058] Specifically, this invention employs a semi-random method to construct the extended parity-check matrix of a high-order LDPC long code. When designing the second-order parity-check base matrix, a fixed part is determined, and a random part is constructed based on this fixed part using the PEG method. When generating the high-order parity-check base matrix, for the random part, the non-zero elements of the random part of the second-order base matrix are directly and randomly replaced with field elements in {1,...,L}; while for the fixed square matrix, the main diagonal elements of the identity matrix are directly and randomly replaced with field elements in {1,...,L}, the main diagonal elements are cyclically shifted one position upwards and added to the previous diagonal element, and the middle element of the first column is randomly replaced with a field element in {1,...,L}.

[0059] Specifically, when generating the higher-order extended parity-check matrix, the position corresponding to the zero element of the parity-check base matrix is ​​set to -1; for the random part, the non-zero elements of the random part of the second-order base matrix are directly and randomly replaced with integers in {0, ..., Z-1}; for the fixed square matrix, the main diagonal elements of the identity matrix are directly and randomly replaced with integers in {0, ..., Z-1}, the main diagonal elements are cyclically shifted one position upwards and added to the previous diagonal matrix, and the middle element of the first column is randomly replaced with integers in {0, ..., Z-1}.

[0060] Specifically, the simplified encoding method suitable for this invention mainly involves: column vector summation, inversion of weighted cyclic shift matrix, product of weighted cyclic shift matrix and column vector, and product of two weighted cyclic shift matrices; and the parallel decoding method suitable for this invention mainly involves: group parallelism and encoding order parallelism of the high-order Max-Log-BP algorithm.

[0061] In one embodiment of the present invention, constructing a high-order LDPC long code parity-check matrix at the transmitting end 100 specifically includes: constructing a second-order basis matrix at the transmitting end 100; expanding the second-order basis matrix to generate a high-order parity-check matrix; determining the expansion factor, generating the expansion factor matrix, and generating the long code; and generating a high-order LDPC long code parity-check matrix based on the high-order parity-check matrix and the long code.

[0062] In one embodiment of the present invention, the construction of the second-order basis matrix at the transmitting end 100 is specifically as follows: the second-order basis matrix is ​​represented as H0 = [A0, B0]. A0 and B0 are M0×K0 matrices and M0×M0 square matrices, respectively, and the submatrix B0 has a double diagonal structure. Let K0 = N0 - M0, and the M0×K0 matrix A0 is constructed using a random method based on the degree distribution of the symbol nodes. The M0×M0 square matrix B0 is the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, and the non-zero elements are set to... To ensure that the square matrix B0 is full rank and m′0∈{1,...,M0-2}, the submatrix B0 consists of its main diagonal elements and elements. Confirmed. Extending the second-order basis matrix to generate the higher-order parity-check matrix specifically involves: increasing the encoding order of the second-order basis matrix H0 to generate an M0×N0 higher-order parity-check matrix H. H To determine the expansion factor, generate the expansion factor matrix, and generate the long code, specifically: determine the expansion factor Z, and generate an M0×N0 expansion factor matrix H. Z To generate long code H Z The generation of the high-order LDPC long code parity matrix based on the high-order parity check matrix and the long code is specifically as follows: Based on the high-order parity check matrix H... H and long code H Z Generate a high-order LDPC long code check matrix H.

[0063] In one embodiment of the present invention, the transmitting end 100 encodes based on a high-order LDPC long code parity-check matrix to generate a high-order LDPC long code. Specifically, this includes: performing calculations on the high-order LDPC long code parity-check matrix using a preset calculation method to generate the high-order LDPC long code. The preset calculation method includes column vector summation, inversion of a weighted cyclic shift matrix, the product of a weighted cyclic shift matrix and column vectors, and the product of two weighted cyclic shift matrices.

[0064] In one embodiment of the present invention, the receiving end 2 decodes the high-order LDPC long code to generate a decision bit sequence, specifically including:

[0065] Receiver 2 decodes the high-order LDPC long code using a block decoding algorithm based on a cyclic shift matrix to generate a decision bit sequence;

[0066] Specifically, receiver 2 decodes the high-order LDPC long code using a block decoding algorithm based on a cyclic shift matrix, generating a decision bit sequence including:

[0067] Step 1, Initialization:

[0068] The second step is to update the symbol node metric:

[0069]

[0070] The third step is to update the verification node metrics:

[0071]

[0072] Fourth step: Repeat steps two and three until the maximum number of iterations is reached, and calculate the log-likelihood value:

[0073]

[0074] The decision symbol sequence is determined by the row order corresponding to the maximum value in each column, using the log-likelihood value. This generates a decision bit sequence.

[0075] Secondly, according to a preferred embodiment of the present invention, a method for transmitting a high-order LDPC long code is applied to a communication system, the communication system including a transmitter 100, and the method includes: constructing a high-order LDPC long code parity check matrix; encoding based on the high-order LDPC long code parity check matrix to generate a high-order LDPC long code; and transmitting the high-order LDPC long code by the transmitter 100. A receiver 2 receiving the high-order LDPC long code decodes the high-order LDPC long code to generate a decision bit sequence.

[0076] Thirdly, according to a preferred embodiment of the present invention, a method for receiving high-order LDPC long codes is applied to a communication system, the communication system including a receiver 2. The method comprises: receiving a high-order LDPC long code; decoding the high-order LDPC long code to generate a decision bit sequence. The high-order LDPC long code is generated by a transmitter 100 based on a high-order LDPC long code parity check matrix, and the high-order LDPC long code parity check matrix is ​​constructed by the transmitter 100.

[0077] Figure 4 This is a schematic diagram of the architecture of a communication system based on high-order LDPC long codes according to an embodiment of the present invention. Figure 4 As shown, in a fourth aspect, according to a preferred embodiment of the present invention, a communication system based on a high-order LDPC long code includes: a transmitter 100 and a receiver 2. The transmitter 100 includes a channel coding module 101 and a spatiotemporal mapping module 102 connected in communication. The receiver 2 is connected in communication with the transmitter 100, and the receiver 2 includes a spatiotemporal detection module 201 and a channel decoding module 202 connected in communication.

[0078] Figure 10 This is a schematic diagram of the structure of a communication device according to an embodiment of the present invention. Figure 10 As shown, in a fifth aspect, the present invention provides a communication device including a processor 801 and a communication interface 802. The processor 801 is used to execute computer programs or instructions stored in a memory 803, or to read data stored in the memory 803, to perform the methods in the above-described method embodiments. Exemplarily, there may be one or more processors 801. The communication interface 802 is used for receiving and / or transmitting signals. For example, the processor 801 is used to control the communication interface 802 to receive and / or transmit signals.

[0079] For example, such as Figure 10 As shown, the communication device may further include a memory 803 for storing computer programs or instructions and / or data. The memory 803 may be integrated with the processor 801 or may be disposed separately. Alternatively, the communication device may not include the memory 803, and the memory 803 may be located outside the communication device. Exemplarily, there may be one or more memories 803.

[0080] For example, the processor 801, communication interface 802, and memory 803 are interconnected via bus 804; bus 804 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 804 can be divided into address bus, data bus, and control bus, etc. For ease of illustration, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0081] It should be understood that the processor mentioned in the embodiments of this application (such as processor 801) may be a central processing unit (CPU), a network processor (NP), or a combination of CPU and NP. The processor may further include a hardware chip. The aforementioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD). The aforementioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0082] It should also be understood that the memory mentioned in the embodiments of this application (such as memory 803) can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache.

[0083] Sixthly, the present invention provides a computer-readable storage medium, including a computer program and instructions, which, when executed on a computer, cause the computer to perform the communication method described above. The computer-readable storage medium includes various media capable of storing program code, such as a USB flash drive, portable hard drive, ROM, RAM, magnetic disk, or optical disk.

[0084] In practical applications, the communication method and system based on high-order LDPC long codes of this invention, inspired by the IEEE 802.16E standard, proposes a coding and decoding scheme for double-diagonal semi-random high-order LDPC long codes. This mainly includes: constructing a high-order parity-check matrix and an extension factor matrix, designing a corresponding fast coding method, and proposing a high-order block Max-Log-BP decoding algorithm that facilitates parallel processing. Under various conditions, the proposed scheme outperforms IEEE 802.16E in resisting random noise, with more significant gains in resisting burst interference. In particular, for code rates and code lengths not covered by existing standards, the proposed scheme allows for flexible design as needed. The semi-random design, fast coding, and decoding methods for high-order LDPC long codes proposed in this invention improve coding gain and anti-deletion gain, and reduce the loss of soft information extraction when concatenated with high-order modulation or space-time coding.

[0085] Figure 5 This is a schematic diagram illustrating the concatenation of channel coding and space-time transmission in a communication system based on high-order LDPC long codes according to an embodiment of the present invention. Figure 5 This is the equivalent baseband model of a MIMO (Multiple Input Multiple Output) coded modulation system, mainly consisting of five parts: channel coding, space-time mapping, MIMO channel, space-time detection, and channel decoding. At the transmitter (transmitter 100), the source symbol sequence s is channel-coded to generate codeword c, and after space-time mapping, a signal X suitable for MIMO channel transmission is generated. After multiplicative fading and additive noise interference, signal X is received at receiver 2 as signal Y. After space-time detection, a likelihood ratio Λ is generated, and after channel decoding, a decision bit sequence is obtained. Space-time mapping can be considered as the process of transforming baseband symbols into those suitable for MIMO channel transmission, while space-time detection is the inverse process.

[0086] Assume the data rate is R bits / symbol, and the number of transmit and receive antennas and the signal length are M respectively. A N A and T, x t，m and y t，n Let m represent the transmitted signal from transmitting antenna m and the received signal from receiving antenna n at time t, respectively, where t ∈ {1, ..., T} and m. A ∈}1,...,M A}、n A ∈{1,...,N A The average signal-to-noise ratio at receiver 2 is expressed as ρ, therefore, T×M A The transmitted signal matrix X and T×N A The relationship between the received signal matrices Y is as follows:

[0087]

[0088] Where G is M A ×N A The fading coefficient matrix W is T×N. A The additive noise matrix has Let L be the number of signals in the transmitted signal constellation. Then any transmitted signal can be represented as X. l , l∈}0,...,L-1}.

[0089] This transmission model has broad applicability, suitable for both AWGN channels and fading channels. Accordingly, matrix X can represent both ordinary signals in a single-antenna system and MIMO signals.

[0090] When receiver 2 knows the CSI, the channel transfer PDF is:

[0091]

[0092] Among them, ||·|| F Let F be the norm of the matrix. The general form of maximum likelihood detection is:

[0093]

[0094] When concatenated with channel coding, the hard decision result of the detection is often not obtained directly. Instead, the soft information corresponding to each signal in the constellation set is extracted. The specific extraction method is described in the decoding algorithm section later.

[0095] Constructing a high-order LDPC long code check matrix

[0096] In practice, easily implemented LDPC codes are often derived from the basis matrix. For second-order LDPC codes, only the extension factor matrix is ​​needed for complete representation; however, for higher-order LDPC codes, a combination of the higher-order parity-check basis matrix and the extension factor matrix is ​​required. Let the coding order L be an integer power of 2, and the higher-order parity-check basis matrix and the extension factor matrix be H, respectively. H and H Z Their sizes are all M0×N0. H H any component in For elements in GF(L). In H Z In, with H H Components corresponding to non-zero elements Let be an integer in {0, ..., Z-1}, and set the other components to -1. The methods for generating higher-order basis matrices and extended matrices are described below.

[0097] Generating the second-order basis matrix: The second-order basis matrix adopts the IEEE 802.16E structure and is represented as H0 = [A0, B0], such as... Figure 2As shown. This structure has the combined advantages of simple implementation and excellent performance. A0 and B0 are M0×K0 matrices and M0×M0 square matrices, respectively. Submatrix B0 has a double diagonal structure, as shown... Figure 3 As shown in the figure, each gray square represents a non-zero GF(L) element.

[0098] Let K0 = N0 - M0. The M0 × K0 matrix A0 can be constructed using a random method based on the degree distribution of the symbolic nodes, often employing the PEG method. The M0 × M0 square matrix B0 is the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, with non-zero elements... To ensure that the square matrix B0 is full rank, where m′0∈}1,...,M0-2}. Submatrix B0 consists of its main diagonal elements and elements... Uniquely certain

[0099] Generating the higher-order basis matrix and the extended matrix: After determining the basis matrix, the coding order needs to be extended to generate an M0×N0 higher-order parity check matrix H. H To achieve higher-order encoding; determine the expansion factor Z, and generate an M0×N0 expansion factor matrix H. Z This is done to obtain the long code. The final high-order LDPC long code parity-check matrix is ​​represented as H.

[0100] In the extension of matrix order, let H H =[A H B H ], where A H and B H The sizes of the matrices are M0×K0 and M0×M0, respectively. An M0×K0 matrix is ​​randomly generated, with its elements drawn from the set of field elements {1, ..., L-1} and following a uniform distribution. This matrix is ​​multiplied digit-wise by A0 to obtain A. H Generate a 1×M0 vector b, whose elements are taken from the set of domain elements {1, ..., L-1} and follow a uniform distribution. Construct a diagonal matrix Diag(b) with b as the diagonal element. Add this diagonal matrix to the result of a one-cycle upward shift, and let... Randomly select from the set of domain elements {1, ..., L-1} to obtain B H .

[0101] In the expansion of matrix size, let H Z =[A Z B Z ], where A Z and B Z The sizes of the matrices are M0×K0 and M0×N0, respectively. An M0×K0 matrix is ​​generated, with all elements being -1. Elements from the set {0, ..., Z-1} are randomly selected from the matrix corresponding to the non-zero elements of A0 to obtain A0. ZGenerate a 1×M0 vector z, whose elements are taken from the set of integers {0, ..., Z-1}. Construct a diagonal matrix Diag(z) with z as its diagonal elements. Add this diagonal matrix to the result of a one-cycle upward shift, and let... Randomly select from the set of integers {0, ..., Z-1}, and set all other elements to -1, thus obtaining B. Z .

[0102] The complete LDPC parity-check matrix H can be obtained from H H With H Z A complete description is given, where the (m0, n0,)th Z×Z submatrix of the parity-check matrix H can be represented as:

[0103] The design process of a high-order LDPC code parity-check matrix can be summarized in the table below:

[0104] Table 1 Design Flow of High-Order LDPC Code Check Matrix

[0105]

[0106] Encoding principle: The block-based design of the LDPC parity-check matrix eliminates the need for matrix generation, Gaussian elimination, and approximate lower triangular processing, greatly simplifying the encoding complexity and significantly improving the practicality of LDPC codes.

[0107] Suppose that the encoded system codeword can be represented as:

[0108] c = [s, p]

[0109] Where s and p are K-dimensional and M-dimensional row vectors, respectively, since the codeword satisfies

[0110] Hc T =0 M×1

[0111] Right now

[0112] As T +Bp T =0 M×1

[0113] Let B consist of m0×m0 Z×Z submatrices, which can be represented as

[0114]

[0115] and

[0116]

[0117] in, It is a 1×Z row vector, 0≤m0≤M0-1.

[0118] Let the check symbol in Let Z be a 1×Z row vector, where 0 ≤ m0 ≤ M0-1. Any subvector... The calculation method is as follows:

[0119]

[0120] Where 0≤m0≤M0-1, and the symbol “\” represents the new set obtained by deleting the elements on the right side of the set to its left.

[0121] Once the check symbol p is determined, the encoding is complete.

[0122] Encoding higher-order LDPC codes involves matrix operations with components being elements of higher-order GF fields, which is too complex to be implemented directly. However, the extended higher-order LDPC long code scheme proposed in this invention can greatly reduce computational complexity by utilizing the second-order equivalence of addition and table lookup for multiplication.

[0123] The higher-order field element operations involved in this invention mainly include the following:

[0124] 1. Summation of column vectors: Transform the higher-order GF field elements in each vector into the corresponding second-order row vectors, add the second-order matrices to be summed modulo 2, and transform each row of the resulting matrix into the corresponding higher-order field elements.

[0125] 2. Inverse of a weighted cyclic shift matrix: A weighted cyclic shift matrix is ​​represented as... Its inverse matrix over the higher-order GF field is GF domain weight coefficients The reverse It can be obtained by looking up a table. The inverse of the identity matrix I Z Move to the right in a circular motion Position, obtained

[0126] 3. Product of a weighted circularly shifted matrix and its column vectors: Circularly shift the column vectors upwards. The resulting vector and weight coefficients The result of multiplication can be obtained by looking up a table.

[0127] 4. Product of two weighted cyclically shifted square matrices: Multiply the higher-order GF field weight coefficients of the two square matrices by looking up a table, and use the resulting product matrix as the weight coefficients. Then, multiply the identity matrix I... Z The sum of the shifts of two shift matrices cyclically shifted to the right is used as the cyclic shift matrix of the product matrix.

[0128] The block-based parallel decoding algorithm for cyclic shift matrices proposed in this invention is based on the conventional high-order Max-Log-BP algorithm. The main improvement is that it processes data in parallel on a per-expansion-factor basis, and further in parallel on a per-encoding-order basis, thereby increasing the decoding speed. For clarity, this section first reviews the conventional high-order Max-Log-BP algorithm, and then proposes a block-based decoding algorithm based on cyclic shift matrices.

[0129] 1. Initialization

[0130] The initial logarithmic measure of time n and constellation signal l is:

[0131]

[0132] To save storage space, the above equation is zeroed out, so that the maximum initial metric value of the L constellation signals at time n is 0. This yields the logarithmic initial metric for constellation signal l at time n.

[0133]

[0134] 2. Update symbol node metrics

[0135] For the parity-check matrix component h m，n and constellation signal X l ,have

[0136]

[0137] For the parity check matrix component h m，n and the q′ corresponding to the constellation set signal l m，n，l Perform zeroing to make its maximum value 0. Then, compare it with the parity check matrix component h. m，n The logarithmic measure of the symbol nodes corresponding to the constellation set signal l can be expressed as:

[0138]

[0139] 3. Update the verification node metrics

[0140] With the components h of the verification matrix m，n The forward and backward components and the logarithm of the probability corresponding to the l-th signal in the constellation set can be expressed as follows:

[0141]

[0142] and

[0143]

[0144] Specifically, initial values ​​are obtained at time 0 and time N-1, respectively.

[0145]

[0146] and

[0147]

[0148] Therefore, with the parity check matrix component h m，n The logarithmic measure of the check nodes corresponding to the constellation set signal l can be expressed as:

[0149]

[0150] 4. Judgment

[0151] Based on the above analysis, at time n, when using the higher-order Max-Log-BP algorithm, the decision result for the transmitted signal is:

[0152]

[0153] Therefore, the judgment symbol can be uniquely obtained.

[0154] Based on the Max-Log-MAP algorithm, this invention proposes a block decoding algorithm suitable for cyclic shift matrices, which is applicable to extended higher-order LDPC codes. The block decoding algorithm uses each element of the basis matrix as a processing unit, processing all Z components of each unit as a whole, theoretically increasing the decoding speed by a factor of Z. Since each component in the codeword corresponds to L likelihood values ​​that can be processed in parallel, the decoding speed can be further increased by a factor of L.

[0155] Let each symbol node metric matrix and check node metric matrix be represented by M0×N0×L Z×Z submatrices respectively:

[0156] and

[0157] Both Q and R are three-dimensional matrices. Let I... T，(z，1) and I T，(z，2) They represent T×T identity matrices I, respectively. T Shift z elements down and to the right. Let Z be a row vector of length Z. ∑ .，t This represents summing the elements of a high-dimensional matrix along its t-th dimension, where max... .，t This means taking the maximum value of the elements in the t-th dimension of a high-dimensional matrix.

[0158] For the (m0, n0)th Z×Z submatrix of the M×N higher-order parity-check matrix H And the symbol l, the symbol node metric update method for group processing is as follows

[0159]

[0160] Determine Q′l Then, it is zeroed out. Therefore, it is compared with the components of the higher-order parity-check matrix. The corresponding group symbol node metric for l can be expressed as:

[0161]

[0162] make

[0163] and

[0164] in,

[0165]

[0166] and

[0167]

[0168] The (m0, n0)th submatrix of the M×N higher-order parity-check matrix H The forward and backward components corresponding to the symbol l, and the logarithm of the probability, can be expressed as follows:

[0169]

[0170] and

[0171]

[0172] Specifically, corresponding to the first and last submatrices of H, respectively, are:

[0173]

[0174] Therefore, the logarithmic measure of the check nodes corresponding to the (m0, n0)th submatrix of the check matrix H and the l-th signal in the constellation set can be expressed in matrix form.

[0175]

[0176] When using a block decoding algorithm based on a cyclic shift matrix, the log-likelihood value of the n0th block and symbol l can be expressed as:

[0177]

[0178] Given the log-likelihood matrix, the decision symbol sequence can be determined by the row number corresponding to the maximum value in each column. The decision bit sequence can then be obtained.

[0179] The block decoding algorithms based on cyclic shift matrices are shown in Table 2 below:

[0180] Table 2

[0181]

[0182] Figure 6 and Figure 7 Error performance of LDPC codes of various orders is presented under BPSK modulation and 1 / 2 code rate conditions in an AWGN channel. The decoding algorithms are all high-order Max-Log-BP. The coding orders are 2... 1 2 2 2 3 2 4 and 2 6 Correspondingly, the sizes of the verification matrices are 1152×2304, 576×1152, 384×768, 288×576, and 192×384, respectively.

[0183] It can be seen that as the signal-to-noise ratio increases, the error rate curve of low-order LDPC codes decreases relatively gently, while the higher the order, the later and steeper the "waterfall region" appears, and correspondingly, the coding gain is also higher. Compared to 2nd-order LDPC codes, the gain of the 64th-order coding scheme is approximately 0.2dB.

[0184] Figure 8 and Figure 9 The error performance of 2nd and 16th order LDPC codes in a Rayleigh flat-fading channel under Alamouti STBC, QPSK modulation, and 1 / 2 code rate conditions is presented. The parity-check matrix is ​​the same as in the previous example. It can be seen that, compared with the 2nd order LDPC code, the 16th order LDPC code has a coding gain of approximately 0.2 dB in both BER and BLER.

[0185] Table 3. Code weight and deletion resistance under noise-free conditions for high-order LDPC codes with a code rate of 1 / 2 and a code length of 2304 bits.

[0186]

[0187] Table 3 presents the codeweights of the high-order LDPC codes with a coderate of 1 / 2 and a codelength of 2304 bits used in this paper. Codewords with an order higher than 2 are converted to second-order codewords before their codeweights are calculated. Table 3 also shows the anti-deletion rate under noise-free conditions, where the packet error rate is below 10%. -5 The higher-order basis matrices and extension matrices corresponding to each encoding order are listed in the appendix.

[0188] It can be seen that, under the same code rate, number of bits, and code length, the higher the coding order, the greater the code weight, and correspondingly, the higher the coding gain. On the other hand, as the coding order increases, the resistance to deletion also increases. For applications resisting deletion interference, the proposed high-order LDPC codes also help improve the deletion resistance rate.

[0189] like Figures 11 to 19As shown, the basis matrix and extended matrix of the parity-check matrix in the simulation are given. A second-order LDPC code can be completely described by the extended parity-check matrix alone, while a higher-order LDPC code requires a combination of the higher-order parity-check basis matrix and the extended parity-check matrix.

[0190] In summary, the communication method and system based on high-order LDPC long codes of the present invention have the following beneficial effects:

[0191] 1. An extended high-order LDPC long code is constructed using an indirect semi-random method, which has higher coding gain and anti-deletion gain;

[0192] 2. Second-order LDPC long codes, represented by IEEE 802.16E and 5G NR, still have room for improvement in error correction performance. This invention fills this gap by utilizing the gain of higher-order coding.

[0193] 3. It can better adapt to the code length and code rate in practical applications;

[0194] 4. It reduces the loss of soft information when concatenated with higher-order modulation or space-time coding.

[0195] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0196] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0197] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0198] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0199] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A communication method based on high-order LDPC long codes, applied to a communication system, the communication system comprising a transmitter and a receiver, characterized in that, The method includes: A high-order LDPC long code check matrix is ​​constructed at the transmitting end; Encoding is performed based on the high-order LDPC long code parity check matrix to generate a high-order LDPC long code. The transmitting end sends the high-order LDPC long code to the receiving end; The receiving end receives the high-order LDPC long code; The higher-order LDPC long code is decoded to generate a decision bit sequence; Specifically, constructing a high-order LDPC long code check matrix at the transmitting end involves: A second-order basis matrix is ​​constructed at the transmitting end; the second-order basis matrix is ​​represented as follows: ;in, and They are respectively Matrix and Square matrix, and submatrices It has a double diagonal structure; phalanx Let be the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, and let the non-zero elements be... To ensure the square formation Full rank; Extend the encoding order of the second-order basis matrix to generate Higher-order parity check matrix ; Determine the expansion factor ,produce Expansion factor matrix To generate long codes; According to the higher-order check matrix The high-order LDPC long code parity matrix is ​​generated using the long code. ; Furthermore, encoding is performed based on the aforementioned high-order LDPC long code parity-check matrix to generate a high-order LDPC long code, including: The higher-order LDPC long code parity matrix is ​​processed using a preset calculation method to generate the higher-order LDPC long code. The preset calculation method includes inverting a weighted cyclic shift matrix, wherein the weighted cyclic shift matrix is ​​composed of the weight coefficients and the cyclic shift matrix, and the inversion of the weighted cyclic shift matrix is ​​accomplished by inverting the weight coefficients and the shift values ​​of the weighted cyclic shift matrix; the preset calculation method also includes column vector summation, the product of the weighted cyclic shift matrix and the column vectors, and the product of two weighted cyclic shift matrices.

2. The communication method based on high-order LDPC long codes as described in claim 1, characterized in that, The receiving end decodes the high-order LDPC long code to generate a decision bit sequence, specifically including: The receiving end decodes the high-order LDPC long code based on a block decoding algorithm using a cyclic shift matrix to generate a decision bit sequence; Specifically, the receiving end decodes the high-order LDPC long code using a block decoding algorithm based on a cyclic shift matrix to generate a decision bit sequence, including: Step 1, Initialization: ; The second step is to update the symbol node metric: ； The third step is to update the verification node metrics: ； Fourth step: Repeat steps two and three until the maximum number of iterations is reached, and calculate the log-likelihood value: ； The decision symbol sequence is determined by the row order corresponding to the maximum value in each column, based on the log-likelihood value. This leads to the generation of a decision bit sequence. .

3. A method for transmitting high-order LDPC long codes, applied to a communication system, the communication system including a transmitting end, characterized in that, The method includes: Construct a high-order LDPC long code check matrix; Encoding is performed based on the high-order LDPC long code parity check matrix to generate a high-order LDPC long code. The transmitting end sends the high-order LDPC long code; The receiving end that receives the high-order LDPC long code decodes the high-order LDPC long code to generate a decision bit sequence. Specifically, the construction of the high-order LDPC long code parity-check matrix is ​​as follows: Construct a second-order basis matrix; the second-order basis matrix is ​​expressed as follows: ;in, and They are respectively Matrix and Square matrix, and submatrices It has a double diagonal structure; phalanx Let be the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, and let the non-zero elements be... To ensure the square formation Full rank; Extend the encoding order of the second-order basis matrix to generate Higher-order parity check matrix ; Determine the expansion factor ,produce Expansion factor matrix To generate long codes; According to the higher-order check matrix The high-order LDPC long code parity matrix is ​​generated using the long code. ; Furthermore, encoding is performed based on the aforementioned high-order LDPC long code parity-check matrix to generate a high-order LDPC long code, including: The higher-order LDPC long code parity matrix is ​​processed using a preset calculation method to generate the higher-order LDPC long code. The preset calculation method includes inverting a weighted cyclic shift matrix, wherein the weighted cyclic shift matrix is ​​composed of the weight coefficients and the cyclic shift matrix, and the inversion of the weighted cyclic shift matrix is ​​accomplished by inverting the weight coefficients and the shift values ​​of the weighted cyclic shift matrix; the preset calculation method also includes column vector summation, the product of the weighted cyclic shift matrix and the column vectors, and the product of two weighted cyclic shift matrices.

4. A receiving method based on high-order LDPC long codes, applied to a communication system, the communication system including a receiving end, characterized in that, The method includes: Receive high-order LDPC long codes; The higher-order LDPC long code is decoded to generate a decision bit sequence; The higher-order LDPC long code is generated by the transmitting end based on the higher-order LDPC long code parity check matrix, and the higher-order LDPC long code parity check matrix is ​​constructed by the transmitting end. Specifically, constructing a high-order LDPC long code check matrix at the sending end involves: A second-order basis matrix is ​​constructed at the transmitting end; the second-order basis matrix is ​​represented as follows: ;in, and They are respectively Matrix and Square matrix, and submatrices It has a double diagonal structure; phalanx Let be the sum of a diagonal matrix and the matrix obtained by cyclically shifting it upwards by one unit, and let the non-zero elements be... To ensure the square formation Full rank; Extend the encoding order of the second-order basis matrix to generate Higher-order parity check matrix ; Determine the expansion factor ,produce Expansion factor matrix To generate long codes; According to the higher-order check matrix The high-order LDPC long code parity matrix is ​​generated from the long code. ; Furthermore, encoding is performed based on the aforementioned high-order LDPC long code parity-check matrix to generate a high-order LDPC long code, including: The higher-order LDPC long code parity matrix is ​​processed using a preset calculation method to generate the higher-order LDPC long code. The preset calculation method includes inverting a weighted cyclic shift matrix, wherein the weighted cyclic shift matrix is ​​composed of the weight coefficients and the cyclic shift matrix, and the inversion of the weighted cyclic shift matrix is ​​accomplished by inverting the weight coefficients and the shift values ​​of the weighted cyclic shift matrix; the preset calculation method also includes column vector summation, the product of the weighted cyclic shift matrix and the column vectors, and the product of two weighted cyclic shift matrices.

5. A communication device, characterized in that, It includes a communication interface and a processor, the processor being used to execute computer programs or instructions, causing the communication device to perform the communication method as described in any one of claims 1-2.

6. A computer-readable storage medium, characterized in that, It includes computer programs and instructions that, when run on a computer, cause the computer to perform the communication method as described in any one of claims 1-2.

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