A link equalization method, device and computer equipment

Abstract

The application discloses a link equalization method and device and a computer device, relates to the technical field of communication, and is used for improving the success rate of link equalization. The method is applied to a PCIe device, the PCIe device is connected with a host device through a PCIe link, and the method comprises the following steps: configuring an equalization parameter of the PCIe device as a first equalization parameter; the equalization parameter of the PCIe device is used for adjusting the strength of a signal sent by the PCIe device; sending indication information to the host device; the indication information is used for indicating that the PCIe device is in an equalization first stage; and under the condition that response information of the host device to the indication information is not received within a first preset time period, the indication information is sent to the host device again.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a link equalization method, apparatus and computer equipment. Background Technology

[0002] The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) link is used for signal transmission between two devices. Specifically, a signal is sent from the transmitter of one device, transmitted through the PCIe link, and arrives at the receiver of another device. During transmission, signal distortion can occur due to factors such as transmission rate, electromagnetic interference, and channel quality, affecting communication performance. Therefore, to receive a high-quality signal at the receiver, signal compensation can be performed at the transmitter, during PCIe link transmission, or at the receiver to reduce the impact of signal distortion on communication performance. This signal compensation is called link equalization.

[0003] When a PCIe link transmits signals at a rate of 2.5GT / s or 5GT / s, link equalization can be performed only at the transmitting end with fixed equalization parameters. When the PCIe link's transmission rate increases to 8GT / s or higher, equalization parameters need to be negotiated between the signal receiving and transmitting ends to achieve optimal transmission performance. During the equalization parameter negotiation process, the upstream port (USP) and downstream port (DSP) of the PCIe link negotiate the equalization parameters by sending indication messages. If one party does not receive a response to the indication message from the other party within a specified time, link equalization may fail, affecting the link's transmission rate. Summary of the Invention

[0004] This application provides a link balancing method, apparatus, and computer device to improve the success rate of link balancing.

[0005] Firstly, this application provides a link balancing method applied to a PCIe device; wherein a host device and a PCIe device are connected via a PCIe link. The method includes: the PCIe device configuring balancing parameters to first balancing parameters; the balancing parameters of the PCIe device being used to adjust the strength of the signal emitted by the PCIe device; sending indication information to the host device; the indication information being used to indicate that the PCIe device is in a first balancing phase; and, if no response information to the indication information is received from the host device within a first preset time period, re-sending the indication information to the host device; the first preset time period being the time period following the start of the PCIe device sending the indication information to the host device.

[0006] It is understood that, based on the method provided in this application, when the PCIe device and the host device are in the first equalization phase (the first equalization phase is when the PCIe device and the host device negotiate equalization parameters to make the bit error rate of the PCIe link less than or equal to a first bit error rate), the PCIe device sends an indication message to the host device; if no response message is received from the host device for the indication message within a first preset time period (i.e., the time period after the PCIe device starts sending the indication message to the host device), the indication message is sent to the host device again. It can be seen that, in the method provided in this application embodiment, the probability of the host device receiving the indication message can be increased by increasing the number of times the PCIe device sends signals to the host device, thereby improving the success rate of link equalization.

[0007] In another possible implementation, when the equalization parameter of the PCIe device is the first equalization parameter, sending indication information to the host device includes: sending a first signal to the host device; the first signal includes the indication information.

[0008] It is understandable that PCIe devices can transmit indication information by sending signals. The strength of the signal transmitted by a PCIe device is related to the value of its equalization parameters. For example, the signal strength of a PCIe device when its equalization parameters are set to the first configuration parameter will differ from the signal strength when it uses other configuration parameters. Since the first equalization parameter is the one specified by the host, the host device has a higher probability of receiving the signal sent by the PCIe device when its equalization parameters are set to the first configuration parameter.

[0009] In another possible implementation, if no response to the instruction information is received from the host device within the first preset time period, sending the instruction information to the host device again includes: sending a first signal to the host device if no response to the instruction information is received from the host device within the first preset time period; the first signal includes the instruction information.

[0010] It is understandable that PCIe devices can transmit indication information by sending signals. The strength of the signal sent by the PCIe device is related to the value of its equalization parameters. Since the first equalization parameter is the one specified by the host, the host device has a higher probability of receiving the signal sent by the PCIe device when its equalization parameters are set to the first configuration parameter.

[0011] In another possible implementation, if no response to the instruction information is received from the host device within the first preset time period, sending the instruction information to the host device again includes: if no response to the instruction information is received from the host device within the first preset time period, determining a second equalization parameter based on a first equalization parameter; wherein, when the equalization parameter of the PCIe device is the second equalization parameter, the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter; configuring the equalization parameter of the PCIe device to the second equalization parameter; and sending the instruction information to the host device again when the equalization parameter of the PCIe device is the second equalization parameter.

[0012] It is understandable that if no response to the indication information is received from the host device within the first preset time period, it may be because the signal strength transmitted by the PCIe device when the equalization parameters are set to the first equalization parameter is not high, and the signal strength will attenuate to varying degrees during transmission, resulting in the host device not receiving the indication information. Therefore, the method provided in this application can dynamically adjust the equalization parameter value and then retransmit the indication information with the new equalization parameter value, which can improve the signal quality of the transmitted indication information, thereby increasing the probability of the host device receiving the indication information and improving the success rate of link equalization.

[0013] In another possible implementation, when the equalization parameters of the PCIe device are the second equalization parameters, sending the indication information to the host device again includes: sending a second signal to the host device when the equalization parameters of the PCIe device are the second equalization parameters; the second signal includes the indication information; and the strength of the second signal is higher than the strength of the first signal.

[0014] It is understandable that PCIe devices can transmit indication information by sending signals. The strength of the signal sent by the PCIe device is related to the value of its equalization parameters. Since the first equalization parameter is specified by the host, and the second equalization parameter is determined based on the first, the host device has a higher probability of receiving the signal sent by the PCIe device when its equalization parameters are set to the second configuration parameter.

[0015] In another possible implementation, if no response information is received from the host device for the indication information within the first preset time period, sending the indication information to the host device again includes: if no response information is received within the first preset time period, determining whether the number of times the PCIe device sends the indication information to the host device is greater than or equal to a preset number; if the number is less than the preset number, sending the indication information to the host device again.

[0016] It is understandable that, since the duration of the first phase of equalization is limited, PCIe devices cannot continuously retransmit indication information. Therefore, the method provided in this application can set a preset number of times to avoid the situation where the host device fails to receive the indication information sent by the PCIe device due to timeout.

[0017] In another possible implementation, after sending the instruction information to the host device again when no response information is received from the host device within the first preset time period, the method further includes: exiting the first phase of load balancing when no response information is received within the second preset time period; wherein the second preset time period is the time period after the PCIe device starts sending the instruction information to the host device again.

[0018] Understandably, if no response is received within the second preset time period, the PCIe device will exit the first phase of link balancing due to timeout and restart the link balancing process. This avoids an increase in the overall balancing time of the PCIe link due to excessively long waiting times in the first phase, thus improving link balancing efficiency.

[0019] In another possible implementation, after sending the instruction information to the host device again when no response information is received from the host device within the first preset time period, the method further includes: entering the second equalization stage when a response information is received within the second preset time period.

[0020] Understandably, since the second bit error rate is lower than the first bit error rate, the first equalization stage is for coarse adjustment of the equalization parameters, while the second equalization stage is for fine adjustment of the equalization parameters. Therefore, receiving a response message within the second preset time period indicates that the PCIe device has completed the adjustment of the equalization parameters in the first equalization stage and can proceed to the second equalization stage.

[0021] Secondly, this application provides a link equalization device applied to a PCIe device; wherein the host device and the PCIe device are connected via a PCIe link. The link equalization device includes: a configuration module, used to configure the equalization parameters of the PCIe device as first equalization parameters; the equalization parameters of the PCIe device are used to adjust the strength of the signal emitted by the PCIe device; a transmission module, used to send indication information to the host device; the indication information is used to indicate that the PCIe device is in the first equalization stage; the transmission module is further used to send the indication information to the host device again if no response information to the indication information is received from the host device within a first preset time period.

[0022] In another possible implementation, the aforementioned sending module is specifically used to send a first signal to the host device; the first signal includes indication information.

[0023] In another possible implementation, the aforementioned sending module is specifically used to send a first signal to the host device if no response information to the indication information is received from the host device within a first preset time period; the first signal includes the indication information.

[0024] In another possible implementation, the aforementioned sending module is specifically used to determine a second equalization parameter based on a first equalization parameter if no response information to the indication information is received from the host device within a first preset time period; wherein, when the equalization parameter of the PCIe device is the second equalization parameter, the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter; the equalization parameter of the PCIe device is configured as the second equalization parameter; and when the equalization parameter of the PCIe device is the second equalization parameter, the indication information is sent to the host device again.

[0025] In another possible implementation, the aforementioned sending module is specifically used to send a second signal to the host device when the equalization parameter of the PCIe device is the second equalization parameter; the second signal includes indication information; the strength of the second signal is higher than the strength of the first signal.

[0026] In another possible implementation, the aforementioned sending module is specifically used to determine whether the number of times the PCIe device sends indication information to the host device is greater than or equal to a preset number if no response information is received within the first preset time period; if the number is less than the preset number, the module sends indication information to the host device again.

[0027] In another possible implementation, the link balancing device further includes an adjustment module, used to exit the first phase of balancing if no response information is received within a second preset time period; wherein the second preset time period is the time period after the PCIe device starts sending instruction information to the host device again.

[0028] In another possible implementation, the aforementioned adjustment module is also used to enter the second stage of equalization upon receiving response information within a second preset time period.

[0029] Thirdly, this application provides a computer device, which includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to enable the computer device to implement any of the link balancing methods provided in the first aspect above.

[0030] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions that, when executed on a computer, cause the computer to perform any of the link balancing methods provided in the first aspect above.

[0031] Fifthly, this application provides a computer program product including computer instructions that, when executed on a computer, cause the computer to perform any of the link balancing methods provided in the first aspect above.

[0032] For a detailed description of the second to fifth aspects and their various implementations in this application, please refer to the detailed description in the first aspect and its various implementations; and for a detailed analysis of the beneficial effects of the second to fifth aspects and their various implementations in the first aspect and its various implementations, please refer to the beneficial effect analysis in the first aspect and its various implementations, which will not be repeated here.

[0033] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0034] Figure 1 A schematic diagram illustrating a link balancing state provided in an embodiment of this application;

[0035] Figure 2 A schematic diagram of the structure of a computer device provided in an embodiment of this application;

[0036] Figure 3 A flowchart of a link balancing method provided in this application embodiment Figure 1 ;

[0037] Figure 4 A flowchart of a link balancing method provided in this application embodiment Figure 2 ;

[0038] Figure 5 A flowchart of a link balancing method provided in this application embodiment Figure 3 ;

[0039] Figure 6 A flowchart of a link balancing method provided in this application embodiment Figure 4 ;

[0040] Figure 7 A flowchart of a link balancing method provided in this application embodiment Figure 5 ;

[0041] Figure 8 This is a schematic diagram of a link balancing device provided in an embodiment of this application. Detailed Implementation

[0042] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0043] The terms "first" and "second," etc., used in the specification and drawings of this application are used to distinguish different objects or to distinguish different treatments of the same object, rather than to describe a specific order of objects.

[0044] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0045] It should be noted that in the embodiments of this application, the words "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the words "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0046] In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0047] During signal transmission, distortion can occur due to factors such as transmission rate, electromagnetic interference, and channel quality, affecting communication performance. Therefore, to receive high-quality signals at the receiving end, signal compensation can be performed at the transmitting end, during PCIe link transmission, or at the receiving end to reduce the impact of signal distortion on communication performance. This signal compensation is called link equalization.

[0048] For example, when the transmission rate of a PCIe link changes, such as when the transmission rate of a PCIe link increases to 8GT / s or higher, it is necessary to negotiate equalization parameters between the signal receiver and the signal transmitter to obtain the best transmission performance.

[0049] Typically, when a PCIe link needs to change its transmission rate, both the upstream port (USP) and downstream port (DSP) at both ends of the PCIe link enter Recovery state to perform PCIe link rate adjustment and link balancing. Specifically, Recovery state includes the following sub-states: RcvrLock state, RcvrCfg state, Speed ​​state, and Equalization state.

[0050] For example, the process of rate adjustment and link equalization performed by the USP and DSP at both ends of the PCIe link in Recovery mode can be as follows: Figure 1 The process is shown. Among them, as... Figure 1 As shown, the USP and DSP sequentially enter the RcvrLock state, RcvrCfg state, Speed ​​state, RcvrLock state, and Equalization state.

[0051] Specifically, after setting its Directed Speed ​​Change parameter to 1, the USP first enters the RcvrLock state. In the RcvrLock state, the USP sends the TS1 sequence (including the requested speed change, with the Speed ​​Change field of the TS1 sequence set to 1) from the training sequence (TS) to the DSP. Upon receiving the TS1 sequence from the USP, the DSP enters the RcvrLock state and also sets its Directed Speed ​​Change parameter to 1; subsequently, the DSP replies with the TS1 sequence to the USP.

[0052] After receiving the TS1 sequence from the DSP, the USP enters the RcvrCfg state. In the RcvrCfg state, the USP sends a TS2 sequence to the DSP (with both the Speed ​​Change and Autonomous Change fields set to 1). Upon receiving the TS2 sequence from the USP, the DSP enters the RcvrCfg state and replies with a TS2 sequence. In the reply TS2 sequence, the Autonomous Change field is reserved.

[0053] After completing the interaction of the TS2 sequence, both the USP and DSP enter the Speed ​​state and change their speed. After the speed change, the USP and DSP re-enter the RcvrLock state and interact with the TS1 sequence to obtain configuration information (such as equalization parameters). The Speed ​​Change setting for the TS1 sequence is set to 0. After completing the interaction of the TS1 sequence, the USP and DSP enter the Equalization state.

[0054] Specifically, the equalization process includes four equilibrium phases: the initial equilibrium phase (Phase 0), the first equilibrium phase (Phase 1), the second equilibrium phase (Phase 2), and the third equilibrium phase (Phase 3). The USP enters the initial equilibrium phase (Phase 0) from the RcvrLock state; the DSP enters the first equilibrium phase (Phase 1) from the RcvrLock state. That is, the USP's equalization process includes four equilibrium phases; the DSP's equalization process includes three equilibrium phases (excluding Phase 0).

[0055] During the initial equalization phase (Phase 0), the USP sends equalization parameters back to the DSP. Optionally, if the USP fails to equalize during the initial equalization phase, it can revert to the Speed ​​phase.

[0056] In the first phase of equalization (Phase 1), the USP and DSP initially coordinate the equalization parameters to ensure that the bit error rate (BER) of the PCIe link is less than or equal to a first preset BER. For example, the first preset BER can be 10-1. -4 Optionally, if the USP and / or DSP fail to achieve equalization in the first equalization phase, the process can revert to the Speed ​​phase.

[0057] In the second equalization phase (Phase 2), the USP, acting as the master, adjusts its own receiver equalization parameters and instructs the DSP to adjust its transmitter equalization parameters, ensuring that the bit error rate (BER) of the signal received by the USP is less than or equal to a second BER. The second BER is less than the first BER. For example, the second BER could be 10-1. -12 Optionally, if the USP and / or DSP fail to equalize in the second equalization phase, the process can revert to the Speed ​​phase.

[0058] In Phase 3 of equalization, the DSP, acting as the Master, adjusts its own receiver equalization parameters and instructs the USP to adjust its transmitter equalization parameters, ensuring that the bit error rate (BER) of the signal received by the DSP is less than or equal to the second BER. Optionally, if the USP and / or DSP fail to equalize in Phase 3, it can revert to the Speed ​​phase.

[0059] As in the background and related technologies, in the first phase of equalization (Phase 1), the uplink port (USP) and downlink port (DSP) of the PCIe link negotiate equalization parameters by sending each other indication information. If one party does not receive the other party's response information to the indication information within a specified time, it may cause the link equalization to fail and affect the transmission rate of the link.

[0060] To address the aforementioned technical problems, this application provides a link balancing method. The method's approach is as follows: When the PCIe device and the host device are in the first balancing phase (the first balancing phase is when the PCIe device and the host device negotiate balancing parameters to ensure the bit error rate of the PCIe link is less than or equal to a first bit error rate), the PCIe device sends an indication message to the host device. If no response is received from the host device within a first preset time period (i.e., the time period after the PCIe device starts sending the indication message to the host device), the PCIe device sends the indication message again. It can be seen that the method provided in this application increases the probability of the host device receiving the indication message by increasing the number of times the PCIe device sends signals to the host device, thereby improving the success rate of link balancing.

[0061] The embodiments provided in this application will now be described in detail with reference to the accompanying drawings.

[0062] See Figure 2 This is a schematic diagram of the hardware operating environment involved in the embodiments of this application. Figure 2 As shown, the method provided in this application embodiment is applied to a computer device, which may be a personal computer (PC), a smartphone, tablet computer, e-book reader, portable computer, or other terminal device with data processing and data storage functions.

[0063] like Figure 2 As shown, the computer device 100 includes a host device 110 and a PCIe device 120. The host device 110 and the PCIe device 120 are connected via a PCIe link.

[0064] It is understandable that the PCIe link is an end-to-end connection. Therefore, the host device 110 and the PCIe device 120 are located at opposite ends of the PCIe link, and the host device 110 and the PCIe device 120 are each other's data sender and data receiver.

[0065] The host device 110 includes a processor, which can be based on an x86 architecture or an ARM (advanced RISC machine) architecture. For example, the processor can be a central processing unit (CPU). The processor can run an operating system (such as Linux or Windows) and run various application software based on the operating system.

[0066] In this embodiment, the host device 110 includes a PCIe interface for connecting to a PCIe device 120. The PCIe interface includes a transmit (TX) end and a receive (RX) end; TX is used to transmit data; and RX is used to receive data.

[0067] In some embodiments, the PCIe interface of the host device 110 is located in the backplane of the host device 110. Optionally, the backplane may also include other interfaces for connecting other devices or circuit boards.

[0068] In some embodiments, the host device 110 further includes a Retimer chip for performing signal recovery and signal enhancement processing on the received signal to ensure the quality of signal transmission. The Retimer chip is located between the processor and the backplane. Optionally, the Retimer chip includes clock and data recovery (CDR), capable of generating a clock reconstruction signal and using the clock reconstruction signal to perform signal recovery and signal enhancement processing on the received signal. It is understood that after a certain distance of transmission, the waveform of the signal may be distorted to some extent, and the signal energy may also be weakened. Therefore, this embodiment of the application uses a Retimer chip to perform signal recovery and signal enhancement processing on the received signal to ensure the quality of signal transmission.

[0069] PCIe device 120 refers to a device that conforms to the PCIe bus standard.

[0070] For example, PCIe device 120 includes: graphics card, solid state drive (SSD), wireless network card, wired network card, sound card or video capture card, etc.

[0071] In some embodiments, the PCIe device 120 includes a PCIe interface. The PCIe device 120 is able to establish a PCIe link with the host device 110 through the PCIe interface.

[0072] In some embodiments, the PCIe interface of the PCIe device 120 is located in the physical layer (Prot) of the PCIe device 120. Optionally, the Prot may also include other interfaces for connecting other devices or circuit boards.

[0073] In some embodiments, the PCIe device 120 further includes a controller for receiving, analyzing, and sending instructions. The controller includes firmware (FW), which drives the PCIe device 120 to operate according to the driver program recorded in the firmware. In this embodiment, the controller executes the link balancing method provided in this embodiment according to the program recorded in the firmware.

[0074] In some embodiments, the USP and DSP of the PCIe link are determined based on the data flow direction. The USP is the port where data flows in, and the DSP is the port where data flows out. For example, in this embodiment, the host device 110 acts as the DSP device, and the PCIe device 120 acts as the USP device.

[0075] In some embodiments, the computer device 100 may further include a memory ( Figure 2 (Not shown in the image). Memory is used to store data such as instructions or program code. For example, memory may be read-only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, electrically erasable programmable read-only memory (EEPROM), disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited thereto.

[0076] In this embodiment of the application, the memory can be used to store the interaction information between the host device 110 and the PCIe device 120 during the link balancing process, as well as the execution program of the link balancing method, etc.

[0077] It should be noted that the execution entity of the link balancing method provided in this application embodiment is not limited. For example, the method can be executed by the computer device 100 itself, or by the PCIe device 120 in the computer device 100. For ease of subsequent explanation, the following embodiment will be described using the method executed by the PCIe device 120 as an example.

[0078] The following is a detailed description of a link balancing method provided in the embodiments of this application.

[0079] The link balancing method provided in this application embodiment can be derived from, for example: Figure 2 The PCIe device 120 shown is used to perform this. Specifically, as... Figure 3 As shown, the method includes the following steps:

[0080] S201, The PCIe device configures the PCIe device's equalization parameter as the first equalization parameter.

[0081] The aforementioned equalization parameters can include pre-emphasis parameters and de-emphasis parameters. It is understood that during signal transmission in a PCIe link, the attenuation of high-frequency components is greater than the attenuation of low-frequency components. Therefore, signal compensation typically needs to compensate for the high-frequency components. Thus, signal compensation methods in PCIe links include pre-emphasis and de-emphasis. Pre-emphasis refers to the transmitting end boosting the high-frequency components of the signal during transmission. De-emphasis refers to the transmitting end attenuating the low-frequency components of the signal during transmission. Therefore, equalization parameters can include pre-emphasis parameters and de-emphasis parameters.

[0082] For example, according to the PCIe protocol, different combinations of pre-emphasis and de-emphasis parameters constitute a level of equalization parameters (which can be represented by Preset). Different levels of equalization parameters can achieve different equalization effects (for example, when the equalization parameters of a PCIe device are of different levels, the signal strength emitted by the PCIe device will be different). For example, different levels of equalization parameters can be represented in the form shown in Table 1 below.

[0083] Table 1

[0084] Equilibrium parameters Pre-weighting parameters De-emphasis parameters P4 0.0 0.0 P1 0.0 -3.5±1dB P0 0.0 -6.0±1.5dB P9 3.5±1dB 0.0 P8 3.5±1dB -3.5±1dB P7 3.5±1dB -6.0±1.5dB P5 1.9±1dB 0.0 P6 2.5±1dB 0.0 P3 0.0 -2.5±1dB P2 0.0 -4.4±1.5dB

[0085] It is understood that the above-mentioned equalization parameters for different gears are merely examples. In other embodiments, equalization parameters for other gears may also be included, and this application does not limit this.

[0086] For example, since the first equalization parameter includes a pre-emphasis parameter and a deemphasis parameter, and both the pre-emphasis parameter and the deemphasis parameter are transmitting parameters, configuring the equalization parameter of the PCIe device as the first equalization parameter includes: configuring the pre-emphasis parameter and the deemphasis parameter of the transmitting end of the PCIe device as the pre-emphasis parameter and the deemphasis parameter corresponding to the first equalization parameter, respectively.

[0087] In some embodiments, the equalization parameters of the PCIe device are used to adjust the strength of the signal emitted by the PCIe device. For example, when the equalization parameters of the PCIe device are different levels as shown in Table 1, the strength of the signal emitted by the PCIe device is also different.

[0088] In some embodiments, the first equalization parameter mentioned above is an equalization parameter specified by the host device. For example, the equalization parameter specified by the host device can be any one of the equalization parameters at different levels shown in Table 1 above. It is understood that the equalization parameter specified by the host device can be determined by the host device according to its own situation. For example, the equalization parameter specified by the host device can be an equalization parameter that gives the host device a higher probability of receiving the indication information (i.e., when the PCIe device sends the indication information using the configuration parameters specified by the host device, the host device has a higher probability of receiving the indication information).

[0089] For example, in the RcvrLock state, the host device can send configuration information to the PCIe device, which includes the load balancing parameters specified by the host device. Correspondingly, after receiving the instruction from the host device, the PCIe device configures its load balancing parameters to those specified by the host device.

[0090] S202. When the equalization parameter of the PCIe device is the first equalization parameter, the PCIe device sends an instruction message to the host device.

[0091] The indication information is used to indicate that the PCIe device is in the first phase of load balancing. The first phase of load balancing is the stage in which the PCIe device and the host device negotiate load balancing parameters to make the bit error rate of the PCIe link less than or equal to the first bit error rate.

[0092] Optionally, the above indication information can be a TS1 sequence. The EC field in the TS1 sequence indicates the leveling stage. For example, when the EC field in the TS1 sequence sent by the PCIe device to the host device is equal to 01h, it indicates that the PCIe device is in the first leveling stage.

[0093] In some embodiments, a PCIe device can transmit indication information by sending signals. The strength of the signal transmitted by the PCIe device is related to the value of its equalization parameters. For example, when the equalization parameters of the PCIe device are different levels as shown in Table 1 above, the strength of the signal transmitted by the PCIe device will be different. Thus, when transmitting indication information, the strength of the signal carrying the indication information can be changed by adjusting the equalization parameters of the PCIe device.

[0094] Optionally, step S202 above can be implemented as follows: when the equalization parameter of the PCIe device is the first equalization parameter, the PCIe device sends a first signal to the host device. The first signal includes indication information.

[0095] In some embodiments, the first signal may further carry a first equalization parameter, enabling the host device to know the equalization parameters of the PCIe device. For example, the first signal may also include an identifier for the equalization parameter, indicating the equalization parameter when the PCIe device sends the first signal. For example, if the PCIe device's equalization parameter is the first equalization parameter, the identifier for the equalization parameter is used when sending the first signal to the host device. For instance, if the first equalization parameter is an equalization parameter at the P3 level as shown in Table 1, the identifier for the equalization parameter can be P3.

[0096] It is understandable that, since the aforementioned first equalization parameter is determined by the host device based on its own circumstances, the probability of the PCIe device receiving the indication information is relatively high when it uses the first equalization parameter to send the indication information. Therefore, in order to increase the probability of the host device receiving the indication information, this embodiment configures the PCIe device's equalization parameter to the first equalization parameter before sending the indication information to the host device.

[0097] It is understandable that S201-S202 described above is one specific implementation of "the PCIe device sending indication information to the host device". Of course, the specific implementation is not limited to this. For example, "the PCIe device sending indication information to the host device" can also be implemented as follows: the PCIe device configures its own balancing parameters to preset balancing parameters; when the PCIe device's balancing parameters are preset balancing parameters, the PCIe device sends indication information to the host device.

[0098] The preset balancing parameters are the balancing parameters specified by the PCIe device. It can be understood that the balancing parameters specified by the PCIe device can be determined by the PCIe device based on its own circumstances or historical link balancing processes. For example, the balancing parameters specified by the PCIe device can be balancing parameters determined by the PCIe device through evaluating historical link balancing processes. When the PCIe device uses these balancing parameters to send indication information, the host device has a higher probability of receiving this indication information.

[0099] S203. If no response information is received from the host device for the indication information within the first preset time period, the PCIe device sends the indication information to the host device again.

[0100] The first preset time period is the period following the start of the PCIe device sending the instruction information to the host device. It should be noted that the duration of the first preset time period is shorter than the duration of the first phase of the load balancing process. For example, assuming the duration of the first phase of load balancing is 32ms, the duration of the first preset time period should be less than 32ms; for instance, the duration of the first preset time period could be 4ms. That is, if no response is received from the host device within 4ms after the PCIe device starts sending the instruction information to the host device, the instruction information is sent to the host device again.

[0101] In some embodiments, the response information is used to indicate that the host device has received the indication information sent by the PCIe device. In other embodiments, the response information is also used to inform the PCIe device of the balance status of the host device. For example, if the host device receives the indication information sent by the PCIe device, it indicates that the first phase of balance has been completed and the host device can enter the second phase of balance. After entering the second phase of balance, the host device sends a response information to the PCIe device so that the PCIe device knows that the host device has entered the second phase of balance, and the PCIe device can also enter the second phase of balance.

[0102] Optionally, the response information described above can be a TS1 sequence. The EC field in the TS1 sequence indicates the leveling stage. For example, when the EC field in the TS1 sequence sent by the host device to the PCIe device equals 10h, it indicates that the host device is in the second leveling stage.

[0103] In some embodiments, step S203 can be implemented as follows: if no response information is received within a first preset time period, determine whether the number of times the PCIe device sends indication information to the host device is greater than or equal to a preset number; if the number is less than the preset number, send indication information to the host device again.

[0104] The preset number of times can be determined based on the duration of the first phase of the load balancing process and the duration of a preset time period (the preset time period is the time period after each time the PCIe device sends an instruction message to the host device; for example, the first preset time period can be the time period after the PCIe device first sends an instruction message to the host device, and the second preset time period can be the time period after the PCIe device sends an instruction message to the host device again). For example, assuming the duration of the first phase of the load balancing process is 32ms and the duration of each preset time period is 10ms, the preset number of times can be 3.

[0105] For example, assuming the preset number of times is 3, and the PCIe device has sent the indication information to the host device 2 times, then if no response information is received within the first preset time period, the PCIe device will send the indication information to the host device again.

[0106] It is understandable that, since the duration of the first phase of equalization is limited, the PCIe device cannot continuously retransmit the indication information. Therefore, the method provided in this application embodiment can set a preset number of times to avoid the situation where the host device fails to receive the indication information sent by the PCIe device due to timeout.

[0107] As one possible implementation, such as Figure 4 As shown, the above step S203 can be implemented as the following step S300.

[0108] S300: If no response information is received from the host device for the indication information within the first preset time period, and the equalization parameter of the PCIe device is the first equalization parameter, the PCIe device sends the indication information to the host device again.

[0109] In some embodiments, the PCIe device can transmit indication information by sending signals. Thus, step S300 can be implemented as follows: if no response information to the indication information is received from the host device within a first preset time period, and the equalization parameter of the PCIe device is the first equalization parameter, a first signal is sent to the host device.

[0110] The first signal includes indication information. Optionally, the first signal may also carry a first equalization parameter, so that the host device can know the equalization parameter of the PCIe device.

[0111] For example, assuming the PCIe device is an SSD; and the first balancing parameter is the P3 level balancing parameter as shown in Table 1, the SSD sets the balancing parameter to the P3 level and then sends a first signal to the host device. Assuming the first preset time period is 4ms, if no response from the host device is received within 4ms, the SSD sends the first signal to the host device again. Assuming the second preset time period is 4ms, if no response from the host device is received within 4ms, the SSD exits the first balancing phase; if a response is received within 4ms, the SSD enters the second balancing phase.

[0112] It is understandable that if no response information for the indication information is received from the host device within the first preset time period, it may be due to the influence of the environment causing the indication information to be lost during transmission. Therefore, in the method provided in this application embodiment, the probability of the host device receiving the indication information can be increased by increasing the number of times the PCIe device sends the indication information to the host device, thereby improving the success rate of link balancing.

[0113] As another possible implementation, such as Figure 5 As shown, step S203 can also be implemented as the following steps S400-S402.

[0114] S400: If no response information for the instruction information is received from the host device within the first preset time period, the second equalization parameter is determined based on the first equalization parameter.

[0115] Specifically, when the equalization parameter of the PCIe device is the second equalization parameter, the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter.

[0116] For example, assuming the first equalization parameter is the equalization parameter corresponding to the P3 level as shown in Table 1, then among the equalization parameters of multiple levels shown in Table 1, if the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter is the equalization parameter corresponding to the P4 level, then the second equalization parameter can be the equalization parameter corresponding to the P4 level.

[0117] S401. Configure the equalization parameters of the PCIe device as the second equalization parameters.

[0118] For example, since the equalization parameters include pre-emphasis parameters and de-emphasis parameters, and both pre-emphasis parameters and de-emphasis parameters are equalization parameters of the transmitting end, configuring the equalization parameters of the PCIe device as the second equalization parameters includes configuring the pre-emphasis parameters and de-emphasis parameters of the transmitting end of the PCIe device as the pre-emphasis parameters and de-emphasis parameters corresponding to the second equalization parameters.

[0119] S402. When the equalization parameter of the PCIe device is the second equalization parameter, the PCIe device sends an instruction message to the host device again.

[0120] In some embodiments, the PCIe device can transmit indication information by sending signals. Thus, step S300 can be implemented as follows: when the equalization parameter of the PCIe device is the second equalization parameter, a second signal is sent to the host device.

[0121] The second signal includes indication information. The strength of the second signal is higher than that of the first signal.

[0122] Optionally, the second signal may also carry a second equalization parameter, enabling the host device to know the equalization parameters of the PCIe device. For example, the second signal may further include an identifier for the equalization parameter, indicating the equalization parameter when the PCIe device sends the second signal. For example, if the PCIe device's equalization parameter is the second equalization parameter, the identifier for the equalization parameter is used when sending the second signal to the host device. For instance, if the second equalization parameter is an equalization parameter at the P4 level as shown in Table 1, the identifier for the equalization parameter can be P4.

[0123] For example, assuming the PCIe device is an SSD; and the first equalization parameter is the P3 level equalization parameter as shown in Table 1, the SSD sets its equalization parameter to the P3 level and then sends a first signal to the host device. Assuming the first preset time period is 4ms, if no response from the host device is received within 4ms, it is assumed that the signal strength is insufficient, causing the host device to fail to receive the signal. Therefore, the SSD determines the second equalization parameter based on the first equalization parameter, configures its equalization parameter to the second equalization parameter, and then sends a second signal to the host device. Assuming the second preset time period is 4ms, if no response from the host device is received within 4ms, the SSD exits the first equalization phase; if a response is received within 4ms, the SSD enters the second equalization phase.

[0124] It is understandable that, since the host and PCIe devices may come from two different manufacturers, the optimal equalization parameters for the host device (i.e., the parameters at which the host device emits the strongest signal) may not be the optimal equalization parameters for the PCIe device, and vice versa.

[0125] Therefore, the embodiments of this application can consider different perspectives during the chain establishment negotiation process. First, the PCIe device sends the indication information using the first equalization parameter suggested by the host device (i.e., the equalization parameter specified by the host device, which may be the optimal equalization parameter for the host device). If the PCIe device does not receive a response from the host device within a first preset time period, it may be because the signal strength sent by the PCIe device with the first equalization parameter is not high, and the signal strength will attenuate to varying degrees during transmission, resulting in the host device not receiving the indication information. Therefore, in the method provided by the embodiments of this application, the PCIe device can dynamically adjust the equalization parameter value and then retransmit the indication information with the new equalization parameter value.

[0126] Since the first equalization parameter may not be the optimal equalization parameter for the PCIe device, the PCIe device can choose the optimal equalization parameter (e.g., the second equalization parameter) to send the indication information. That is, the signal strength emitted by the PCIe device configured with the second equalization parameter is higher than the signal strength emitted by the PCIe device configured with the first equalization parameter. It can be seen that the method provided in this application embodiment can improve the signal quality of the transmitted indication information, thereby increasing the probability of the host device receiving the indication information and improving the success rate of link equalization.

[0127] Optional, such as Figure 6 As shown, after step S203, the method may further include the following step S204:

[0128] S204. If no response information is received within the second preset time period, the PCIe device exits the first phase of load balancing.

[0129] The second preset time period is the period after the PCIe device sends the instruction information to the host device again.

[0130] Understandably, if no response is received within the second preset time period, the PCIe device will exit the first phase of link balancing due to timeout. Optionally, after exiting the first phase, the PCIe device can enter the Speed ​​state, redetermine the transmission rate of the PCIe link, and perform link balancing again. This avoids an increase in the overall balancing time of the PCIe link due to excessive waiting time in the first phase, thus improving link balancing efficiency.

[0131] Optional, such as Figure 7 As shown, after step S203, the method may further include the following step S205:

[0132] S205. If a response is received within the second preset time period, the PCIe device enters the second phase of equalization.

[0133] The second preset time period is the period after the PCIe device sends the instruction information to the host device again.

[0134] The aforementioned equalization second stage is a stage in which the PCIe device adjusts the equalization parameters of its own receiving end and instructs the host device to adjust the equalization parameters of the host device's transmitting end, so that the bit error rate of the signal received by the PCIe device is less than or equal to the second bit error rate; wherein, the second bit error rate is less than the first bit error rate.

[0135] Understandably, since the second bit error rate is lower than the first bit error rate, the first equalization stage is for coarse adjustment of the equalization parameters, while the second equalization stage is for fine adjustment of the equalization parameters. Therefore, receiving a response message within the second preset time period indicates that the PCIe device has completed the adjustment of the equalization parameters in the first equalization stage and can proceed to the second equalization stage.

[0136] It is understood that, based on the method provided in this application embodiment, when the PCIe device and the host device are in the first equalization phase (the first equalization phase is when the PCIe device and the host device negotiate equalization parameters to make the bit error rate of the PCIe link less than or equal to a first bit error rate), the PCIe device sends indication information to the host device; if no response information to the indication information is received from the host device within a first preset time period (i.e., the time period after the PCIe device starts sending the indication information to the host device), the indication information is sent to the host device again. It can be seen that, in the method provided in this application embodiment, the probability of the host device receiving the indication information can be increased by increasing the number of times the PCIe device sends signals to the host device, thereby improving the success rate of link equalization.

[0137] The foregoing primarily describes the solutions of the embodiments of this application from a methodological perspective. It is understood that, in order to achieve the above functions, the link balancing device includes at least one of the hardware structures and software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0138] This application embodiment can divide the link equalization device into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0139] like Figure 8 As shown in the figure, this application embodiment provides a link balancing device for performing, as Figure 3The link balancing method shown is illustrated. The link balancing device 500 includes a configuration module 501 and a transmission module 502. In some embodiments, the link balancing device 500 further includes an adjustment module 503.

[0140] Configuration module 501 is used to configure the equalization parameters of the PCIe device as the first equalization parameter; the equalization parameters of the PCIe device are used to adjust the strength of the signal emitted by the PCIe device. For example, combined with Figure 3 Configuration module 501 can be used to perform actions such as Figure 3 S201 is shown.

[0141] The sending module 502 is used to send indication information to the host device; the indication information is used to indicate that the PCIe device is in the first phase of equalization; if no response information to the indication information is received from the host device within a first preset time period, the indication information is sent to the host device again; the first preset time period is the time period after the PCIe device starts sending the indication information to the host device. For example, combined with Figure 3 The sending module 502 can be used to perform actions such as... Figure 3 S202-S203 are shown.

[0142] In another possible implementation, the aforementioned sending module 502 is specifically used to send a first signal to the host device; the first signal includes indication information. For example, combined with Figure 3 The sending module 502 can be used to perform actions such as... Figure 3 S202 is shown.

[0143] In another possible implementation, the aforementioned sending module 502 is specifically used to send a first signal to the host device if no response information to the indication information is received from the host device within a first preset time period; the first signal includes the indication information. For example, combined with Figure 4 The sending module 502 can be used to perform actions such as... Figure 4 The S300 shown.

[0144] In another possible implementation, the aforementioned sending module 502 is specifically used to determine a second equalization parameter based on the first equalization parameter if no response information to the indication information is received from the host device within a first preset time period; wherein, when the equalization parameter of the PCIe device is the second equalization parameter, the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter; the equalization parameter of the PCIe device is configured as the second equalization parameter; and when the equalization parameter of the PCIe device is the second equalization parameter, the indication information is sent to the host device again. For example, combined with Figure 5 The sending module 502 can be used to perform actions such as... Figure 5 The S400-S402 shown.

[0145] In another possible implementation, the aforementioned sending module 502 is specifically used to send a second signal to the host device when the equalization parameters of the PCIe device are the second equalization parameters; the second signal includes indication information; and the strength of the second signal is higher than the strength of the first signal. For example, combined with Figure 5 The sending module 502 can be used to perform actions such as... Figure 5 S402 is shown.

[0146] In another possible implementation, the aforementioned sending module 502 is specifically used to determine, if no response information is received within a first preset time period, whether the number of times the PCIe device sends indication information to the host device is greater than or equal to a preset number; if the number is less than the preset number, it sends indication information to the host device again. For example, combined with Figure 3 The sending module 502 can be used to perform actions such as... Figure 3 S203 is shown.

[0147] In another possible implementation, the adjustment module 503 is used to exit the first phase of load balancing if no response information is received within a second preset time period; wherein the second preset time period is the time period after the PCIe device starts sending the instruction information to the host device again. For example, combined with Figure 6 The adjustment module 503 can be used to perform actions such as... Figure 6 S204 is shown.

[0148] In another possible implementation, the adjustment module 503 is further configured to enter the second equalization stage upon receiving response information within a second preset time period. For example, combined with Figure 7 The adjustment module 503 can be used to perform actions such as... Figure 7 S205 is shown.

[0149] Through the above description of the implementation methods, those skilled in the art can clearly understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the link equalization device can be divided into different functional modules to complete all or part of the functions described above.

[0150] This application also provides a computer-readable storage medium. All or part of the processes in the above method embodiments can be executed by computer instructions instructing related hardware. The program can be stored in the computer-readable storage medium, and when executed, it can include the processes of the above method embodiments. The computer-readable storage medium can be any of the foregoing embodiments or memory. The computer-readable storage medium can also be an external storage device of the link equalization device, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the link equalization device. Further, the computer-readable storage medium can include both internal storage units of the link equalization device and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the link equalization device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0151] This application also provides a computer program product comprising a computer program that, when run on a computer, causes the computer to execute any of the link balancing methods provided in the above embodiments.

[0152] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, disclosure, and appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0153] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

[0154] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A link load balancing method, characterized in that, Host devices and high-speed serial computer expansion bus standard PCIe devices are connected via PCIe links; The method is applied to the PCIe device; the method includes: The PCIe device configures the equalization parameter to the first equalization parameter; the equalization parameter of the PCIe device is used to adjust the strength of the signal emitted by the PCIe device. Send indication information to the host device; the indication information is used to indicate that the PCIe device is in the first phase of equalization; If no response information from the host device to the indication information is received within a first preset time period, a second equalization parameter is determined based on the first equalization parameter; wherein, when the equalization parameter of the PCIe device is the second equalization parameter, the strength of the signal emitted by the PCIe device is greater than the strength of the signal emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter. Configure the balancing parameters of the PCIe device to the second balancing parameters; If the balancing parameters of the PCIe device are the second balancing parameters, the instruction information is sent to the host device again.

2. The method according to claim 1, characterized in that, Sending the indication information to the host device includes: Send a first signal to the host device; the first signal includes the indication information.

3. The method according to claim 1 or 2, characterized in that, When the balancing parameters of the PCIe device are the second balancing parameters, the instruction information is sent to the host device again, including: When the equalization parameter of the PCIe device is the second equalization parameter, a second signal is sent to the host device; the second signal includes the indication information; the strength of the second signal is higher than the strength of the first signal.

4. The method according to claim 1 or 2, characterized in that, If no response to the indication information is received from the host device within the first preset time period, the instruction information is sent to the host device again, including: If no response information is received within the first preset time period, determine whether the number of times the PCIe device sends the indication information to the host device is greater than or equal to a preset number. If the number of attempts is less than the preset number, the instruction information is sent to the host device again.

5. The method according to claim 1 or 2, characterized in that, If no response to the indication information is received from the host device within a first preset time period, and the indication information is sent to the host device again, the method further includes: If the response information is not received within the second preset time period, the first phase of the load balancing is terminated; wherein, the second preset time period is the time period after the PCIe device sends the indication information to the host device again.

6. The method according to claim 1 or 2, characterized in that, If no response to the indication information is received from the host device within a first preset time period, and the indication information is sent to the host device again, the method further includes: If the response information is received within the second preset time period, the system enters the second equalization phase.

7. A link equalization device, characterized in that, Applied to PCIe devices; wherein the PCIe device and the host device are connected via a PCIe link; the device includes: A configuration module is used to configure the equalization parameters of the PCIe device to the first equalization parameters; the equalization parameters of the PCIe device are used to adjust the strength of the signal emitted by the PCIe device; a transmission module is used to send indication information to the host device; the indication information is used to indicate that the PCIe device is in the first equalization stage; The sending module is further configured to, if no response information to the indication information is received from the host device within a first preset time period, determine a second equalization parameter based on the first equalization parameter; wherein, when the equalization parameter of the PCIe device is the second equalization parameter, the signal strength emitted by the PCIe device is greater than the signal strength emitted by the PCIe device when the equalization parameter of the PCIe device is the first equalization parameter; configure the equalization parameter of the PCIe device to the second equalization parameter; and, when the equalization parameter of the PCIe device is the second equalization parameter, send the indication information to the host device again.

8. A computer device, characterized in that, The computer device includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to enable the computer device to implement the link balancing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed on a computer, enable the computer to implement the link balancing method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes computer instructions that, when executed on a computer, cause the computer to implement the link balancing method as described in any one of claims 1 to 6.

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