Low specific on-resistance silicon carbide field effect transistor

Abstract

This invention belongs to the field of semiconductor technology, specifically providing a low specific on-resistance silicon carbide field-effect transistor to solve the problem of low electron mobility in the channel inversion layer of traditional SiC MOSFET devices. By utilizing an accumulation layer as the conductive channel, this invention achieves high electron mobility in the channel region, significantly reducing the specific on-resistance of the device while maintaining the same voltage rating as traditional silicon carbide MOSFETs. This greatly improves the trade-off between breakdown voltage and specific on-resistance in power devices. Furthermore, the device features a simplified manufacturing process and requires less ion implantation, avoiding the high cost and lattice damage associated with ion implantation, and achieving a significant performance improvement. Additionally, it further enhances the device's reverse freewheeling capability, greatly expanding its circuit applications and reducing application costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically providing a low specific on-resistance silicon carbide (SiC) accumulation-type channel field-effect transistor power device. Background Technology

[0002] Silicon carbide (SiC), a group IV-IV compound material with unique physical and chemical properties, possesses exceptionally high hardness, chemical stability, and thermal conductivity due to the strong chemical bonds between silicon and carbon atoms. The band gap of SiC (3.26 eV) is approximately three times that of silicon (1.12 eV). This wide band gap results in extremely low intrinsic carrier concentrations, allowing devices to withstand higher junction temperatures and operate under high-temperature conditions. Furthermore, it leads to a high breakdown electric field strength, meaning that at the same breakdown voltage, the breakdown voltage region thickness (or width) is smaller, the current density is higher, and the on-resistance is lower. A key parameter for evaluating power devices, the Baliga figure of merit, is expressed as FOM = V B 2 / R ON,sp ,in, V B Indicates the breakdown voltage of the device. R ON,sp This represents the specific on-resistance of the device; however, higher breakdown voltages require a reduction in the doping concentration in the breakdown voltage region, which in turn increases the specific on-resistance of the device. Therefore, balancing the trade-off between these two factors is a major focus in power device design.

[0003] In actual manufacturing, silicon carbide (SiC) field-effect transistors (MOSFETs) suffer from the problem of extremely high interface state density in the SiC / SiO2 system. Although numerous process methods have been proposed to optimize this, these methods significantly increase the complexity of the manufacturing process and production costs. For metal-oxide-semiconductor (MOSFETs), the high interface state density of the SiC / SiO2 system also leads to low inversion layer electron mobility (typically around 20–50 cm⁻¹). 2 ·v -1 ·s -1 The problem remains: existing technologies still struggle to significantly improve the electron mobility of the inversion layer in MOSFETs. Currently, through reasonable device structure design, the breakdown voltage of SiC MOSFET devices can reach near its theoretical limit, but the low electron mobility of the inversion layer in the channel region severely inhibits further reduction in the specific on-resistance. Summary of the Invention

[0004] The purpose of this invention is to address the problem of low electron mobility in the channel inversion layer of traditional SiC MOSFET devices by proposing a low on-state resistance silicon carbide (SiC) accumulation-type channel field-effect transistor. In this invention, the accumulation-type SiC MOSFET device achieves high electron mobility (150~200 cm⁻¹) in the accumulation layer of the channel region. 2 ·v -1 ·s -1 The design significantly reduces the resistance in the channel region, thereby greatly improving the trade-off between the device's breakdown voltage and specific on-resistance. Furthermore, the accumulator-type SiC MOSFET device in this invention demonstrates great potential due to its simple process flow and minimal ion implantation, avoiding to some extent the high cost and lattice damage associated with ion implantation, while also achieving a substantial improvement in device performance. In addition, considering the application scenarios of the device in circuits, achieving the normally-off capability of the accumulator-type field-effect transistor is essential. Based on the accumulator-type SiC MOSFET device, further improvements have been made to achieve the reverse freewheeling capability, greatly enriching the device's circuit application scenarios and reducing application costs.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A low on-resistance silicon carbide accumulation-type field-effect transistor, characterized in that it comprises:

[0007] A first conductivity type heavily doped silicon carbide substrate 1, a metallized drain 8 located below the first conductivity type heavily doped silicon carbide substrate 1 and the two forming an ohmic contact, a first conductivity type lightly doped silicon carbide region 2 located above the first conductivity type heavily doped silicon carbide substrate 1, and a metallized source 7 located above the first conductivity type lightly doped silicon carbide region 2.

[0008] Within the first conductivity type lightly doped silicon carbide region 2, there are two second conductivity type doped silicon carbide regions 3, four second conductivity type heavily doped polysilicon gates or nickel oxide gates 4, and three first conductivity type heavily doped silicon carbide regions 5. The four second conductivity type heavily doped polysilicon gates or nickel oxide gates are arranged at equal intervals, and each second conductivity type heavily doped polysilicon gate or nickel oxide gate is wrapped in a gate oxide layer 6. The three first conductivity type heavily doped silicon carbide regions are respectively disposed between adjacent gate oxide layers, and each of them forms an ohmic contact with the metallization source above. The two second conductivity type doped silicon carbide regions are respectively disposed below the gate oxide layers on both sides.

[0009] Furthermore, a Schottky metal region 9 is disposed between the second conductivity type doped silicon carbide region 3 and the gate oxide layer above it. The Schottky metal region 9 is connected to the metallization source and forms a Schottky barrier diode with the first conductivity type lightly doped silicon carbide region 2.

[0010] Furthermore, a silicon region is provided between the second conductivity type doped silicon carbide region 3 and the gate oxide layer above it. The silicon region and the first conductivity type lightly doped silicon carbide region 2 form a silicon / silicon carbide heterojunction diode, and a metallized source electrode is provided on the outer surface of the silicon region.

[0011] Furthermore, a polycrystalline silicon region is disposed between the second conductivity type doped silicon carbide region 3 and the gate oxide layer above it. The polycrystalline silicon region and the first conductivity type lightly doped silicon carbide region 2 form a polycrystalline silicon / silicon carbide heterojunction diode, and a metallized source electrode is disposed on the outer surface of the polycrystalline silicon region.

[0012] It should be noted that among all the devices mentioned above, the first conductivity type is N-type and the second conductivity type is P-type; the first conductivity type and the second conductivity type can be switched between each other according to design requirements.

[0013] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0014] This invention provides normally-off high-voltage silicon carbide accumulator field-effect transistors with low specific on-resistance, normally-off high-voltage silicon carbide accumulator field-effect transistors with low specific on-resistance and integrated Schottky barrier diodes, and normally-off high-voltage silicon carbide accumulator field-effect transistors with low specific on-resistance and integrated silicon / silicon carbide or polysilicon / silicon carbide heterojunction diodes. These structures, by utilizing the accumulation layer as a conductive channel, greatly reduce the specific on-resistance of the device while maintaining the same voltage rating as traditional silicon carbide MOSFETs, and significantly improve the trade-off between the breakdown voltage and specific on-resistance of power devices. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the cell (cross-sectional) structure of the normally off, low specific on-resistance high-voltage silicon carbide accumulation field-effect transistor in Embodiment 1 of the present invention.

[0016] Figure 2 This is a schematic diagram of the cell (cross-sectional) structure of the normally off, low specific on-resistance high-voltage silicon carbide accumulation field-effect transistor in Embodiment 2 of the present invention.

[0017] Figure 3 This is a schematic diagram of the cell (cross-sectional) structure of the normally off, low specific on-resistance high-voltage silicon carbide accumulation field-effect transistor in Embodiment 3 of the present invention.

[0018] Wherein, 1 is an N-type heavily doped silicon carbide substrate, 2 is an N-type lightly doped silicon carbide region, 3 is a P-type doped silicon carbide region, 4 is a P-type heavily doped polysilicon gate, 5 is an N-type heavily doped silicon carbide region, 6 is a gate oxide layer, 7 is a metallized source (S), 8 is a metallized drain (D), 9 is a Schottky metal region, and 10 is a silicon / polysilicon region. Detailed Implementation

[0019] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be described clearly and completely below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some implementations of this invention, and not all implementations.

[0020] Example 1

[0021] This embodiment provides a silicon carbide accumulation field-effect transistor with low on-resistance when normally off, and its cell structure is as follows: Figure 1 As shown, it specifically includes:

[0022] N-type heavily doped silicon carbide substrate 1, a metallized drain 8 (D) located below the N-type heavily doped silicon carbide substrate 1 and the two forming an ohmic contact, an N-type lightly doped silicon carbide region 2 located above the N-type heavily doped silicon carbide substrate 1, and a metallized source 7 (S) located above the N-type lightly doped silicon carbide region 2.

[0023] The N-type lightly doped silicon carbide region 2 contains two P-type doped silicon carbide regions 3, four P-type heavily doped polysilicon gates 4 (G), and three N-type heavily doped silicon carbide regions 5. The four P-type heavily doped polysilicon gates are arranged at equal intervals, and each P-type heavily doped polysilicon gate is encapsulated in a gate oxide layer 6. The three N-type heavily doped silicon carbide regions are respectively disposed between adjacent gate oxide layers, and each of them forms an ohmic contact with the metallization source above. The two P-type doped silicon carbide regions are respectively disposed below the gate oxide layers located on both sides.

[0024] It should be noted that, as Figure 1 The diagram shown is only a schematic of the cell structure. Considering a complete cell, the gates on the left and right sides are half of the complete gate in the diagram. Here, d1 represents the spacing between adjacent gate oxide layers, which is the channel width of the device, and d2 represents the width of the gate oxide layer that encloses the P-type heavily doped polysilicon gate.

[0025] The working principle of this embodiment is as follows: When the device is in the reverse off state, the four P-type heavily doped polysilicon gates (G) cause the energy band of the N-type lightly doped silicon carbide region (i.e., the device channel region) between adjacent P-type heavily doped polysilicon gates to bend, thereby establishing an electron potential barrier and blocking the flow of electrons from the source (S) to the drain (D), thus achieving the normally off capability of the device. Furthermore, the two P-type doped silicon carbide regions located within the N-type lightly doped silicon carbide region will deplete the N-type lightly doped silicon carbide region between them. Through reasonable design of the channel width d1 and the gate width d2, it can be ensured that when an ultra-high potential is applied to the drain (d), no high potential is imparted to the channel, thereby causing a non-ideal turn-on of the device. When the device is in the forward conduction state, a forward gate voltage higher than the threshold is applied to the polysilicon gate, and the energy band of the channel region bends into an electron potential well, thereby forming a high-mobility electron accumulation layer, and electrons flow from the source (S) to the drain (D).

[0026] Simulation results show that for devices with a voltage rating of 1200V, the silicon carbide accumulation MOSFET device proposed in this embodiment can achieve a forward threshold voltage greater than 1V; compared with traditional SiC MOSFET devices of the same voltage rating, the on-resistance is reduced by more than 60%.

[0027] Example 2

[0028] This embodiment provides a silicon carbide accumulation field-effect transistor with low on-resistance when normally off, and its cell structure is as follows: Figure 2 As shown; its only difference from Embodiment 1 is that: an integrated Schottky barrier diode is provided, specifically: a Schottky metal region 9 is also provided between the P-type doped silicon carbide region 3 and the gate oxide layer above it, the Schottky metal region 9 is connected to the metallization source 7 (S) and forms a Schottky barrier diode with the N-type lightly doped silicon carbide region 2.

[0029] The working principle of this embodiment is as follows: When the device is in the reverse turn-off state, the four P-type heavily doped polysilicon gates (G) cause the energy band of the N-type lightly doped silicon carbide region (i.e., the device channel region) between adjacent P-type heavily doped polysilicon gates to bend, thereby establishing an electron potential barrier and blocking the flow of electrons from the source (S) to the drain (D). At the same time, electrons are also blocked by the Schottky barrier formed by the Schottky metal region (metal source) and the N-type lightly doped silicon carbide region, jointly realizing the normally off capability of the device. Furthermore, the two P-type doped silicon carbide regions located in the N-type lightly doped silicon carbide region will deplete the N-type lightly doped silicon carbide region between them. Through the reasonable design of the channel width d1 and the gate width d2, it can be ensured that when an ultra-high potential is applied to the drain (d), no high potential is imparted to the channel, thereby causing a non-ideal turn-on of the device. When the device is in the forward conduction state, a forward gate voltage higher than the threshold is applied to the polysilicon gate, causing the energy band in the channel region to bend into an electron potential well, thereby forming a high-mobility electron accumulation layer, with electrons flowing from the source (S) to the drain (D). When the device is in the reverse conduction state, electrons flow from the drain (D) to the Schottky metal region (metal source), realizing the device's reverse freewheeling capability.

[0030] Simulation results show that the silicon carbide accumulator MOSFET proposed in this embodiment can achieve a forward threshold voltage greater than 1 V; compared with traditional SiC MOSFET devices of the same withstand voltage level (such as 1200V), the specific on-resistance is reduced by more than 60%; the integrated Schottky barrier diode realizes the reverse freewheeling capability of the silicon carbide accumulator MOSFET, and compared with the body diode of traditional SiC MOSFET devices, it achieves better reverse freewheeling capability due to the absence of minority carrier injection.

[0031] Example 3

[0032] This embodiment provides a silicon carbide accumulation field-effect transistor with low on-resistance when normally off, and its cell structure is as follows: Figure 3 As shown; its only difference from Embodiment 1 is that: it integrates a silicon / silicon carbide or polysilicon / silicon carbide heterojunction diode, specifically: a silicon or polysilicon region 10 is also provided between the P-type doped silicon carbide region 3 and the gate oxide layer above it, the silicon and the N-type lightly doped silicon carbide region 2 form a silicon / silicon carbide heterojunction diode, or the polysilicon and the N-type lightly doped silicon carbide region 2 form a polysilicon / silicon carbide heterojunction diode, and a metallized source (S) is provided on the outer surface of the silicon or polysilicon region.

[0033] The working principle of this embodiment is as follows: When the device is in the reverse turn-off state, the four P-type heavily doped polysilicon gates (G) cause the energy band of the N-type lightly doped silicon carbide region (i.e., the device channel region) between adjacent P-type heavily doped polysilicon gates to bend, thereby establishing an electron barrier and blocking the flow of electrons from the source (S) to the drain (D). At the same time, electrons are also blocked by the silicon / silicon carbide heterojunction barrier or the polysilicon / silicon carbide heterojunction barrier, which together realize the normally-off capability of the device. Furthermore, the two P-type doped silicon carbide regions located in the N-type lightly doped silicon carbide region will deplete the N-type lightly doped silicon carbide region between them. Through the reasonable design of the channel width d1 and the gate width d2, it can be ensured that when an ultra-high potential is applied to the drain (d), no high potential is imparted to the channel, thereby causing a non-ideal turn-on of the device. When the device is in the forward conduction state, a forward gate voltage higher than the threshold is applied to the polysilicon gate, causing the energy band in the channel region to bend into an electron potential well, thereby forming a high-mobility electron accumulation layer, with electrons flowing from the source (S) to the drain (D). When the device is in the reverse conduction state, electrons flow from the drain (D) to the metallized source on the outer surface of the silicon or polysilicon region, realizing the reverse freewheeling capability of the device.

[0034] Simulation results show that the silicon carbide accumulation MOSFET proposed in this embodiment can achieve a forward threshold voltage greater than 1 V; compared with traditional SiC MOSFET devices of the same withstand voltage level (such as 1200V), the specific on-resistance is reduced by more than 60%; the integrated silicon / silicon carbide or polysilicon / silicon carbide heterojunction realizes the reverse freewheeling capability of the silicon carbide accumulation MOSFET.

[0035] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A low specific on-resistance silicon carbide field effect transistor, characterized by, include: A first conductivity type heavily doped silicon carbide substrate (1), a metallized drain (8) located below the first conductivity type heavily doped silicon carbide substrate (1) and the two forming an ohmic contact, a first conductivity type lightly doped silicon carbide region (2) located above the first conductivity type heavily doped silicon carbide substrate (1), and a metallized source (7) located above the first conductivity type lightly doped silicon carbide region (2). The first conductivity type lightly doped silicon carbide region (2) is provided with two second conductivity type doped silicon carbide regions (3), four second conductivity type heavily doped polysilicon gates (4) and three first conductivity type heavily doped silicon carbide regions (5). The four second conductivity type heavily doped polysilicon gates are arranged at equal intervals and each second conductivity type heavily doped polysilicon gate is wrapped in a gate oxide layer (6). The three first conductivity type heavily doped silicon carbide regions are respectively disposed between adjacent gate oxide layers and form ohmic contact with the metallization source above. The two second conductivity type doped silicon carbide regions are respectively disposed below the gate oxide layers on both sides. A Schottky metal region (9) is also provided between the second conductivity type doped silicon carbide region (3) and the gate oxide layer above it. The Schottky metal region (9) is connected to the metallization source and forms a Schottky barrier diode with the first conductivity type lightly doped silicon carbide region (2).

2. A low specific on-resistance silicon carbide field effect transistor, characterized by include: A first conductivity type heavily doped silicon carbide substrate (1), a metallized drain (8) located below the first conductivity type heavily doped silicon carbide substrate (1) and the two forming an ohmic contact, a first conductivity type lightly doped silicon carbide region (2) located above the first conductivity type heavily doped silicon carbide substrate (1), and a metallized source (7) located above the first conductivity type lightly doped silicon carbide region (2). The first conductivity type lightly doped silicon carbide region (2) is provided with two second conductivity type doped silicon carbide regions (3), four second conductivity type heavily doped polysilicon gates (4) and three first conductivity type heavily doped silicon carbide regions (5). The four second conductivity type heavily doped polysilicon gates are arranged at equal intervals and each second conductivity type heavily doped polysilicon gate is wrapped in a gate oxide layer (6). The three first conductivity type heavily doped silicon carbide regions are respectively disposed between adjacent gate oxide layers and form ohmic contact with the metallization source above. The two second conductivity type doped silicon carbide regions are respectively disposed below the gate oxide layers on both sides. A silicon region is also provided between the second conductivity type doped silicon carbide region (3) and the gate oxide layer above it. The silicon region and the first conductivity type lightly doped silicon carbide region (2) form a silicon / silicon carbide heterojunction diode. A metallized source electrode is provided on the outer surface of the silicon region.

3. A low specific on-resistance silicon carbide field effect transistor, characterized by include: A first conductivity type heavily doped silicon carbide substrate (1), a metallized drain (8) located below the first conductivity type heavily doped silicon carbide substrate (1) and the two forming an ohmic contact, a first conductivity type lightly doped silicon carbide region (2) located above the first conductivity type heavily doped silicon carbide substrate (1), and a metallized source (7) located above the first conductivity type lightly doped silicon carbide region (2). The first conductivity type lightly doped silicon carbide region (2) is provided with two second conductivity type doped silicon carbide regions (3), four second conductivity type heavily doped polysilicon gates (4) and three first conductivity type heavily doped silicon carbide regions (5). The four second conductivity type heavily doped polysilicon gates are arranged at equal intervals and each second conductivity type heavily doped polysilicon gate is wrapped in a gate oxide layer (6). The three first conductivity type heavily doped silicon carbide regions are respectively disposed between adjacent gate oxide layers and form ohmic contact with the metallization source above. The two second conductivity type doped silicon carbide regions are respectively disposed below the gate oxide layers on both sides. A polycrystalline silicon region is provided between the second conductivity type doped silicon carbide region (3) and the gate oxide layer above it. The polycrystalline silicon region and the first conductivity type lightly doped silicon carbide region (2) form a polycrystalline silicon / silicon carbide heterojunction diode. A metallized source electrode is provided on the outer surface of the polycrystalline silicon region.

4. The low on-resistance silicon carbide field-effect transistor according to any one of claims 1, 2, and 3, characterized in that, The second conductivity type of heavily doped polysilicon gate (4) is replaced with a nickel oxide gate.

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